SU148965A1 - Arithmetic device of a digital differential analyzer - Google Patents

Description

Known arithmetic devices of digital differential analyzers of the sequential type, containing one-digit adders and gates. The known digital differential analyzers (CDL) work in various number systems - binary or binary-decimal. However, the arithmetic and logical devices of these ZDLs are sharply different, which precludes a transition within the DLC from an account using One Number system to another account.

In the proposed device, in order to ensure the transition from the binary number calculation to the binary number binary, when performing actions in integrators, the result correction scheme is applied to "3 in the presence of a decimal i-on transfer in its absence. The circuit consists of four gates, one collective circuit and a trigger for the signs of the number system, a single output of which (TPS), connected to the correction circuit, is connected to the input through one of the single-bit adders.

On f-ig. 1 shows a scheme for summing numbers; in fig. 2 is a table explaining the selection of time pulses that i-execute -correction.

The addition of codes is performed in the following sequence. First, the digits of each decimal digit are added as two four-bit binary numbers. The addition is performed by a one-bit adder (Sma}. After adding the decimal digits as binary codes, the result is corrected, for which the second adder (Smb) is used.

Corrections are made according to the following rule. If the transfer from the .distribute bit (from the fourth binary bit) is absent, then the number ' 13 (code 1101) is added to the resulting amount. If there is a transfer, then the number "3 (UN code) is added to the amount received.

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/ JeficTBHf correction of spears from additional time impulses alternating with an interval of 4 cycles (4 tons). When the subtraction is performed, the code of the Sma adder (input R) that is being scanned to the second input is received with the interworking of the binary bits. The inversion control is determined by the state of the storage cell 7 i (the trigger of word lay and subtraction).

FIG. I also denotes valves and delay lines t, as well as a trigger of the NSG number system, included in the correction circuit.

Subject invention

An arithmetic unit of a digital differential analyzer of the sequential type, containing one-digit adders and gates, from the LR and KSHTES - that, in order to ensure the transition from the Binary system of C 1M1 to CAL with the binary-decimal system without changing other analyzer devices, It applied the result correction scheme to "3 in the presence of a decimal transfer and on" 13 in its absence, consisting of four gates, an entire collective circuit and a trigger of the notation system signs, a single output which, via one of the valves connected to the correction circuit, is connected to the input of a one-sided adder.

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