JP3280470B2 - Error correction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the decoding of a double error-correcting (n, k) BCH code having α as a primitive element of the Galois extension field GF (2 ^m ) of order ^m and α and α ³ as roots. And an error correction circuit for performing the correction.

[0002]

2. Description of the Related Art A t-bit corrected BCH (Bose-Chauduri-Ho)
cqenghem Codes) For code parameters, code length n
Is n = 2 ^m -1 (1), the number of information k is k ≧ n-mt (2), and the BCH code of such a code length n and the number of information k is (n, k) Called BCH code.

[0003] Among error correction codes, the BCH code is extremely important in practical use, and is widely used in the fields of communication and recording. Among them, the double error correction code is
The relationship between the error locator polynomial coefficient used in decoding and the syndrome has been clarified, and it is relatively easy to consider hardware. However, the decoding requires addition, multiplication, and division operations on the Galois field. Therefore, in the prior art, (a) exponent ← → vector representation, inverse element, etc. are stored in a read-only memory. , An external access, or (b) a configuration in which a syndrome and an error position are obtained in a table and the read-only memory is accessed from the outside in the same manner. In such prior art, when hardware is used, a large memory capacity is required for the read-only memory, and the cost is high relative to the number of corrections.

For example, in the prior art shown in FIG. 19, a register 2 of a syndrome S1 to which a BCH code signal is supplied from a line 1, a register 3 of a syndrome S3, and a read-only memory 4 are provided, and the received BCH code signal is provided. Is provided, and an exclusive OR gate circuit 6 for deriving a corrected BCH code signal is provided. The prior art shown in FIG. 19 realizes the above-described prior art (b),
As described above, there is a problem that the memory capacity of the read-only memory 4 needs to be increased.

[0005]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an error correction circuit capable of realizing operations such as addition, multiplication and division on a Galois extended field GF (2 ^m ) with a simple configuration. To provide.

Conventionally, a chain search method has been used to derive an error position. In a configuration for realizing this method, there is a problem that an external clock signal is required and real-time processing cannot be performed.

It is another object of the present invention to provide an error correction circuit which can search for an error position while reading a BCH code signal.

[0008]

SUMMARY OF THE INVENTION The present invention provides (a) BCH
A first syndrome register 9 for dividing the code signal by (x-α) to find a first syndrome S1; and (b) dividing the BCH code signal by (x-α ³ ) to find a second syndrome S3. A second syndrome register 10; and (c) a coefficient deriving circuit 12 for an error locator polynomial, wherein (c1) α is a primitive element of an m-th order Galois extended field GF (2 ^m ), and α and α ³ are roots. Double error correction (n, k) BC
In decoding the H code, (2 ^m -1) first α multipliers MX1 to MXi are connected in series, and the first stage first α multiplier M
By giving α0 to X1, the ^element αα of GF (2 ^m )
(c2) responding to the first syndrome S1 and the output of the element creation circuit 19, which creates α (2 ^m -1) (hereinafter, α represents the power of (2 ^m -1)); A power circuit 21 for calculating S1α to S1α (2 ^m -1), wherein (2 ^m -1) first adders AD
0 to ADi, and each of the adders AD0 to ADi is a first exclusive OR gate to which each bit a0 to a3 of S1 and each bit b0 to b3 of α1 to α (2 ^m -1) are given. E
R0 to ER3 and these first exclusive OR gates ER
0 to ER3 are applied to first NAND gate G0
And the first adders AD0 to ADi output L0 to L0.
A power circuit 21 for deriving a li, (c3) a first syndrome S1 and the GF (2 ^m) on the (2 ^m
-1) a first multiplication circuit 23 for multiplying the elements,
(C 4) a first multiplication circuit 23 that connects the (2 ^m −1) second α multipliers MX11 to MX1i in series and provides the first syndrome S1 to the first-stage second α multiplier MX11; results and, based on the result of the exponentiation circuit 21, obtains the S1 ² S1 ² search circuit 2
A first AND gate G10 to which the outputs of the second α multipliers MX11 to MX1i and the outputs L0 to Li of the first adders AD0 to ADi of the power circuit 21 are provided.
~G1i and, the output of the 1AND gate G10~G1i is given, a second exclusive-OR gate E outputs the S1 ²
And S1 ² search circuit 22 and a R10, (c5) S1 a inverse search circuit 25 for obtaining the inverse of, (2 ^m -1) pieces of third exclusive OR gate ER30
ER3i, each of the third exclusive OR gates ER3
⁰ to ER3i are supplied with α ⁰ and the outputs of the second multipliers MX11 to MX1i of the first multiplier circuit 23. The third exclusive OR gates ER30 to ER3i and the third exclusive OR gate ER30 to An inverse element search circuit 25 having all-zero detection circuits AZ0 to AZi realized by a NAND gate for detecting that all bits of each output of ER3i become logic "0"; (c6) second syndromes S3 and GF (2 ^m) on the (2 ^m
-1) a second multiplication circuit 27 for multiplying the elements,
A second multiplier circuit 27 that connects (2 ^m −1) third α multipliers MX21 to MX2i in series and provides a second syndrome S3 to the first-stage third α multiplier MX21; and (c7) a second multiplier circuit 27. Result and inverse element search circuit 25
S3 / S1 to obtain S3 / S1 based on the result from
(C7-1) (2 ^m -1) second AND gates G20
To G2i, each of the second AND gates G20 to G2i.
Are all zero detection circuits AZ0 to AZ of the inverse element search circuit 25.
i and the third α of the second multiplying circuit 27
A second AND gate G20 to G2i to which the output from the multipliers MX21 to MX2i is applied; and (c7-2) a fourth exclusive OR gate to which the output of the second AND gate G20 to G2i is applied to derive S3 / S1. and S3 / S1 search circuit 26 and a ER5, adds the result of (c8) S1 ² and S3 / S1 circuit 2
A 8, S1 ² second exclusive logical output S1 ² of OR gate ER10, S3 / S1 output S3 / S1 of the fourth exclusive OR gate ER5 the search circuit 26 of the search circuit 22
Is given for each bit, and (S1 ² + S3 / S1)
EXCLUSIVE-OR Gates ER60 to ER63 for Outputting
An error locator polynomial coefficient derivation circuit 12 including: an adder circuit 28 having: (d) a chain search circuit 13 for performing a chain search in response to an output of the error locator polynomial coefficient derivation circuit and representing an error position; (E) a register 11 for receiving and storing the BCH code signal, and (f) a calculation circuit 14 for calculating the output of the chain search circuit and the output of the data register to obtain a corrected BCH code signal.
And an error correction circuit comprising:

The present invention also provides (a) a first syndrome register 9 for dividing a BCH code signal by (x-α) to obtain a first syndrome S1, and (b) converting the BCH code signal to (x-α ³ And (c) a coefficient derivation circuit 12 for the error locator polynomial, wherein (c1) α is an m-th order Galois extended field GF (2 ^m ) Error correction (n, k) BC with α, α ³ as roots
In decoding the H code, (2 ^m -1) first α multipliers MX1 to MXi are connected in series, and the first stage first α multiplier M
By giving α0 to X1, the ^element αα of GF (2 ^m )
(c2) responding to the first syndrome S1 and the output of the element creation circuit 19, which creates α (2 ^m -1) (hereinafter, α represents the power of (2 ^m -1)); A power circuit 21 for calculating S1α to S1α (2 ^m -1), wherein (2 ^m -1) first adders AD
0 to ADi, and each of the adders AD0 to ADi is a first exclusive OR gate to which each bit a0 to a3 of S1 and each bit b0 to b3 of α1 to α (2 ^m -1) are given. E
R0 to ER3 and these first exclusive OR gates ER
0 to ER3 are applied to first NAND gate G0
And the first adders AD0 to ADi output L0 to L0.
A power circuit 21 for deriving a li, (c3) a first syndrome S1 and the GF (2 ^m) on the (2 ^m
-1) a first multiplication circuit 23 for multiplying the elements,
(C 4) a first multiplication circuit 23 that connects the (2 ^m −1) second α multipliers MX11 to MX1i in series and provides the first syndrome S1 to the first-stage second α multiplier MX11; results and, based on the result of the exponentiation circuit 21, obtains the S1 ² S1 ² search circuit 2
A first AND gate G10 to which the outputs of the second α multipliers MX11 to MX1i and the outputs L0 to Li of the first adders AD0 to ADi of the power circuit 21 are provided.
~G1i and, the output of the 1AND gate G10~G1i is given, a second exclusive-OR gate E outputs the S1 ²
And S1 ² search circuit 22 and a R10, (c5) S1 a inverse search circuit 25 for obtaining the inverse of, (2 ^m -1) pieces of third exclusive OR gate ER30
ER3i, each of the third exclusive OR gates ER3
⁰ to ER3i are supplied with α ⁰ and the outputs of the second multipliers MX11 to MX1i of the first multiplier circuit 23. The third exclusive OR gates ER30 to ER3i and the third exclusive OR gate ER30 to An inverse element search circuit 25 having all-zero detection circuits AZ0 to AZi realized by a NAND gate for detecting that all bits of each output of ER3i become logic "0"; (c6) second syndromes S3 and GF (2 ^m) on the (2 ^m
-1) a second multiplication circuit 27 for multiplying the elements,
A second multiplier circuit 27 that connects (2 ^m −1) third α multipliers MX21 to MX2i in series and provides a second syndrome S3 to the first-stage third α multiplier MX21; and (c7) a second multiplier circuit 27. Result and inverse element search circuit 25
S3 / S1 to obtain S3 / S1 based on the result from
(C7-1) (2 ^m -1) second AND gates G20
To G2i, each of the second AND gates G20 to G2i.
Are all zero detection circuits AZ0 to AZ of the inverse element search circuit 25.
i and the third α of the second multiplying circuit 27
A second AND gate G20 to G2i to which the output from the multipliers MX21 to MX2i is applied; and (c7-2) a fourth exclusive OR gate to which the output of the second AND gate G20 to G2i is applied to derive S3 / S1. and S3 / S1 search circuit 26 and a ER5, adds the result of (c8) S1 ² and S3 / S1 circuit 2
A 8, S1 ² second exclusive logical output S1 ² of OR gate ER10, S3 / S1 output S3 / S1 of the fourth exclusive OR gate ER5 the search circuit 26 of the search circuit 22
Is given for each bit, and (S1 ² + S3 / S1)
EXCLUSIVE-OR Gates ER60 to ER63 for Outputting
And (d) an error position detection circuit, wherein (d1) the error position polynomial is σ (z) = 1 + Az + Bz ² . Then, (2 ^m −2) fourth α multipliers MX31 to MX31
MX3i are connected in series, and a first-stage fourth α multiplier MX31
The second exclusive OR gate E of the S1 ² search circuit 22
By giving A which is the output S1 ² of R10, Aα ⁱ
The first arithmetic circuit 41 that outputs (i = 0, 1, 2,..., 2 ^m −2) is connected in series with (d2) (2 ^m −2) fifth α multipliers, and the first stage 5α to the multiplier, the output from the fifth exclusive OR gate ER60~ER63 of the adder circuit 28 (S1 ² +
S3 / S1) to give Bα ^j (j
= 0,1,2, ..., the second arithmetic circuit 42 for outputting a ^{2 m -2), (d3)} Bα k (k = 0,1,2, ..., 2 m -2) to the 6α multiplier MX41; MX51, MX52; MX6
, MX62, MX63; are connected to each other to output B (α ^k ) ^2. (D4) Based on the outputs of the first and third arithmetic circuits 41 and 43, A circuit for determining ^L where the error locator polynomial is σ (α ^L ) = 0 (L = 0, 1, 2,..., 2 ^m −2) and deriving an output indicating the error position of the received codeword 44, Aα ⁱ and B (α ⁱ )
² (i = 0, 1,..., 2 ^m −2) are provided, and the third adders AD10 to AD1i are provided.
D1i is, A.alpha ⁱ and B (α ⁱ⁾ for each bit, each bit of ² is given sixth exclusive OR gates ER70~E
R7 _m-1 and bits a1 to am _-1 , b1 after the second bit
Sixth exclusive OR gates ~b _m-1 is given ER71
To the output of ER7 _m-1
And an error position indication output deriving circuit 44 having an AND gate G2 to which an output of the sixth exclusive OR gate ER70 to which the first bits a0 and b0 are applied and an output of the second NAND gate G3. A detection circuit 53; (e) a correction control circuit 17 for clearing a correction output when S1 = 0, S3 ≠ 0, assuming that an uncorrectable error has occurred;
(F) storing the BCH code signal, performing correction by the output of the error position detection circuit and the correction control circuit, and correcting the corrected BC
An error correction circuit including a data register for obtaining an H code signal.

[0010]

[0011]

[0012]

Operation The error locator polynomial derivation circuit will be described first. The double error correcting BCH code is a Galois extended field GF (2
^When α in ^m ) is a primitive element, it has α and α ³ as roots. Now, when the error positions are L1 and L2, the syndrome S
1, S3 becomes ^{S1 = α L1 + α L2 ...} (3) S3 = α 3L1 + α 3L2 ... (4). Error position polynomial using this, the σ (x) = 1 + S1x + (S1 2 + S3 / S1) x 2 ... (5). Since the coefficient S1 of x has been obtained, (S1 ²
+ S3 / S1). Conventionally, this calculation uses R
References were made by OM. But it is difficult operations directly S1 ² and S3 / S1 by the gate circuit. Therefore, the present invention is configured as follows.

[0013] First, an S1 ^2, S1 is either Galois extension field GF (2 ^m) on the (2 ^m -1) of the number of elements. Therefore, by connecting (2 ^m -1) α multiplication circuits MX1 to MXi in series,

[0014]

(Equation 1)

By obtaining the [0015] S1 ² is any of this. Assuming that S1 = alpha ^i, since it is ^{S1 2 = S1α i mod 2 m} -1 ... (6), of the group GR1, the calculation result of alpha ⁱ is S1 ^2. In the above equation 6, mod means taking the remainder obtained by dividing the operation result of the original exponent by 2 ^m -1.

On the other hand, to calculate S3 / S1, it is necessary to find the inverse of S1. When the same manner as described above S1 = alpha ^i, inverse alpha ^j of alpha ⁱ serves as a ^{α i · α j = α o} mod 2 m -1 ... (7), whereby, S3 / S1 is , S3 / S1 = S3 · α− ⁱ = S3 · ^αj mod 2 ^m −1 (8)

First, similarly to the aforementioned group GR1,

[0018]

(Equation 2)

## EQU1 ## And Find ^{S1α j = α o mod 2 m} -1 ... to become α ^j (9) from the group GR1. Then, since α ^j is the inverse element of S1, S3 / S1 is the result of multiplying S3 by α ^j in group GR2.

S1 ² and S3 /
If added to S1, it is the coefficient for x ² of Formula 5.

Next, the error position detecting circuit will be described.

When σ (α ⁱ ) = 0 (i = 0, 1,..., 2 ^m −2)... (10) with respect to equation (5) above, j = i + j mod 2 ^m −1 = 0 Indicates the location of the error. Therefore, in deriving the error position, α ⁱ (i = 1, 2,..., 2 ^m −2) is sequentially substituted, and σ
It is sufficient to check (α ⁱ ) = 0.

To implement this in hardware, a chain search method is used, but a clock for the code length is required. Therefore, the present invention is as follows.

First, for A and B, an α multiplication circuit is set to 2 ^m −
By inputting two in series

[0025]

(Equation 3)

Can be calculated simultaneously. Aα ⁰ and Bα ⁰ are
Consider A and B themselves.

The above-mentioned group GR3 is obtained by calculating the second item of Expression 5 for all α ⁱ (i = 0, 1,..., 2 ^m −2). However, to find the three items in Equation 5,
The square of α ⁱ (i = 0, 1,..., 2 ^m −2) is required.

According to the present invention, Bα of the aforementioned group GR4
^{For i} (i = 0, 1,..., 2 ^m −2), by connecting i multipliers in series, (Bα ⁱ ) · α ⁱ = B (α ⁱ ) ² (i = 0, 1 , ..., ^2m- 2) ... (11).

Aα ⁱ , B (α ⁱ ) ² (i = 0, 1,..., 2 ^m
Since −2) was calculated, this is added for each i, and 1 + Aα ⁱ + B (α ⁱ ) ² = 0 (12) Then, j satisfying i + j mod 2 ^m -1 indicates the position of the error.

The above operation is performed for all α ⁱ (i = 0, 1,
, 2 ^m -2) are simultaneously performed, so that an error position can be searched at high speed.

[0031]

FIG. 1 is a block diagram showing an entire configuration of an error correction circuit according to one embodiment of the present invention. The BCH code signal is input from a line 8 and is divided by (x-α) to obtain a syndrome S1. An m-bit syndrome register 9 is used to divide the BCH code signal by (x-α ³ ) to generate a syndrome S3. This is supplied to the m-bit syndrome register 10 to be obtained. The error correction circuit includes an n-bit data register 11 to which a BCH code signal is applied, and a coefficient derivation circuit 12 of an error locator polynomial to which syndromes S1 and S3 from the syndrome registers 9 and 10 are respectively provided. Can be The output S of the coefficient derivation circuit 12 for the error locator polynomial
1, S1 ² + S3 / S1 is applied to the chain search circuit 13, and the exclusive OR gate 14 is connected to the chain search circuit 13
And the output of the data register 11 are operated to obtain a corrected BCH code signal. When the n-bit code word is read in this way, the syndromes S1 and S3 are calculated by the syndrome registers 9 and 10, and the coefficients of the error locator polynomial are also calculated at the same time. Then, α ^-i (i
= 0, 1,..., 2 ^m −2), and σ (α ⁱ )
I where = 0 indicates an error position. This calculation can be easily realized by the chain search circuit 13. The chain search circuit is disclosed, for example, in "Code Theory", page 166, written by Hideki Imai.

FIG. 2 is a block diagram showing the entire configuration of an error correction circuit according to another embodiment of the present invention. This embodiment is similar to the embodiment shown in FIG. 1 and corresponding parts are denoted by the same reference numerals. In this embodiment, an error position detection circuit 53 is provided instead of using the chain search circuit 13 described above. From the error locator polynomial coefficient deriving circuit 12, a signal for clearing the corrected output on the line 16 is determined as having an uncorrectable error when S1 = 0 and S3 ≠ 0, and is supplied to the correction control circuit 17. This correction control circuit 17
Is provided to the data register 18 of the received codeword. According to the configuration shown in FIG. 2, there is no need to use the chain search circuit 13 in the embodiment shown in FIG. 1, and therefore, the external clock signal required in the chain search circuit is not used in the embodiment shown in FIG. This is not necessary, and the error position can be detected in real time.

FIG. 3 is a block diagram showing a specific configuration of the error derivation polynomial coefficient derivation circuit 12 in each of the embodiments shown in FIGS. The element creation circuit 19 is a circuit that represents all elements of the m-th order Galois extended field GF (2 ^m ).
The element creation circuit 19 includes (2 ^m -1) α multipliers MX
1 to MXi are connected in series.
Double arrows in FIG. 3 and other drawings indicate the flow of m-bit parallel data on the Galois extended field GF (2 ^m ).

FIG. 4 shows a specific configuration of the α multiplier MX1, which shows a configuration in the (15,7) BCH code (m = 4). The α multiplier MX1 includes the exclusive OR gate 20, and can be realized by a simple configuration by using an adjoint matrix.

The power circuit 21 is for multiplying the original on the syndrome S1 and the Galois extension field GF (2 ^m), look for whether the syndrome S1 is equal to any original on Galois extension field GF (2 ^m) Work.

FIG. 5 is a block diagram showing a specific configuration of the power circuit 21. The exponentiation circuit 21 has adders AD0 to ADi, and S1 = (a _m−1 ,..., A ₀ ), α
^{When i} = (b _m−1 ,..., b ₀ ), a configuration for finding α ^{i such} that a ⁱ = (bi) (i = 0, 1, 2,..., m−1) (14) That is what we need to do.

FIG. 6 shows a specific configuration of the adder AD0. The adder AD0 outputs the bits a0 to a3, b0 to b3
Is calculated by exclusive OR gates ER0 to ER3, and all outputs may be logic "0". In the configuration of FIG. 6,
The configuration in the (15, 7) BCH code (m = 4) is shown. The output of the exclusive OR gates ER0 to ER3 is NAN.
This is applied to D gate G0. Control signal at the output lines L0~Li of the adders AD0~ADi the control signal applied only to the S1 ² search circuit 22 to be described later for i to be S1 = α ⁱ ... (15) becomes a logic "1".

The first multiplication circuit 23 multiplies the syndrome S1 by (2 ^m -1) elements on the Galois extended field GF (2 ^m ). The first multiplying circuit 23 is realized by connecting (2 ^m -1) α multipliers MX11 and MX1i in series, and the configuration thereof is the same as that of the α multipliers MX1 to MX1
Same as Xi.

FIG. 7 is a block diagram showing a specific configuration of the S1 ² search circuit 22. This S1 ² search circuit 2
2 is based on the result of the first multiplying circuit 23 and the result of the exponentiation circuit 21 to obtain S1 ^2.
α ⁱ (i = 0, 1,..., 2 ^m −2) to select S1 ² , control signals for lines L0 to Li are given to AND gates G10 to G1i, and the first multiplication is performed. The outputs from the α multipliers MX11 to MX1i of the circuit 23 are respectively provided, and the outputs of the AND gates G10 to G1i are provided to the exclusive OR gate ER10. Is
S1 output ² is derived.

FIG. 8 is an electric circuit diagram more specifically showing a part of the S1 ² search circuit 22 shown in FIG.
When the (15, 7) BCH code (m = 4) is used, the above-mentioned AND gate G10 is connected to AND gates G20 to G23.
And exclusive-OR gates ER20 to ER
The output of each of the AND gates G20 to G23 and the output of an exclusive OR gate connected in connection with the next AND gate G11 are given to 23. Thus exclusive OR gates ER20~ER23 derives an output S1 ^2.

The S1 inverse element search circuit 25 calculates S1α ^k (i
= 0, 1,..., 2 ^m −2), S1α ⁱ = i ⁰ (16), that is, α ⁱ which is the inverse of S1 is obtained.

FIG. 9 is a block diagram showing a specific configuration of the S1 inverse search circuit 25. S1 inverse element search circuit 2
5 is similar to the S1 search circuit 22 shown in FIG. 7 described above, and when S1α ⁱ = (a _m−1 ,..., A ₀ ) and α ⁰ = (0,. Α ⁱ that satisfies 16 may be obtained. Therefore, each α multiplier MX11 of the first multiplication circuit 23
To MX1i are output from an exclusive OR gate ER30.
ER3i together with α ⁰ , that is, exclusive OR operation is performed on each bit, and all outputs are all zero detection circuit AZ0
ＡAZi, it is detected that the logic becomes “0”, and the output is derived from the lines L20 to L2i, respectively.

FIG. 10 is an electric circuit diagram showing a specific configuration of the exclusive OR gate ER30 and the all-zero detection circuit AZ0.

For signal processing of the (15, 7) BCH code (m = 4), the exclusive OR gate ER30 is provided with exclusive OR gates ER40 to ER44 for each bit and all zeros. The detection circuit AZ0 is realized by a NAND gate. The control signal applied to the S3 / S1 search circuit 26 described later becomes logic "1" only for i for which the above-mentioned Expression 16 holds.

The second multiplication circuit 27 multiplies the syndrome S3 by (2 ^m -1) elements of the Galois extended field GF (2 ^m ). The second multiplying circuit 27 includes α multipliers MX21 to MX21
2i, and the configuration is the same as that of the original creation circuit 19 described above.

The S3 / S1 search circuit 26 generates S3α
ⁱ (i = 0, 1,..., 2 ^m −2) is used to select an S3 / S1 operation result.

FIG. 11 is a block diagram showing the overall configuration of the S3 / S1 search circuit 26. The S3 / S1 search circuit 26 is similar to the configuration of the S1 ² search circuit 22 described above, and includes lines L20 to L2i of the S1 inverse search circuit 25.
And the α multipliers MX21 to MX2 of the second multiplication circuit 27
AND gates G20 to G2 supplied with respective outputs
i and an exclusive OR gate ER5, and S3 / S1 is derived from a line L30. That is, the control signal from the line L20~L21 is S3arufa ⁱ is S3 / S1 is a logic "1", only the output is selected.

[0048] S1 ² and the output S1 ² from the line L10 of the search circuit 22, S3 / S1 line L of the search circuit 26
The output S3 / S1 from the exclusive OR gate 2
8 to the adder circuit 28, which outputs (S1 ² + S3 / S1). The specific configuration of the exclusive OR gate 28 is (15,7) B
In the case of the CH code (m = 4), as shown in FIG.
This is realized by exclusive OR gates ER60 to ER63 for each bit. These exclusive OR gates ER6
The outputs of 0 to ER63 are derived from line L40,
(S1 ² + S3 / S1) is obtained.

FIG. 13 is a block diagram showing a specific configuration of the chain search circuit 13. As shown in FIG. The output S1 ² of the S1 ² search circuit 22 via the line L10 and the output of the exclusive OR gate 28 from the line L40 (S1 ² + S3 / S
1) are stored in m-bit data registers 29 and 30 in which those values are stored as initial values, respectively. A clock signal from a clock generator 31 realized by a counter is applied to these registers 29 and 30. Each register 29, 30 has an α multiplier 32
And α ² multiplier 33 are connected to form a closed loop 3
4 and 35 are provided, and their outputs are applied to an addition circuit 36 of a Galois extended field GF (2 ^m ) of order ^m, and an exclusive OR gate 1 shown in FIG.
4 given. The adding circuit 36 is realized by an exclusive OR gate.

The error position detection circuit 5 shown in FIG.
FIG. 14 shows a specific configuration of No. 3. The first arithmetic circuit 41, S1 ² is given from the error position polynomial coefficient derivation is included in circuit 12 S1 ² search circuit 22 via a line L10. This arithmetic circuit 41 is provided in FIG.
, The α multipliers MX31, MX32,.
MX3i is constituted by connecting in series, thus all ^{α i (i = 0,1, ...} , 2 m -2) performs calculation of A.alpha ⁱ relative to derive respective line L50～L5i.

Another arithmetic circuit 42 also has the same configuration as the above-described arithmetic circuit 41, and is connected to line L40 in exclusive OR gate 28 (see FIG. 3 described above) of error locator polynomial coefficient deriving circuit 12. Of (S1 ² + S3 / S
1), Bα ⁱ (i = 0, 1,..., 2 ^m −
2) are derived to lines L60 to L6i, respectively.

The arithmetic circuit 43 calculates the value of Bα from the arithmetic circuit 42.
B (α ⁱ ) ² is obtained in response to the output of ⁱ . A specific configuration of the arithmetic circuit 43 is shown in FIG. Bα
Relative to ^1, B (α ⁱ⁾ to determine the ^2, i pieces of alpha multiplier ^{Bα i MX41; MX51, MX52;} MX61, M
X62, MX63; are used. This may be realized by preparing i α multiplications in a matrix and configuring an α ⁱ circuit.

The error position detector 44 functions to obtain i satisfying the condition of the above-mentioned expression 10 from all Aα ⁱ and B (α ⁱ ) ² (i = 0, 1,..., 2 ^m −2). . The specific configuration of the error position detector 44 is shown in FIG.

The error position detector 44 shown in FIG.
It serves to derive a logical "1" signal to lines L80-L8i for i for which the condition of Equation 10 is satisfied. In order to achieve this function, adders AD10 to AD1i are provided for each bit of the error position detector 44.

FIG. 18 is an electric circuit diagram showing a specific configuration of the adder AD10 provided in the error position detector 44. The output of each bit A0 _- Am _-1 and B0 _- Bm _-1 is
Exclusive OR gates forming the adder circuit are designated by ER70 to ER70.
R7 _m-1 and their outputs are AND
Gate G2 and NAND gate G3, respectively. The second and subsequent bits a1 to am _-1 , b1 to bm _-1 are applied to the NAND gate G3. AND gate G2 is supplied with first bits a0 and b0.

[0056] _{^{Aα i = (a m-1}} , a m-2, ..., a0), B (a i) 2 = (b m-1, b m-2, ..., b0) when a, a0 + b0 = 1 mod 2... (17) aj + bj = 0 mod 2 (j = 1, 2,..., M−1) If the two conditions are satisfied, Expression 10 is satisfied, and the logic “1” is satisfied. Is output.

Assuming that the received word Y = (y _m−1 , y _m−2 ,..., Y 0) (m = code length), among the outputs from the lines L80 to L8i, i =
If L1 and i = L2 are logic “1” and 0 ≦ L1 <L2 <2 ^m −2,

[0058]

(Equation 4)

This bit is an error, and it is sufficient to invert it. This inversion operation is performed by the data register 18.
Is achieved.

According to the present invention, the relationship between the coefficients of the error locator polynomial and the syndrome is obtained not only for the above-mentioned double error correction code but also for a code having a larger number of corrections by the Euclidean method and the Berlekamp-Matsushii method. Thus, the present invention can be implemented for hardware.

[0061]

As described above, according to the error derivation polynomial coefficient derivation circuit of the present invention, the operations of addition, multiplication, and division for deriving the inverse element on the Galois extended field GF (2 ^m ) It is realized by a simple gate circuit, so that its operation can be performed at high speed. Further, the effect that the configuration such as the gate circuit is a simple circuit configuration centering on the α multiplier is also achieved. Further, according to the present invention, the need for access by an external read-only memory is eliminated. Further, the structure of the present invention can be easily realized by an integrated circuit, and has an effect of reducing cost.

Further, according to the error position detecting circuit of the present invention, the error position can be detected in real time,
An external clock is not required, and furthermore, it can be constituted only by a gate circuit, so that an effect that the integration is easy and the cost is reduced is achieved. As described above, according to the present invention, it is possible to search for an error position simultaneously with reading of a BCH code signal by a specific circuit configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an entire configuration of an error correction circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an entire configuration of an error correction circuit according to another embodiment of the present invention.

FIG. 3 is a block diagram showing a specific configuration of an error locator polynomial coefficient derivation circuit 12;

FIG. 4 is an electric circuit diagram showing a specific configuration of an α-multiplier MX1 included in the element creating circuit 19.

FIG. 5 is a block diagram showing a specific configuration of a power circuit 21;

FIG. 6 is a block diagram showing a specific configuration of an adder AD0 included in the power circuit 21.

7 is a block diagram showing a specific structure of S1 ² search circuit 22.

8 is an electric circuit diagram showing a more specific configuration of the S1 ² search circuit 22 shown in FIG.

FIG. 9 is a block diagram showing a specific configuration of the S1 inverse search circuit 25;

10 is an electric circuit diagram showing a specific configuration of an exclusive OR gate ER30 and an all-zero detection circuit AZ0 included in the S1 inverse element search circuit 25 shown in FIG.

FIG. 11 is a block diagram showing a specific configuration of an S3 / S1 search circuit 26;

FIG. 12 is an electric circuit diagram showing a specific configuration of an adding circuit 28.

FIG. 13 is a block diagram showing a specific configuration of a chain search circuit 13 of FIG. 1;

14 is an overall block diagram showing a specific configuration of an error position detection circuit 53 shown in FIG.

FIG. 15 is a block diagram showing a specific configuration of an arithmetic circuit 41 shown in FIG.

FIG. 16 is a block diagram showing a specific configuration of a squaring circuit 43.

FIG. 17 is a block diagram showing a specific configuration of the error position detector 44.

FIG. 18 is an electric circuit diagram showing a specific configuration of an adder AD10 included in the error position detector 44 shown in FIG.

FIG. 19 is a block diagram showing the overall configuration of a prior art error correction circuit.

[Explanation of symbols]

9,10 syndrome register 11 n-bit data register 12 error derivation polynomial coefficient derivation circuit 13 chain search circuit 14 addition circuit 17 correction control circuit 18 data register 19 element creation circuit 21 exponentiation circuit 22 S1 ² search circuit 23 multiplication circuit 25 S1 inverse Original search circuit 26 S3 / S1 search circuit 27 Multiplication circuit 28 Addition circuit 41, 42 Arithmetic circuit 43 Square circuit 44 Error position detector 53 Error position detection circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 13/00 G06F 11/10 330 H04L 1/00

Claims (2)

(57) [Claims] 1. A first syndrome register 9 for dividing a BCH code signal by (x-α) to obtain a first syndrome S1; and (b) dividing the BCH code signal by (x-α ³ ). And (c1) a coefficient deriving circuit 12 for an error locator polynomial, wherein (c1) α is a primitive element of a Galois extension field GF (2 ^m ) of the m-th order And a double error correction (n, k) BC having α and α ³ as roots
In decoding the H code, (2 ^m -1) first α multipliers MX1 to MXi are connected in series, and the first stage first α multiplier M
By giving α0 to X1, the ^element αα of GF (2 ^m )
(c2) responding to the first syndrome S1 and the output of the element creation circuit 19, which creates α (2 ^m -1) (hereinafter, α represents the power of (2 ^m -1)); a power circuit 21 for obtaining the ^{S1α~S1α (2 m -1), (} 2 m -1) has a number of first adder AD0～ADi, the adders AD0～ADi, each bit a0 of S1 -A3 and bits b0-b3 of α1-α (2 ^m -1) are provided, and the outputs of these first exclusive-OR gates ER0-ER3 are Each of the first adders AD0 to ADi has a power circuit 21 for deriving outputs L0 to Li, and (c3) first syndromes S1 and (2m) on GF (2 ^m ). ^m
-1) a first multiplication circuit 23 for multiplying the elements,
(C 4) a first multiplication circuit 23 that connects the (2 ^m −1) second α multipliers MX11 to MX1i in series and provides the first syndrome S1 to the first-stage second α multiplier MX11; results and, based on the result of the exponentiation circuit 21, obtains the S1 ² S1 ² search circuit 2
2, the outputs of the second α multipliers MX11 to MX1i and the outputs L0 to Li of the first adders AD0 to ADi of the power circuit 21.
And the outputs of the first AND gates G10 to G1i are given.
And S1 ² search circuit 22 and a second exclusive OR gate ER10 for outputting 1 ^2, (c5) S1 a inverse search circuit 25 for obtaining the inverse of, (2 ^m -1) pieces of the 3 exclusive OR gates ER30-E
R3i, each of the third exclusive OR gates ER30 to ER30.
ER3i is provided with third exclusive OR gates ER30 to ER3i to which α ⁰ and outputs of the second multipliers MX11 to MX1i of the first multiplier circuit 23 are provided, and ER3i of the third exclusive OR gates ER30 to ER3i. An inverse element search circuit 25 having all-zero detection circuits AZ0 to AZi realized by a NAND gate for detecting that all bits of each output become logic "0"; (c6) second syndromes S3 and GF (2 ^m ) on (2 ^m
-1) a second multiplication circuit 27 for multiplying the elements,
A second multiplier circuit 27 that connects (2 ^m −1) third α multipliers MX21 to MX2i in series and provides a second syndrome S3 to the first-stage third α multiplier MX21; and (c7) a second multiplier circuit 27. Result and inverse element search circuit 25
S3 / S1 to obtain S3 / S1 based on the result from
(C7-1) (2 ^m -1) second AND gates G20
To G2i, each of the second AND gates G20 to G2i.
Are all zero detection circuits AZ0 to AZ of the inverse element search circuit 25.
second AND gates G20 to G2 to which outputs L20 to L2i of i and outputs from third α multipliers MX21 to MX2i of second multiplying circuit 27 are provided.
and i, and (C7-2) output is supplied first 2AND gate G20~G2i, S3 / S1 search circuit 26 and a fourth exclusive OR gate ER5 to derive S3 / S1, (c8) S1 2 2 for adding the results of S3 and S3 / S1
8, the second exclusive OR gate ER1 of the S1 ² search circuit 22
The output S1 ^{2 of} 0 and the output S3 / S1 of the fourth exclusive OR gate ER5 of the S3 / S1 search circuit 26 are given for each bit, and the fifth exclusive output that outputs (S1 ² + S3 / S1) is provided. Error locator polynomial coefficient deriving circuit 12 including an addition circuit 28 having logical OR gates ER60 to ER63
(D) a chain search circuit 13 for performing a chain search in response to an output of the coefficient derivation circuit of the error locator polynomial to indicate an error position; and (e) a register for receiving and storing the BCH code signal. And (f) an arithmetic circuit 14 for calculating the output of the chain search circuit and the output of the data register to obtain a corrected BCH code signal.
And an error correction circuit comprising: 2. (a) a first syndrome register 9 for dividing a BCH code signal by (x-α) to obtain a first syndrome S1; and (b) dividing the BCH code signal by (x-α ³ ). And (c1) a coefficient deriving circuit 12 for an error locator polynomial, wherein (c1) α is a primitive element of a Galois extension field GF (2 ^m ) of the m-th order And a double error correction (n, k) BC having α and α ³ as roots
In decoding the H code, (2 ^m -1) first α multipliers MX1 to MXi are connected in series, and the first stage first α multiplier M
By giving α0 to X1, the ^element αα of GF (2 ^m )
(c2) responding to the first syndrome S1 and the output of the element creation circuit 19, which creates α (2 ^m -1) (hereinafter, α represents the power of (2 ^m -1)); a power circuit 21 for obtaining the ^{S1α~S1α (2 m -1), (} 2 m -1) has a number of first adder AD0～ADi, the adders AD0～ADi, each bit a0 of S1 -A3 and bits b0-b3 of α1-α (2 ^m -1) are provided, and the outputs of these first exclusive-OR gates ER0-ER3 are Each of the first adders AD0 to ADi has a power circuit 21 for deriving outputs L0 to Li, and (c3) first syndromes S1 and (2m) on GF (2 ^m ). ^m
-1) a first multiplication circuit 23 for multiplying the elements,
(C 4) a first multiplication circuit 23 that connects the (2 ^m −1) second α multipliers MX11 to MX1i in series and provides the first syndrome S1 to the first-stage second α multiplier MX11; results and, based on the result of the exponentiation circuit 21, obtains the S1 ² S1 ² search circuit 2
2, the outputs of the second α multipliers MX11 to MX1i and the outputs L0 to Li of the first adders AD0 to ADi of the power circuit 21.
And the outputs of the first AND gates G10 to G1i are given.
And S1 ² search circuit 22 and a second exclusive OR gate ER10 for outputting 1 ^2, (c5) S1 a inverse search circuit 25 for obtaining the inverse of, (2 ^m -1) pieces of the 3 exclusive OR gates ER30-E
R3i, each of the third exclusive OR gates ER30 to ER30.
ER3i is provided with third exclusive OR gates ER30 to ER3i to which α ⁰ and outputs of the second multipliers MX11 to MX1i of the first multiplier circuit 23 are provided, and ER3i of the third exclusive OR gates ER30 to ER3i. An inverse element search circuit 25 having all-zero detection circuits AZ0 to AZi realized by a NAND gate for detecting that all bits of each output become logic "0"; (c6) second syndromes S3 and GF (2 ^m ) on (2 ^m
-1) a second multiplication circuit 27 for multiplying the elements,
A second multiplication circuit 27 that connects (2 ^m -1) third α multipliers MX21 to MX2i in series and provides a second syndrome S3 to the first-stage third α multiplier MX21; and (c7) a second multiplication circuit 27. Result and inverse element search circuit 25
S3 / S1 to obtain S3 / S1 based on the result from
(C7-1) (2 ^m -1) second AND gates G20
To G2i, each of the second AND gates G20 to G2i.
Are all zero detection circuits AZ0 to AZ of the inverse element search circuit 25.
second AND gates G20 to G2 to which outputs L20 to L2i of i and outputs from third α multipliers MX21 to MX2i of second multiplying circuit 27 are provided.
and i, and (C7-2) output is supplied first 2AND gate G20~G2i, S3 / S1 search circuit 26 and a fourth exclusive OR gate ER5 to derive S3 / S1, (c8) S1 2 2 for adding the results of S3 and S3 / S1
8, the second exclusive OR gate ER1 of the S1 ² search circuit 22
The output S1 ^{2 of} 0 and the output S3 / S1 of the fourth exclusive OR gate ER5 of the S3 / S1 search circuit 26 are given for each bit, and the fifth exclusive output that outputs (S1 ² + S3 / S1) is provided. Error locator polynomial coefficient deriving circuit 12 including an addition circuit 28 having logical OR gates ER60 to ER63
If, (d) an error position detecting circuit, (d1) when the error position polynomial σ and (z) = 1 + Az + Bz 2, (2 m -2) pieces of the 4α multiplier MX31~
MX3i are connected in series, and a first-stage fourth α multiplier MX31
The second exclusive OR gate E of the S1 ² search circuit 22
By giving A which is the output S1 ² of R10, Aα ⁱ
The first arithmetic circuit 41 that outputs (i = 0, 1, 2,..., 2 ^m −2) is connected in series with (d2) (2 ^m −2) fifth α multipliers, and the first stage 5α to the multiplier, the output from the fifth exclusive OR gate ER60~ER63 of the adder circuit 28 (S1 ² +
S3 / S1) to give Bα ^j (j
= 0,1,2, ..., the second arithmetic circuit 42 for outputting a ^{2 m -2), (d3)} Bα k (k = 0,1,2, ..., 2 m -2) to the 6α multiplier MX41; MX51, MX52; MX6
, MX62, MX63; are connected to each other to output B (α ^k ) ^2. (D4) Based on the outputs of the first and third arithmetic circuits 41 and 43, A circuit for determining ^L where the error locator polynomial is σ (α ^L ) = 0 (L = 0, 1, 2,..., 2 ^m −2) and deriving an output indicating the error position of the received codeword 44, Aα ⁱ and B (α ⁱ )
² (i = 0, 1,..., 2 ^m −2) are provided, and each of the third adders AD10 to AD1i is provided with each of Aα ⁱ and B (α ⁱ ) ² . Sixth exclusive OR gates ER70 to ER7 for each bit to which a bit is applied
sixth exclusive OR gates ER71 to ER7 _{m-1 to which m-1} and the second and subsequent bits a1 to am _-1 , b1 to bm _-1 are given.
Error position indicating output having a second NAND gate G3 to which the output of the second NAND gate G3 is applied, a sixth exclusive OR gate ER70 to which the first bits a0 and b0 are applied, and an AND gate G2 to which the output of the second NAND gate G3 is applied. An error position detection circuit 53 including a derivation circuit 44; and (e) a correction control circuit 17 for clearing a correction output as an uncorrectable error has occurred when S1 = 0 and S3 ≠ 0.
(F) storing the BCH code signal, performing correction by the output of the error position detection circuit and the correction control circuit, and correcting the corrected BC
An error correction circuit comprising: a data register for obtaining an H code signal.