JPH06348518A - Error correcting circuit - Google Patents

Abstract

PURPOSE:To provide a circuit which finds the coefficients of an error position polynomial with a simple gate circuit. CONSTITUTION:This circuit is equipped with a circuit which generates the element of a Galois field GF (2<m>) by connecting (2<m>-1) alpha multipliers in series for the a compound of double error correction (n, k) BCH codes of GF (2<m>), a circuit which finds power by contrasting the element with a syndrome S1, a circuit which multiplies the syndrome S1 by (2<m>-1) elements, a circuit which finds S1<2> from the arithmetic results, a circuit which finds the inverse element of S1, a circuit which multiplies a syndrome S2 by (2<m>-1) elements, a circuit which finds S3/S1 from the multiplication results, and an adding circuit which finds S1<2>+S3/S1.

Description

Detailed Description of the Invention

[0001]

The present invention relates to the decoding of a double error correction (n, k) BCH code having α as an atomic source of Galois extension field GF (2 ^m ) and α and α ³ as roots. The present invention relates to an error locator polynomial coefficient deriving circuit, an error locator detection circuit, and a correction circuit using them.

[0002]

2. Description of the Related Art t-bit correction BCH (Bose-Chauduri-Ho)
cqenghem Codes) For code parameters, code length n
Is n = 2 ^m −1 (1), the number of information k is k ≧ n−mt (2), and the BCH code having such a code length n and the number of information k is (n, k) Called BCH code.

Among the error correction codes, the BCH code is extremely important in practical use and is widely used in the fields of communication and recording. Among them, the double error correction code is
The relationship between the error locator polynomial coefficient used in decoding and the syndrome has been clarified, and it is relatively easy to study hardware implementation. However, since the decoding requires operations such as addition, multiplication, and division on the Galois field, in the prior art, (a) exponent ← → vector representation, inverse element, etc. are stored in the read-only memory. , Or a configuration in which (b) a syndrome and an error position are obtained from a table and the read-only memory is similarly accessed from the outside is realized. In such a prior art, when hardware is used, a read-only memory requires a large memory capacity, resulting in a high cost for the number of corrections.

For example, in the prior art of FIG. 19, a register 2 of the syndrome S1 to which the BCH code signal is given from the line 1, a register 3 of the syndrome S3, and a read only memory 4 are provided, and the received BCH code signal is provided. Is provided, and an exclusive OR gate circuit 6 for deriving the corrected BCH code signal is provided. Such a prior art shown in FIG. 19 realizes the above prior art (b),
As described above, there is a problem that it is necessary to increase the memory capacity of the read-only memory 4.

[0005]

SUMMARY OF THE INVENTION An object of the present invention is to provide an error locator polynomial which enables operations such as addition, multiplication and division on a Galois extension field GF (2 ^m ) to be realized with a simple structure. It is to realize a coefficient derivation circuit and to provide a correction circuit using it.

Conventionally, the chain search method has been used for deriving the error position, and the configuration for realizing this method requires an external clock signal, and thus there is a problem that real-time processing cannot be performed.

Another object of the present invention is to realize an error position detection circuit which enables the search for an error position simultaneously with the reading of a BCH code signal, and to provide an error correction circuit using the error position detection circuit. .

[0008]

According to the present invention, a double error correction (n, k) BCH code having α as a primitive element of Galois extension field GF (2 ^m ) and having α and α ³ as roots is used in the present invention. In decoding
By connecting (2 ^m −1) α multipliers in series, an element creation circuit that creates an element of GF (2 ^m ) and the syndrome S1 by the output of the element creation circuit Exponentiation circuit and syndrome S
1 by multiplying 1 by (2 ^m −1) elements on GF (2 ^m ).
A circuit for obtaining S1 ² based on the result of the multiplication circuit, the first multiplication circuit, and the result of the power circuit, a circuit for obtaining the inverse element of S1 based on S1 ² , and syndromes S3 and G
A second multiplication circuit for multiplying (2 ^m −1) elements on F (2 ^m ); a circuit for obtaining S3 / S1 based on the result of the second multiplication circuit and the result from the inverse element circuit; S1 ² and S3 / S1
It is a coefficient deriving circuit of an error locator polynomial characterized by including a circuit for adding the results of and.

In the present invention, α is an Galois extension G of degree m
In the decoding of a double error correction (n, k) BCH code having a primitive element of F (2 ^m ) and having α and α ³ as roots, the error locator polynomial is expressed by σ (z) = 1 + Az + Bz ² Then, by multiplying A by a circuit in which (2 ^m −2) α multipliers are connected in series, Aα ⁱ (i = 0,
1, 2, ..., 2 ^m -2) outputting a first arithmetic circuit,
By multiplying B by a circuit in which (2 ^m −2) α multipliers are connected in series, Bα ^j (j = 0, 1, 2, ..., 2 ^m
-2) and a second arithmetic circuit that outputs Bα ^k (k = 0,
A second arithmetic circuit for outputting B (α ^k ) ² by connecting k α multipliers to 1, 2, ..., 2 ^m −2);
Based on the outputs of the arithmetic circuit and the third arithmetic circuit, ^L that satisfies σ (α ^L ) = 0 (L = 0, 1, 2, ..., 2 ^m −2) is discriminated, and the error position of the received codeword is determined. And a circuit for deriving an instructed output.

Still further, according to the present invention, (a) a first syndrome register for obtaining a syndrome S1 by dividing a BCH code signal by (x-α), and (b) the BCH
A second syndrome register for dividing the coded signal by (x-α ³ ) to obtain a syndrome S3; and (c)
A coefficient deriving circuit for an error locator polynomial, wherein α is a primitive element of a Galois extension field GF (2 ^m ) of degree ^m , and decoding of a double error correction (n, k) BCH code having α and α ³ as roots At
By connecting (2 ^m −1) α multipliers in series, an element creation circuit that creates an element of GF (2 ^m ) and the syndrome S1 by the output of the element creation circuit Exponentiation circuit and syndrome S
1 by multiplying 1 by (2 ^m −1) elements on GF (2 ^m ).
A circuit for obtaining S1 ² based on the result of the multiplication circuit, the first multiplication circuit, and the result of the power circuit, a circuit for obtaining the inverse element of S1 based on S1 ² , and syndromes S3 and G
A second multiplication circuit for multiplying (2 ^m −1) elements on F (2 ^m ); a circuit for obtaining S3 / S1 based on the result of the second multiplication circuit and the result from the inverse element circuit; S1 ² and S3 / S1
And an error position polynomial coefficient deriving circuit, and (d) a chain search in response to the output of the error position polynomial coefficient deriving circuit, and a chain search representing an error position. A circuit, (e) a register for data that receives and stores the BCH code signal, and (f) an arithmetic circuit that calculates the output of the chain search circuit and the output of the data register to obtain a corrected BCH code signal. It is an error correction circuit characterized by including.

The present invention further comprises (a) a first syndrome register for dividing the BCH code signal by (x-α) to obtain a syndrome S1, and (b) dividing the BCH code signal by (x-α ³ ). Is a second syndrome register for obtaining the syndrome S3 and (c) a coefficient deriving circuit of the error locator polynomial, wherein α is a primitive element of the Galois extension field GF (2 ^m ) of degree ^m , and α, α ³ are 2 with root
In decoding a multiple error correction (n, k) BCH code, (2
^{By connecting m} −1) α multipliers in series, G
An element generation circuit that generates an element of F (2 ^m ) and a power circuit that calculates the exponentiation by comparing the syndrome S1 with the output of the element generation circuit, and syndromes S1 and G
A first multiplication circuit for multiplying (2 ^m −1) elements on F (2 ^m ), a circuit for obtaining S1 ² based on the result of the first multiplication circuit and the result of the exponentiation circuit, and S1 Based on ² , S
A circuit for finding the inverse element of 1 and the syndromes S3 and GF (2
a second multiplication circuit for multiplying (2 ^m -1) elements on ^m ),
Derivation of such error location polynomial coefficient including a circuit for obtaining S3 / S1 based on the result of the second multiplication circuit and the result from the inverse element circuit, and a circuit for adding the results of S1 ² and S3 / S1 Circuit and (d) error position detection circuit, where (2 ^m −2) α multipliers are connected in series when the error position polynomial is σ (z) = 1 + Az + Bz ² . By multiplying the circuit by A, Aα ⁱ (i = 0,
1, 2, ..., 2 ^m -2) outputting a first arithmetic circuit,
By multiplying B by a circuit in which (2 ^m −2) α multipliers are connected in series, Bα ^j (j = 0, 1, 2, ..., 2 ^m
-2) and a second arithmetic circuit that outputs Bα ^k (k = 0,
A second arithmetic circuit for outputting B (α ^k ) ² by connecting k α multipliers to 1, 2, ..., 2 ^m −2);
Based on the outputs of the arithmetic circuit and the third arithmetic circuit, ^L that satisfies σ (α ^L ) = 0 (L = 0, 1, 2, ..., 2 ^m −2) is discriminated, and the error position of the received codeword is determined. An error position detection circuit including a circuit for deriving an instructed output, and (e)
When S1 = 0 and S3 ≠ 0, a correction control circuit that clears the correction output assuming that an uncorrectable error has occurred, and (f) B
It is an error correction circuit characterized by including a CH code signal and storing the error position detection circuit and a data register for performing correction by the output of a correction control circuit to obtain a corrected BCH code signal.

[0012]

First, the error locator polynomial deriving circuit will be described. The double error correction BCH code is a Galois extension field GF (2
^When α of ^m ) is a primitive element, it has α and α ³ as roots. Now, when the error positions are L1 and L2, the syndrome S
1, S3 becomes ^{S1 = α L1 + α L2 ...} (3) S3 = α 3L1 + α 3L2 ... (4). By using this, the error locator polynomial becomes σ (x) = 1 + S1x + (S1 ² + S3 / S1) x ² (5). Since the coefficient S1 of x has been obtained, (S1 ²
+ S3 / S1) may be calculated. For this calculation, conventionally R
Reference was made by OM. However, it is difficult to directly calculate S1 ² and S3 / S1 by the gate circuit. Therefore, the present invention is configured as follows.

First, S1 ² is one of (2 ^m -1) elements on GF (2 ^m ) of the Galois extension field. Therefore, by connecting (2 ^m -1) α multiplication circuits in series,

[0014]

[Equation 1]

If S1 ² is obtained, S12 is either of them. Assuming that S1 = alpha ^i, since it is ^{S1 2 = S1α i mod 2 m} -1 ... (6), of the group GR1, the calculation result of alpha ⁱ is S1 ^2. In the above equation 6, mod means taking the remainder obtained by dividing the result of the original power calculation by 2 ^m −1.

On the other hand, in order to calculate S3 / S1, it is necessary to find the inverse element of S1. When the same manner as described above S1 = alpha ^i, inverse alpha ^j of alpha ⁱ serves as a ^{α i · α j = α o} mod 2 m -1 ... (7), whereby, S3 / S1 is obtained in ^{S3 / S1 = S3 · α -i} = S3 · α j mod 2 m -1 ... (8).

First, like the group GR1 described above,

[0018]

[Equation 2]

[0019] Then, the group GR1 is searched for α ^j that satisfies S1α ^j = α ^o mod 2 ^m -1 (9). Then, since α ^j is the inverse element of S1, the multiplication result of S3 by α ^j in the group GR2 is S3 / S1.

S1 ² and S3 / calculated as described above
If S1 is added, it becomes the coefficient for x ^{2 in} Equation 5.

Next, the error position detection circuit will be described.

When σ (α ⁱ ) = 0 (i = 0, 1, ..., 2 ^m −2) (10) with respect to the above expression 5, i + j mod 2 ^m −1 = 0 j Indicates the position of the error. Therefore, to derive the error position, α ⁱ (i = 1, 2, ..., 2 ^m −2) is successively substituted, and σ
It is sufficient to check (α ⁱ ) = 0.

To realize this in hardware, the chain search method is used, but a clock corresponding to the code length is required. Therefore, in the present invention, the following is performed.

First, for A and B, an α multiplication circuit of 2 ^m −
By inputting two in series

[0025]

[Equation 3]

Can be calculated simultaneously. Aα ⁰ and Bα ⁰ are
Consider A and B themselves.

The above-mentioned group GR3 is the second item of Equation 5 calculated for all α ⁱ (i = 0, 1, ..., 2 ^m −2). However, to find the three items in Equation 5,
The square of α ⁱ (i = 0, 1, ..., 2 ^m −2) is required.

In the present invention, Bα of the above-mentioned group GR4 is used.
^{For i} (i = 0,1, ..., 2 ^m −2), by connecting i multipliers in series, (Bα ⁱ ) · α ⁱ = B (α ⁱ ) ² (i = 0,1) , ..., 2 ^m -2) ... (11) is obtained.

A α ⁱ , B (α ⁱ ) ² (i = 0, 1, ..., 2 ^m
-2) can be calculated, so this is added for each i, and 1 + Aα ⁱ + B (α ⁱ ) ² = 0 (12) Then, j that satisfies i + j mod 2 ^m −1 indicates the error position.

The above calculation is performed for all α ⁱ (i = 0, 1,
, 2 ^m -2), the error position can be searched at high speed.

[0031]

1 is a block diagram showing the overall structure of an error correction circuit according to an embodiment of the present invention. The BCH code signal is input from the line 8 and is divided by (x-α) to obtain the syndrome S1, and the m-bit syndrome register 9 is divided by (x-α ³ ) to obtain the syndrome S3. And the m-bit syndrome register 10 to be obtained. Further, the error correction circuit is provided with an n-bit data register 11 to which a BCH code signal is given, and further an error locator polynomial coefficient deriving circuit 12 to which the syndromes S1 and S3 from the syndrome registers 9 and 10 are respectively provided. To be The output S of the error deriving polynomial coefficient deriving circuit 12
1, S1 ² + S3 / S1 are given to the chain search circuit 13, and the exclusive OR gate 14 is connected to the chain search circuit 13
And the output of the data register 11 are calculated to obtain the corrected BCH protection signal. When the n-bit code word is read in this way, the syndromes S1 and S3 are calculated by the syndrome registers 9 and 10, and the coefficient of the error locator polynomial is also calculated at the same time. Then α ^-i (i
= 0, 1, ..., 2 ^m −2), and σ (α ⁱ )
I for which = 0 represents an error position. This calculation can be easily realized by the chain search circuit 13. The chain search circuit is disclosed, for example, in Hideki Imai, "Code Theory", page 166.

FIG. 2 is a block diagram showing the overall structure of an error correction circuit according to another embodiment of the present invention. This embodiment is similar to the embodiment shown in FIG. 1 and the corresponding parts bear the same reference numerals. In this embodiment, an error position detection circuit 53 is provided instead of using the chain search circuit 13 described above. When S1 = 0 and S3 ≠ 0 from the error locator polynomial coefficient deriving circuit 12 to the line 16, a signal for deriving a correction output is derived when an uncorrectable error occurs and is supplied to the correction control circuit 17. This correction control circuit 17
Is provided to the received codeword data register 18. According to the configuration shown in FIG. 2, it is not necessary to use the chain search circuit 13 in the embodiment shown in FIG. 1, and therefore the external clock signal required in the chain search circuit is not required in the embodiment shown in FIG. It is not necessary, so that the error position can be detected in real time.

FIG. 3 is a block diagram showing a specific configuration of the error locator polynomial coefficient deriving circuit 12 in each of the embodiments shown in FIGS. The element generation circuit 19 is a circuit that represents all elements of the Galois extension field GF (2 ^m ) of order ^m .
This element creation circuit 19 is composed of (2 ^m −1) α multipliers MX.
It is realized by connecting 1 to MXi in series.
Double-headed arrows in FIG. 3 and other figures indicate the flow of m-bit parallel data on the Galois extension field GF (2 ^m ).

FIG. 4 shows a specific configuration of the α multiplier MX1, which is a configuration of the (15,7) BCH code (m = 4). The α multiplier MX1 includes the exclusive OR gate 20, and can be realized with a simple configuration by using an adjoint matrix.

The power circuit 21 is for multiplying the original on the syndrome S1 and the Galois extension field GF (2 ^m), look for whether the syndrome S1 is equal to any original on Galois extension field GF (2 ^m) Work.

FIG. 5 is a block diagram showing a specific structure of the exponentiation circuit 21. The power circuit 21, an adder _{AD0~ADi, S1 = (a m-} 1, ..., a 0), α
^{When i} = (b _m−1 , ..., b ₀ ), a configuration for obtaining α ^{i such} that ai = (bi) (i = 0,1,2, ..., m−1) (14) is realized. It should be done.

FIG. 6 shows a specific structure of the adder AD0. The adder AD0 has bits a0 to a3 and b0 to b3.
Is calculated by the exclusive OR gates ER0 to ER3, and all outputs may be logical "0". In the configuration of FIG. 6,
The configuration for a (15,7) BCH code (m = 4) is shown. The output of the exclusive OR gates ER0 to ER3 is NAN.
It is applied to the D gate G0. As for the control signals on the output lines L0 to Li of the adders AD0 to ADi, the control signal given to the S1 ² search circuit 22 described later has a logic “1” only for i for which S1 = α ⁱ (15).

The first multiplication circuit 23 multiplies the syndrome S1 by (2 ^m -1) elements on the Galois extension field GF (2 ^m ). The first multiplication circuit 23 is realized by connecting (2 ^m −1) α multipliers MX11 and MX1i in series, and the configuration thereof is the same as the α multipliers MX1 to MX of the original creation circuit 19 described above.
Similar to Xi.

FIG. 7 is a block diagram showing a specific configuration of the S1 ² search circuit 22. This S1 ² search circuit 2
2 is a source for obtaining S1 ² based on the result of the first multiplication circuit 23 and the result of the exponentiation circuit 21.
It operates to select S1 ² from α ⁱ (i = 0, 1, ..., 2 ^m −2), the AND gates G10 to G1 i are supplied with the control signals of the lines L0 to Li, and the first multiplication The respective outputs from the α multipliers MX11 to MX1i of the circuit 23 are respectively supplied to the exclusive OR gate ER10, and the outputs of the AND gates G10 to G1i thereof are supplied to the exclusive OR gate ER10 to the line 10. Is
The output of S1 ² is derived.

FIG. 8 is an electric circuit diagram more specifically showing a part of the S1 ² search circuit 22 shown in FIG.
When the (15,7) BCH code (m = 4) is used, the AND gate G10 described above has AND gates G20 to G23.
Realized by the exclusive OR gates ER20 to ER
The output of each AND gate G20 to G23 and the output of the exclusive OR gate connected in connection with the next AND gate G11 are given to 23. Thus exclusive OR gates ER20~ER23 derives an output S1 ^2.

The S1 inverse element search circuit 25 uses the S1α ^k (i
From 0 = 0, 1, ..., 2 ^m −2), S1α ⁱ = i ⁰ (16), that is, α ⁱ that is the inverse element of S1 is obtained.

FIG. 9 is a block diagram showing a specific configuration of the S1 inverse element search circuit 25. S1 inverse element search circuit 2
5 is similar to the S1 search circuit 22 shown in FIG. 7, and when S1α ⁱ = (a _m-1 , ..., A ₀ ) and α ⁰ = (0, ..., 1) It suffices to find α ^{i for} which 16 holds. Therefore, each α multiplier MX11 of the first multiplication circuit 23
The output from MX1i is the exclusive OR gate ER30.
To ER3i together with α ⁰ , that is, each bit is subjected to exclusive OR operation, and all outputs are all zero detection circuit AZ0
~ AZi detects that it becomes a logic "0" and derives its output from lines L20 to L2i, respectively.

FIG. 10 is an electric circuit diagram showing a specific configuration of the exclusive OR gate ER30 and the all-zero detection circuit AZ0.

For the signal processing of the (15,7) BCH code (m = 4), the exclusive OR gate ER30 is provided with exclusive OR gates ER40 to ER44 for each bit and all zeros. The detection circuit AZ0 is realized by a NAND gate. Only for i for which the above equation 16 is satisfied, the control signal given to the S3 / S1 search circuit 26, which will be described later, becomes a logic “1”.

The second multiplication circuit 27 multiplies the syndrome S3 by (2 ^m -1) elements of the Galois extension field GF (2 ^m ). The second multiplication circuit 27 includes α multipliers MX21 to MX.
2i, and the configuration thereof is similar to that of the original creation circuit 19 described above.

The S3 / S1 search circuit 26 uses S3α
^It has a function of selecting from ⁱ (i = 0, 1, ..., 2 ^m −2) the result of S3 / S1.

FIG. 11 is a block diagram showing the overall structure of the S3 / S1 search circuit 26. The S3 / S1 search circuit 26 has a configuration similar to that of the S1 ² search circuit 22 described above, and includes lines L20 to L2i of the S1 inverse element search circuit 25.
Output and each α multiplier MX21 to MX of the second multiplication circuit 27
AND gates G20 to G2 to which respective outputs of 2i are given
i and an exclusive OR gate ER5 are provided, and S3 / S1 is derived from the line L30. That is, the control signal from the line L20~L21 is S3arufa ⁱ is S3 / S1 is a logic "1", only the output is selected.

The output S1 ² from the line L10 of the S1 ² search circuit 22 and the line L of the S3 / S1 search circuit 26
The output S3 / S1 from 30 is the exclusive OR gate 2
8 is applied to the adder circuit 28, which outputs (S1 ² + S3 / S1). The specific configuration of the exclusive OR gate 28 is (15,7) B.
In the case of CH code (m = 4), as shown in FIG.
It is realized by exclusive OR gates ER60 to ER63 for each bit. These exclusive OR gates ER6
The outputs of 0 to ER63 are derived from the line L40,
(S1 ² + S3 / S1) is obtained.

FIG. 13 is a block diagram showing a specific structure of the chain search circuit 13. The output S1 ² from the line L10 of the S1 ² search circuit 22 and the output (S1 ² + S3 / S) from the line L40 of the exclusive OR gate 28.
1) is stored in m-bit data registers 29 and 30, respectively, in which those values are stored as initial values. A clock signal from a clock generator 31 realized by a counter is given to these registers 29 and 30. Each of the registers 29 and 30 has an α multiplier 32.
And α ² multiplier 33 are connected to each other, and closed loop 3
4, 35 are constructed, and their outputs are given to the adder circuit 36 of the Galois extension field GF (2 ^m ) of order ^m , and from the line 37, the exclusive OR gate 1 shown in FIG.
Given to 4. The adder circuit 36 is realized by an exclusive OR gate.

Error position detection circuit 5 shown in FIG. 2 described above.
The specific configuration of No. 3 is shown in FIG. The first arithmetic circuit 41 is supplied with S1 ² from the S1 ² search circuit 22 included in the error locator polynomial coefficient deriving circuit 12 via the line L10. This arithmetic circuit 41 is shown in FIG.
, Α multipliers MX31, MX32, ...,
MX3i is configured by being connected in series. In this way, Aα ⁱ is calculated for all α ⁱ (i = 0, 1, ..., 2 ^m −2) and leads to lines L50 to L5i.

The other arithmetic circuit 42 also has the same configuration as the arithmetic circuit 41 described above, and from the line L40 in the exclusive OR gate 28 of the error locator polynomial coefficient deriving circuit 12 (see FIG. 3 described above). Of (S1 ² + S3 / S
1), Bα ⁱ (i = 0, 1, ..., 2 ^m −
2) is derived to each of the lines L60 to L6i.

The arithmetic circuit 43 receives the Bα from the arithmetic circuit 42.
B (α ⁱ ) ² is obtained in response to the output of ⁱ . The specific configuration of the arithmetic circuit 43 is shown in FIG. Bα
Relative to ^1, B (α ⁱ⁾ to determine the ^2, i pieces of alpha multiplier ^{Bα i MX41; MX51, MX52;} MX61, M
X62, MX63 ... are used. This may be realized by preparing i number of α multiplications in a matrix and configuring an α ⁱ circuit.

The error position detector 44 functions to obtain i satisfying the condition of the above-mentioned expression 10 from all Aα ⁱ and B (α ⁱ ) ² (i = 0, 1, ..., 2 ^m −2). . The specific configuration of the error position detector 44 is shown in FIG.

The error position detector 44 shown in FIG.
It serves to derive a signal of logic "1" on lines L80 to L8i for i for which the condition of Expression 10 is satisfied. In order to achieve this function, adders AD10 to AD1i are provided for each bit of the error position detector 44.

FIG. 18 is an electric circuit diagram showing a specific structure of the adder AD10 provided in the error position detector 44. The output of each bit A0-A _m-1 and B0 _- B _m-1 is
The exclusive OR gates constituting the adder circuit are ER70 to E.
Each of them is given to R7 _m-1 and their outputs are ANDed.
It is applied to gate G2 and NAND gate G3, respectively.

When Aα ⁱ = (a _m-1 , a _m-2 , ..., A0) and B (a ⁱ ) ² = (b _m-1 , b _m-2 , ..., b0), then a0 + b0 = 1 mod 2 (17) aj + bj = 0 mod 2 (j = 1, 2, ..., m-1) (18) If the two conditions are satisfied, it means that Expression 10 is satisfied, and the logic "1" is satisfied. Is output.

As the received word Y = (y _m-1 , y _m-2 , ..., y0) (m = code length), among output from lines L80 to L8i, i =
If L1 and i = L2 are logic "1" and 0 ≦ L1 <L2 <2 ^m −2,

[0058]

[Equation 4]

The bit of is erroneous, and it is sufficient to invert it. This inversion operation is performed by the data register 18
Achieved in.

The present invention finds the relationship between the coefficient of the error locator polynomial and the syndrome by the Euclidean method or the Berlekamp-Massie method not only for the above-mentioned double error correction code but also for a code with a larger number of corrections. Thus, the present invention can be implemented for hardening.

[0061]

As described above, according to the coefficient deriving circuit of the error locator polynomial of the present invention, the operations of addition, multiplication, and division for deriving the inverse element on the Galois extension field GF (2 ^m ) are performed. It is realized by a simple gate circuit, and therefore its operation can be performed at high speed. Further, the effect that the configuration of the gate circuit and the like is a simple circuit configuration centered on the α multiplier is also achieved. Further, according to the present invention, it is not necessary to access by an external read only memory. Further, the configuration of the present invention is easy to realize by an integrated circuit and has an effect of low cost.

Further, according to the error position detection circuit of the present invention, the error position can be detected in real time,
Since an external clock is not required and the circuit can be configured only with a gate circuit, the effect of facilitating the integration into a circuit and reducing the cost can be achieved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of an error correction circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an overall configuration of an error correction circuit according to another embodiment of the present invention.

FIG. 3 is a block diagram showing a specific configuration of an error locator polynomial coefficient deriving circuit 12.

FIG. 4 is an electric circuit diagram showing a specific configuration of an α multiplier MX1 included in the original creation circuit 19.

5 is a block diagram showing a specific configuration of a power circuit 21. FIG.

FIG. 6 is a block diagram showing a specific configuration of an adder AD0 included in a power circuit 21.

FIG. 7 is a block diagram showing a specific configuration of an S1 ² search circuit 22.

8 is an electric circuit diagram showing a more specific configuration of the S1 ² search circuit 22 shown in FIG.

9 is a block diagram showing a specific configuration of an S1 inverse element search circuit 25. FIG.

10 is an electric circuit diagram showing a specific configuration of an exclusive OR gate ER30 and an all-zero detection circuit AZ0 included in the S1 inverse element search circuit 25 shown in FIG.

11 is a block diagram showing a specific configuration of an S3 / S1 search circuit 26. FIG.

FIG. 12 is an electric circuit diagram showing a specific configuration of an adder circuit.

13 is a block diagram showing a specific configuration of a chain search circuit 13 of FIG.

14 is an overall block diagram showing a specific configuration of error position detection circuit 53 shown in FIG.

15 is a block diagram showing a specific configuration of the arithmetic circuit 41 shown in FIG.

16 is a block diagram showing a specific configuration of a squaring circuit 43. FIG.

FIG. 17 is a block diagram showing a specific configuration of error position detector 44.

18 is an electric circuit diagram showing a specific configuration of an adder AD10 included in the error position detector 44 shown in FIG.

FIG. 19 is a block diagram showing the overall configuration of a prior art error correction circuit.

[Explanation of symbols]

9, 10 Syndrome register 11 n-bit data register 12 Error position polynomial coefficient deriving circuit 13 Chain search circuit 14 Adder circuit 17 Correction control circuit 18 Data register 19 Element creation circuit 21 Power circuit 22 S1 ² Search circuit 23 Multiplier circuit 25 S1 Inverse Original search circuit 26 S3 / S1 search circuit 27 Multiplier circuit 28 Adder circuit 41, 42 Operation circuit 43 Square circuit 44 Error position detector 53 Error position detection circuit

Claims (4)

[Claims] 1. Double error correction (n, n) having α as a primitive element of a Galois extension field GF (2 ^m ) of degree ^m and having α, α ³ as roots.
k) In decoding the BCH code, by connecting (2 ^m −1) α multipliers in series, an element generation circuit for generating an element of GF (2 ^m ) and a syndrome S1 as an output of the element generation circuit. The exponentiation circuit for obtaining the exponentiation by comparing them, the first multiplication circuit that multiplies (2 ^m −1) elements on the syndrome S1 and GF (2 ^m ), the result of the first multiplication circuit, and the exponentiation based on the results of the circuit, a circuit for determining the S1 ^2, based on the S1 ^2, a circuit for determining the inverse of S1, the syndrome S3 and the GF (2 ^m) on the (2 ^m -1) number of elements A second multiplying circuit for multiplying, a circuit for obtaining S3 / S1 based on the result of the second multiplying circuit and the result from the inverse circuit, and a circuit for adding the results of S1 ² and S3 / S1 An error locator polynomial coefficient deriving circuit characterized by. 2. Double error correction (n, n) having α as a primitive element of a Galois extension field GF (2 ^m ) of order ^m and having α and α ³ as roots.
k) In decoding the BCH code, assuming that the error locator polynomial is σ (z) = 1 + Az + Bz ² , multiply A by a circuit in which (2 ^m −2) α multipliers are connected in series. A α ⁱ (i = 0,
1, 2, ..., 2 ^m -2) and a circuit in which (2 ^m -2) α multipliers are connected in series by multiplying B by Bα ^j (j = 0). , 1, 2, ..., 2 ^m
-2) and a second arithmetic circuit that outputs B (α ^k ) ² by connecting k α multipliers to Bα ^k (k = 0,1,2, ..., 2 ^m -2) Based on the outputs of the third arithmetic circuit and the first arithmetic circuit and the third arithmetic circuit, ^L that satisfies σ (α ^L ) = 0 (L = 0, 1, 2, ..., 2 ^m −2) is determined. , A circuit for deriving an output indicating the error position of the received codeword, the error position detecting circuit. 3. A first syndrome register for (a) dividing a BCH code signal by (x-α) to obtain a syndrome S1, and (b) dividing the BCH code signal by (x-α ³ ). A second syndrome register for obtaining the syndrome S3, and (c) a coefficient deriving circuit of the error locator polynomial, wherein α is a primitive element of a Galois extension field GF (2 ^m ) of order ^m ,
An element of GF (2 ^m ) is created by connecting (2 ^m −1) α multipliers in series in the decoding of a double error correction (n, k) BCH code having roots of α, α ^3. An element generating circuit that calculates the exponentiation by comparing the syndrome S1 with the output of the element generating circuit, and the syndrome S1 and (2 ^m −1) elements on GF (2 ^m ) are multiplied. A first multiplication circuit, a circuit that obtains S1 ² based on the result of the first multiplication circuit and a result of the exponentiation circuit, a circuit that obtains the inverse element of S1 based on S1 ² , and syndromes S3 and GF ( A second multiplication circuit for multiplying (2 ^m −1) elements above 2 ^m ), a circuit for obtaining S3 / S1 based on the result of the second multiplication circuit and the result from the inverse element circuit, and S1 ² And a circuit for adding the results of S3 / S1
Such an error locator polynomial coefficient deriving circuit, (d) a chain search circuit that represents an error position by performing a chain search in response to the output of the error locator polynomial coefficient deriving circuit, and (e) the BCH code signal An error correction circuit comprising: a register for data to be received and stored; and (f) an operation circuit for calculating the output of the chain search circuit and the output of the data register to obtain a corrected BCH code signal. 4. A first syndrome register for obtaining a syndrome S1 by dividing a BCH code signal by (x-α), and (b) dividing the BCH code signal by (x-α ³ ). A second syndrome register for obtaining the syndrome S3, and (c) a coefficient deriving circuit of the error locator polynomial, wherein α is a primitive element of a Galois extension field GF (2 ^m ) of order ^m ,
An element of GF (2 ^m ) is created by connecting (2 ^m −1) α multipliers in series in the decoding of a double error correction (n, k) BCH code having roots of α, α ^3. An element generating circuit that calculates the exponentiation by comparing the syndrome S1 with the output of the element generating circuit, and the syndrome S1 and (2 ^m −1) elements on GF (2 ^m ) are multiplied. A first multiplication circuit, a circuit that obtains S1 ² based on the result of the first multiplication circuit and a result of the exponentiation circuit, a circuit that obtains the inverse element of S1 based on S1 ² , and syndromes S3 and GF ( A second multiplication circuit for multiplying (2 ^m −1) elements above 2 ^m ), a circuit for obtaining S3 / S1 based on the result of the second multiplication circuit and the result from the inverse element circuit, and S1 ² And a circuit for adding the results of S3 / S1
Such an error locator polynomial coefficient deriving circuit and (d) an error locator detection circuit, where the error locator polynomial is σ (z) = 1 + Az + Bz ² , (2 ^m -2) By multiplying A by a circuit in which α multipliers are connected in series, Aα ⁱ (i = 0,
1, 2, ..., 2 ^m -2) and a circuit in which (2 ^m -2) α multipliers are connected in series by multiplying B by Bα ^j (j = 0). , 1, 2, ..., 2 ^m
-2) and a second arithmetic circuit that outputs B (α ^k ) ² by connecting k α multipliers to Bα ^k (k = 0,1,2, ..., 2 ^m -2) Based on the outputs of the third arithmetic circuit and the first arithmetic circuit and the third arithmetic circuit, ^L that satisfies σ (α ^L ) = 0 (L = 0, 1, 2, ..., 2 ^m −2) is determined. , An error position detection circuit including a circuit for deriving an output indicating the error position of the received codeword, and (e) when S1 = 0 and S3 ≠ 0, the correction output is cleared as an uncorrectable error has occurred. (F) BCH code signal is stored, and correction is performed by the output of the error position detection circuit and the correction control circuit to correct BC.
An error correction circuit including a data register for obtaining an H code signal.