JPH07111463A - Code error position detection circuit - Google Patents

Abstract

PURPOSE:To detect the error position of Read Solomon code at a high speed. CONSTITUTION:Multipliers Mi1, Mi2,..., Mik of k sets are connected in series between an output and an input of a degree number latch register Ri and outputs Li1, Li2,..., Lik are obtained from them respectively. One ai of coefficients of an error position polynomical sigma(x) is latched in the degree number latch register Ri and when a clock signal CLK is activated once, the data ai having been given to the degree number latch register Ri is given to the multiplier Mij and an output Li1 is obtained. The output Li1 is further given to the multiplier Mi2, from which the output Li2 is obtained. Thus, the error of Read Solomon code is confirmed as to k-sets of positions and the processing time is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for detecting a code error position. In particular, it relates to a technique for detecting an error position in a Reed-Solomon code, and more particularly to a chain search circuit.

[0002]

2. Description of the Related Art Conventionally, code error correction techniques have been devised, and among them, the Reed-Solomon code is capable of correcting block errors and is used as a code correction technique for optical disks.

FIG. 20 is a circuit diagram showing a configuration of a conventional chain search circuit 200 used for error detection of Reed-Solomon code. The chain search circuit 200 is provided with 8-bit order latch registers R _{0 to} R ₈ . These outputs are multiplied by 8-bit multipliers M _{0 to} M ₈ each time the clock signal CLK is activated, and the results are again multiplied by the order latch registers R _{0 to} R 8.
Retained in ₈ .

[0004] On the other hand, the output of the multiplier M ₀ ~M ₈ L ₀ ~L ₈
Are given to the adders A _{0 to} A ₈ together for each bit,
Modulo-2 addition is performed. The result is given to the OR gate 200a for each bit, and the logical sum is taken to obtain the signal G.

The number of times the clock signal CLK is activated by the counter 200b is counted, and the result is output as the signal C. Also, the signal G and the clock signal C
The LK is given to both the address generator 200c and the write pulse generator 200d, and the address P and the write pulse Q are obtained from them, respectively, and given to the error position register 200e together with the signal C.

In the error locator polynomial σ (x) shown in Equation 1, the chain search circuit 200 has Galois field elements {1, α, α ² , α ³ , ..., α ^m } having continuous exponents.
Error locator polynomial σ
The operation for finding the root at which (x) becomes 0 is performed.

[0007]

[Equation 1]

Processing for latching coefficients a _{0 to} a ₈ of the error locator polynomial σ (x) in the order latch registers R _{0 to} R ₈ and multiplying the multipliers M _{0 to} M ₈ with α ^{120 to} α ¹²⁸ , respectively. Clock signal CLK
Is first activated, the output L of each multiplier M _{0 to} M _{8
0 to} L ₈ are respectively

[0009]

[Equation 2]

[0010] However, the error locator polynomial σ (x) has an order of 8, and the calculation is performed by the Galois field GF.
Since it is performed in (2 ⁸ ), the 8-bit multiplier M ₀
In the multiplication processing in, the coefficient a ₀ is expanded into a column vector and the 8 × 8 corresponding to α ¹²⁰ is not simply multiplied by the numerical value.
An operation corresponding to the processing of multiplying by the matrix is performed.
Similar processing is performed in the multipliers M _{1 to} M ₈ .

The outputs L _{0 to} L ₈ are added to the adder A _{0 for} each bit.
Is added to the ~A _8,

[0012]

[Equation 3]

Is calculated for each bit.

However, equation 3 is transformed into equation 4.

[0015]

[Equation 4]

Therefore, if α ¹²⁰ is not 0, σ (α) = 0
Whether or not it can be detected by the signal G output from the OR gate 200a. That is, α is the root of the error locator polynomial σ (x) if the signal G is “0”, and is not the root if it is “1”. When it is the root of σ (x), it is detected that the code is incorrect at the position corresponding to the element α.

Whether or not a position of the Reed-Solomon code is incorrect is thus determined by whether or not the element corresponding to the position is the root of the error locator polynomial σ (x). Therefore, whether or not the code is incorrect at the position corresponding to the element α ² is determined when the clock signal CLK is activated again. The outputs L _{0 to} L ₈ obtained by the first activation of the clock signal CLK are latched in the order latch registers R _{0 to} R ₈ , respectively, so that when the clock signal CLK is activated for the second time, Equation 5 is obtained as the outputs L _{0 to} L ₈ .

[0018]

[Equation 5]

Since this can be transformed into Expression 6 in the same manner as Expression 4, the signal G determines whether or not the element α ² is the root of the error locator polynomial σ (x). Similarly, when the clock signal CLK is activated for the third time, the signal G determines whether the element α ³ is the root of the error locator polynomial σ (x).

[0020]

[Equation 6]

The error position thus detected can be known by the number of times the clock signal CLK is activated. Therefore, a signal G indicating whether or not an error has occurred and a signal C indicating the number of times the clock signal CLK is activated are provided to the error position register 200e, and a record of the error position is saved every time the clock signal CLK is activated. Being done.

[0022]

In the conventional chain search circuit 200, only one element is error locator polynomial σ (x) every time the clock signal CLK is activated in this way.
Since it is determined whether the error position of the Reed-Solomon code is detected at only one place for each activation of the clock signal CLK, the error position of the Reed-Solomon code can be detected only once. There was a problem that the chain search processing time was required.

[0023]

[Equation 7]

The present invention has been made to solve the above problems, and provides a code error position detection circuit capable of detecting an error position of a Reed-Solomon code in a short chain search processing time. Is intended.

[0025]

A code error position detection circuit according to the present invention detects an error position of a Reed-Solomon code in which an nth-order error position polynomial and an nth-order primitive polynomial are set.

In the first mode, (a) in the initial state, the coefficients of each degree of the error locator polynomial are respectively stored, (a-1) an input end and an output end, and (a-2)
Control input terminals to which a clock signal for controlling the operation of supplying the stored data to the output terminal and the operation of newly storing the data supplied to the input terminal are input; ≧ 1) degree correspondence storage means,
(B) It is provided for each of the i-th (0 ≦ i ≦ n) order correspondence storage means and is connected in series between the input end and the output end of the i-th order correspondence storage means. Is
K multipliers M _ij (1 ≦ j ≦) that perform multiplication with a predetermined multiplier in the Galois field determined by the primitive polynomial.
k, 2 ≦ k), and (c) first to kth addition means for performing modulo-2 addition on the output of the multiplier M _ij ,
(D) A counter that counts the number of times the clock signal is activated. Here, the predetermined multiplier in the multiplier M _ij is equal to α ^{p + i} in all j, and the α ^p is selected from an element of a finite field defined by the root of the primitive polynomial.

In a second aspect of the code error position detection circuit according to the present invention, (a) in the initial state, the coefficients of each degree of the error position polynomial are stored, respectively, and (a-1)
A control input for inputting an input end and an output end, and (a-2) a clock signal for controlling an operation of giving the stored data to the output end and an operation of newly storing the data given to the input end. 0th to nth (n ≧)
1) the degree correspondence storage means, and (b) the i-th (0 ≦ i ≦
n) is provided for each of the degree correspondence storage means, is connected to the input terminal of the i-th degree correspondence storage means, and performs k multiplication by a predetermined multiplier in a Galois field determined by the primitive polynomial. Multiplier M _ij (1 ≦ j ≦ k,
2 ≦ k), (c) first to k-th addition means for performing modulo-2 addition on the output of the multiplier M _ij , and (d)
A counter that counts the number of times the clock signal is activated. The output of the multiplier M _ik is the i th
Connected to the output terminal of the degree correspondence storage means of, the predetermined multiplier in the multiplier M _ij is α ^{(p + i) j} , and α ^p is a finite field defined by the root of the primitive polynomial. Selected from the original.

As a third aspect of the code error position detection circuit according to the present invention, it is desirable that (e) a logic processing unit that obtains a logical product of the outputs of the first to kth addition means,
(F) error position specifying data generation means for coding the outputs of the first to kth adding means to generate error position specifying data; and (g) the clock signal as error position basic data, and the error position. An error position storage means for storing the specific data at a predetermined address, and (h) an address generation means for generating the predetermined address based on the output of the logic processing unit are provided.

[0029]

In the first and second aspects of the present invention, the i-th
The value stored in each of the degree correspondence storage means of is sequentially multiplied by (α ^{p + i} ) ^k by the activation of the clock signal. On the other hand, the j-th addition means detects whether or not α ^{j + (s−1) k} is the root of the error locator polynomial by the activation of the s-th clock signal.

In the third aspect of the present invention, the clock signal is stored as error position basic data, and the error position specifying data is stored in the error position storage means for each address.

[0031]

【Example】

First Embodiment: FIG. 1 is a circuit diagram showing the basic concept of a chain search circuit according to a first embodiment of the present invention. Between the output terminal and the input terminal of the order latch register R _i , k number of multipliers M _i1 , M _i2 , ..., M _ik are connected in series, and outputs L _i1 , L _i2 , ..., From each of them. _Lik is obtained.

[0032] Now, consider a case where one a _i coefficients of the error locator polynomial sigma (x) is held in order latch register R _i. At this time, when the clock signal CLK is activated once, the data a given to the order latch register R _i
i is given to the multiplier M _i1 to obtain the output L _i1 . This output L _i1 is further given to the multiplier M _i2 to obtain the output L _i2 .

In this first embodiment, the multipliers M _i1 ,
_{Each of} M _i2 , ..., M _ik has a structure in which the same element of a Galois field is multiplied. For example, which multiplier M
_{It is assumed} that _i1 , M _i2 , ..., M _ik are also multiplied by the same element α ⁱ of a certain Galois field. However, the calculation is performed in the Galois field corresponding to the error locator polynomial σ (x).

In this case, each output L _i1 , L _i2 , ..., L
_ik is expressed as in _Equation 8.

[0035]

[Equation 8]

Therefore, by activating the clock signal CLK once, k outputs L _i1 , L _i2 , ..., L _ik are obtained from one order latch register. Therefore, in each of the plurality of order latch registers provided corresponding to the error locator polynomial σ (x), a multiplier connected in series as shown in FIG. 1 and performing the same multiplication process is provided. For example, by activating the clock signal CLK once, it is possible to detect k error positions.

FIG. 2 is a circuit diagram showing the structure of the chain search circuit 101 according to the first embodiment of the present invention. The chain search circuit 101 corresponds to the error locator polynomial σ (x) represented by Expression 1, and each of them has 8-bit order latch registers R _{0 to} R ₈ . Coefficients a _{0 to} a _{8 of the} error locator polynomial σ (x) are latched in the order latch registers R _{0 to} R ₈ , respectively. The clock signal CLK is applied as a trigger to all the order latch registers R _{0 to} R ₈ .

A multiplier M ₀₂ is connected to the output terminal of the order latch register R ₀ via a multiplier M _01.
The output terminal of ₀₂ is connected to the input terminal of the order latch register R ₀ . Then, each of the multipliers M ₀₁ and M ₀₂ performs an operation of multiplying by the same element α ¹²⁰ . The Galois field having an element selected here is a primitive polynomial in the Galois field of GF (2 ⁸ ).

[0039]

[Equation 9]

Based on the root β ⁱ of α, α ⁱ = (β ⁸⁸ ) ⁱ is obtained.

Outputs L ₀₁ and L ₀₂ are obtained from the multipliers M ₀₁ and M ₀₂ , respectively. First time clock signal CLK
When is activated, these are expressed as in Eq.

[0042]

[Equation 10]

Similarly, the order latch register R _i (i =
A multiplier M _i2 is connected to the output ends of 1 to 8) via a multiplier M _i1 . Then, each of the multipliers M _i1 and M _i2 performs an operation of multiplying by the same element α ^{120 + i} . Therefore, when the clock signal CLK is activated for the first time, two sets of nine outputs are obtained. That is,

[0044]

[Equation 11]

And

[0046]

[Equation 12]

It is

The outputs L _{01 to} L ₈₁ are applied to the adders A _{01 to} A ₈₁ together for each bit, and the addition of modulo 2 is performed. This result is given to the OR gate 101a for each bit and the logical sum is taken to obtain the signal G ₁ . By performing such an operation, the values obtained by the equations 3 and 4 are obtained as the signal G ₁ , and it is possible to determine whether or not α is the root of the error locator polynomial σ (x). .

On the other hand, the outputs L _{02 to} L ₈₂ are supplied to the adders A _{02 to} A ₈₂ together for each bit, and the modulo 2 addition is performed. The result is the OR gate 101b for each bit.
And the logical sum is taken to obtain the signal G ₂ . As can be seen by comparing Equation 12 with Equation 5, the value obtained in Equation 6 is obtained as the signal G ₂ by performing such an operation, so α ² is the root of the error locator polynomial σ (x). It is possible to determine whether or not

After all, by activating the clock signal CLK once, it is possible to determine whether the Reed-Solomon code is erroneous at the positions corresponding to the two elements α and α ² .

Counter 101e, arithmetic units 101c, 10
1d operates to store the detection result of the error position.
Before describing the connection relationship and operation of these, the specific configuration of the multipliers M _{01 to} M ₈₁ and M _{02 to} M ₈₂ will be described.

As described above, since these multipliers perform multiplication in the Galois field, they do not simply multiply a certain value by the value held by the order latch register. Based on the root β ⁱ of the 8th-order primitive polynomial p (X) expressed by Equation 9, (β
⁸⁸⁾ a predetermined process corresponding to the alpha ⁱ obtained as ⁱ is performed.

For example, it is assumed that the zero-order coefficient a ₀ of the error locator polynomial σ (x), which is held in the order latch register R ₀ , is an 8-bit number expressed by the equation 13.

[0054]

[Equation 13]

The processing of the multiplier M ₀₁ of multiplying this by α ^{120 corresponds} to obtaining the 8-bit output L ₀₁ shown in the equation (14).

[0056]

[Equation 14]

That is, when the coefficient a ₀ and the output L ₀₁ are expanded into a column vector, they are related by the matrix shown in the equation 15, and this matrix corresponds to the element α ¹²⁰ .

[0058]

[Equation 15]

Both equations (14) and (15) are performed by addition of modulo 2, and specifically, the multiplier M
₀₁ can be configured by an EXOR gate. FIG. 3 shows an example of the configuration of the multiplier M ₀₁ , and the multiplier M ₀₂ that performs the process of multiplying the same element α ¹²⁰ can also have the same configuration.

Since the multiplier M ₀₂ multiplies the output L ₀₁ by α ¹²⁰ , the output L ₀₂ and the coefficient a ₀ are given by
Will be related by a matrix that is the square of the matrix shown in. That is,

[0061]

[Equation 16]

There is a relation of (3), which corresponds to the first multiplication described in the equation (12).

I-th coefficient a _{i of the} error locator polynomial σ (x)
If (i = 1 to 8) is an 8-bit number represented by Expression 17, the multiplier M that multiplies the coefficient a _i by α ^{120 + i}
processing _i1 corresponds to obtaining the output L _i1 of 8 bits represented by the number 18 to number 25.

[0064]

[Equation 17]

[0065]

[Equation 18]

[0066]

[Formula 19]

[0067]

[Equation 20]

[0068]

[Equation 21]

[0069]

[Equation 22]

[0070]

[Equation 23]

[0071]

[Equation 24]

[0072]

[Equation 25]

Corresponding to each of the equations 19 to 25,
The multiplier M _i1 (i = 1 to 8) has a configuration shown in FIGS. 4 to 11 by a plurality of EXOR gates. Multiplier M _i2
Also has the same configuration as the multiplier M _i1 .

Returning to FIG. 2, the first clock signal CLK
It is possible to determine whether or not the Reed-Solomon code is erroneous at the positions corresponding to the two elements α and α ² by the activation of the second time. And the second time clock signal CLK
Is activated, the order latch register R _i (i =
0 to 8), a _i α ^{240 + 2i} is given to the multiplier M _i1 respectively, so that the outputs L _i1 and L _i2 are respectively a
_i α ^{360 + 3i} and a _i α ^{480 + 4i} . Therefore, at this time, two elements α ³ and α ⁴ are respectively generated by the signals G ₁ and G ₂ .
Is a root of the error locator polynomial σ (x), that is, whether or not an error has occurred at the positions of the codes corresponding to these elements.

The counter 101e outputs, as a signal C, the number of times the clock signal CLK is activated. Arithmetic unit 101
The c and 101d receive the signal C and output a value obtained by subtracting 1 from twice the value indicated by the signal C and a value obtained by doubling the value.

For example, when the sign is wrong at the positions corresponding to the elements α ³ and α ⁸ of the Galois field, the operation of the conventional chain search circuit 200 and the chain search circuit 101 of the first embodiment of the present invention is performed. Let's compare in.

12 and 13 are timing charts showing the operation of the chain search circuits 200 and 101, respectively. First, the operation of the chain search circuit 200 will be described (see also FIG. 20). The counter 200b outputs the signal C output by the activation of the clock signal CLK.
Increment the value of by one. And the elements α ³ and α ⁸
Since there is a code error at the position corresponding to
The elements α ³ and α ⁸ are the error locator polynomial σ (x) shown in Equation 1.
Is the root of the signal G, and the signal G takes the value "0" when the values of the signal C correspond to "3" and "8". The clock signal CLK must be activated eight times before this error position is detected.

On the other hand, in FIG. 13, the operation of the chain search circuit 101 (see also FIG. 2) causes the arithmetic unit 10 to operate.
The outputs of 1c and 101d are shown as 2C-1 and 2C, respectively. As described above, the first clock signal C
By activating LK, the elements α and α ² become error locator polynomial σ
It is determined whether or not it is the root of (x). After that, every time the clock signal CLK is activated, the original (α ³ , α ⁴ ), (α
^Since it is determined whether or not each pair of ⁵ , α ⁶ ) and (α ⁷ , α ⁸ ) is a root of the error locator polynomial σ (x), α ³ and It is detected that α ⁸ is a root. The clock signal CLK is used for this detection.
Need only be activated four times.

As described above, k (k ≧ 2) multipliers that perform the same operation are connected in series between the input end and the output end of one order latch register, and the multipliers of each multiplier are connected. By adding modulo 2 to the output, it is possible to determine whether or not there are errors in k positions by one activation of the clock signal CLK.

After all, the chain search processing time required to detect the error position of the code is

[0081]

[Equation 26]

As shown by, it is possible to obtain the effect of being shortened to 1 / k as compared with the conventional case.

Second Embodiment: Generally, the maximum number of error positions that can be detected has an upper limit depending on the capability of the error correction code. Therefore, there is an upper limit on the maximum number of error positions detected by the chain search circuit. An error position register for storing error position information is provided according to this number. The error position register 200c in FIG. 20 corresponds to this.

However, when there are a plurality of signals G ₁ and G ₂ which provide information on error positions in parallel as in the first embodiment, the error position information is stored in accordance with the upper limit of the maximum number of error positions. If the error position register is simply provided for each of these signals G ₁ and G ₂ , the required register capacity will be doubled.

Therefore, the second embodiment of the present invention provides a technique for storing error position information by an error position register having a small capacity even if there are a plurality of signals having error position information.

FIG. 14 is a block diagram showing the structure of the chain search circuit 102 according to the second embodiment of the present invention. The chain search circuit 102 is the chain search circuit 1
01, an AND gate 102a, an error position specifying data generator 102b, an address generator 102c, a write pulse generator 102d, and an error position register 102e are further added. However, since these additional constituent elements specify the error position and store the information thereof, the arithmetic units 101c and 10c in the chain search circuit 101 are described.
1d is not always necessary.

The AND gate 102a receives the signals G ₁ and G ₂
When any of the above is "0", the value "0" is output. The address generator 102c and the write pulse generator 10
2d inputs the output of the AND gate 102a and the clock signal CLK.

When either of the signals G ₁ and G ₂ is "0", there is a code error and the AND gate 10
When the output of 2a is "0", the clock signal CLK
The address generator 102c and the write pulse generator 102d are respectively synchronized with the error position register 102e.
Address P and a write pulse Q are generated, and the address P and error position specifying data D and error position basic data described later are written in the error position register 102e.

The signal C output from the counter 101e is used as error position basic data, and the signals G ₁ and G ₂ are coded into error position specifying data D by the error position specifying data generator 102b. 1
02e.

In the error position register 102e, the address P, the error position specifying data D, and the error position basic data (signal C) are stored in the areas 102f, 102g, 102, respectively.
It is stored in association with h. In this way, since the error position information can be written in the same error position register 102e regardless of which of the signals G ₁ and G ₂ is obtained, the required capacity is smaller than that in the conventional case. It is sufficient to add a few bits of data to each address.

FIGS. 15 and 16 are timing charts showing the operations of writing to the error position register 200e in the chain search circuit 200 and writing to the error position register 102e in the chain search circuit 102, respectively.

First, the operation of the chain search circuit 200 will be described. In FIG. 15, the clock signal CL
Each time K is activated, the number of the signal C output from the counter 200b is increased by one. Now, consider the case where the sign is incorrect at the positions corresponding to the elements α ³ , α ⁴ , α ⁶ , and α ⁷ of the Galois field. At this time, OR gate 20
In the signal G which is the output of 0a, the signal C has the value "3",
When taking "4", "6", "7", take the value "0",
Other than that, it takes “1”.

The address generator 200c receives the signal G and the clock signal CLK and receives the address P.
To occur. Here, an example is shown in which the address P is updated one by one each time the error position is detected, starting with the value “1”, but it is not always necessary to generate the address in this way.

The write pulse generator 200d also receives the signal G and the clock signal CLK and generates a write pulse Q. Here, when the error position is detected (when the signal G takes the value "0"), the write pulse Q taking the value "0" is generated at the timing when the clock signal CLK takes the value "0". There is no need to synchronize at timing.

The error position register 200e stores the address P when the write pulse Q is received. In such an operation, the chain search processing time takes seven times as long as one cycle of the clock signal CLK to detect the error position.

On the other hand, as shown in FIG. 16, also in the operation relating to the chain search circuit 102, the number of the signal C which is the output of the counter 101e is incremented by one each time the clock signal CLK is activated. As in the above case, if the sign is wrong at the positions corresponding to the elements α ³ , α ⁴ , α ⁶ , and α ⁷ of the Galois field, the signal G ₁ is the signal C having the values “2” and “4”. When it is taken, it takes the value "0", and otherwise it takes "1". And signal G ₂
Takes the value "0" when the signal C takes the values "2" and "3", and takes "1" otherwise.

The logical product AND gate 102a of the signals G ₁ and G ₂ is taken, and the address generator 102c receives this and the clock signal CLK to generate the address P. Here, an example is shown in which the address P is updated one by one each time the error position is detected, starting with the value “1”, but it is not always necessary to generate the address in this way.

The write pulse generator 102d also receives the logical sum of the signals G ₁ and G ₂ and the clock signal CLK to generate a write pulse Q. Here, when the error position is detected (when the signal G ₁ or G ₂ takes the value “0”), the write pulse Q taking the value “0” is generated at the timing when the clock signal CLK takes the value “0”. It is not always necessary to perform synchronization at such timing.

The error position register 102e stores the address P when the write pulse Q is received. In such an operation, the chain search processing time is four times as long as one cycle of the clock signal CLK to detect the error position.

Error position specifying data D is also given to the error position register 102e. This is obtained by coding the signals G ₁ and G ₂ , and the coding shown in Table 1 is performed.

[0101]

[Table 1]

That is, when the signals G ₁ and G ₂ both take the value "0", the error position specifying data D takes the value "2". When the signals G ₁ and G ₂ take the values “1” and “0”, respectively, the error position specifying data D takes “1”, and the signals G ₁ and G
_{When 2} takes the values "0" and "1" respectively, the error position specifying data D takes "0". When the signals G ₁ and G ₂ both take the value “1”, the error position specifying data D takes other values.

Accordingly, since the error position basic data (signal C) and the error position specifying data D are stored in the error position register 102e for each address P, the error position can be specified. The signals G ₁ and G ₂ respectively correspond to a value obtained by subtracting 1 from the value of the error position basic data and a value of 2 times the value of the error position basic data, and therefore, for example, the value of the position basic data stored at address 3 From "4" and the value "0" of the error position identification data D, there is an error in the position corresponding to α ^{2 4-1} = α ⁷ , and there is no error in the position corresponding to α ^{2 4} = α ^8. I understand.

Therefore, in the second embodiment, even if there are a plurality of signals having error position information, the error position information can be stored by the error position register having a small capacity.

Third Embodiment: In the first embodiment, a configuration is shown in which a plurality of multipliers are provided in series between the input terminal and the output terminal of the order latch register, but the multiplier is used as the input terminal of the order latch register. The same effect can be obtained also by providing a plurality in common.

FIG. 17 is a circuit diagram showing the basic concept of the chain search circuit according to the third embodiment of the present invention. K _j multipliers M _j1 , M _j2 , ..., M _jk are commonly connected to the input terminal of the order latch register R _j , and outputs L _j1 , L _j2 , ..., L _jk are obtained from each of them. .

[0107] Now, consider a case where one a _j of the coefficients of the error position polynomial sigma (x) is held in order latch register R _j. At this time, when the clock signal CLK is activated once, the data a given to the order latch register R _j is
_j is given to the multiplier M _j1 to obtain the output L _j1 . The coefficient a _j is also given to the multiplier M _j2 to obtain the output L _j2 .

In the third embodiment, the multiplier M _j1 ,
M _j2 , ..., M _jk have a function of sequentially multiplying by a value having a power that is an integral multiple of the value of an element of a certain Galois field. However, the calculation is performed in the Galois field corresponding to the error locator polynomial σ (x).

For example, it is assumed that the multiplier M _j1 performs an operation for multiplying the same element α _j of a Galois field. At this time, each of the multipliers M _j1 , M _j2 , ..., M _jk has α _j , α _j ² , and
,, has a function of multiplying by α _j ^k .

In this case, each output L _j1 , L _j2 , ..., L
_jk is expressed as in _Expression 27.

[0111]

[Equation 27]

Therefore, by activating the clock signal CLK once, k outputs L _j1 , L _j2 , ..., L _jk are obtained from one order latch register R _j . And the multiplier M
The output of _jk is provided as an input to the order latch register R _j . Therefore, each of the plurality of order latch registers provided corresponding to the error locator polynomial σ (x) is commonly connected as shown in FIG. 17 and sequentially has an integer multiple value as a power number. If a multiplier for multiplying the values is provided, it is possible to detect k error positions by activating the clock signal CLK once.

As can be seen by comparing the equations 27 and 8, the k outputs L _j1 , L _j2 , ..., L _jk are substantially equal to the k outputs L _i1 , L _i2 , ..., L _ik. Are the same, the chain search circuit having a similar structure to the first embodiment can be constructed in the third embodiment.

FIG. 18 is a circuit diagram showing the structure of the chain search circuit 103 according to the third embodiment of the present invention, which corresponds to FIG. 2 in the first embodiment.

The chain search circuit 103 is different from the chain search circuit 101 in the connection relation between the multipliers M _j1 and M _j2 and the order latch register R _j (j = 0 to 8). The output end of degree latch register R _j as described in Figure 17 are connected in common multipliers M _j1, M _j2, output L ₀₂ of the multiplier M _j2 is supplied to the input terminal of the degree latch register R _j To be

The multipliers M _j1 and M _j2 are respectively α ^{120 + j} and α
Perform an operation of multiplying by ^{240 + 2j} . For example, multipliers M ₀₁ and M ₀₂
Performs multiplication by α ¹²⁰ and α ²⁴⁰ , respectively. In this case, the multiplier M ₀₁ can have the configuration shown in FIG. 3, for example. Further, the multiplier M ₀₂ can have the configuration shown in FIG. 19, for example.

Therefore, when the clock signal CLK is activated for the first time, two sets of nine outputs can be obtained.
That is, there are two sets represented by equations 11 and 12. Therefore, at this time, it is determined whether or not the elements α and α ² are roots of σ (x). Then, when the clock signal CLK is activated for the second time, it is determined whether or not the elements α ³ and α ⁴ are the roots of σ (x).

Therefore, also in the third embodiment, the chain search processing time can be shortened as in the first embodiment.

[0119]

As concretely shown in the above embodiment, in the first and second aspects of the present invention, the j-th addition means is activated by the activation of the s-th clock signal to generate the original α.
^Since it is possible to determine whether the code at the position corresponding to ^{j + (s-1) k} is incorrect, the processing time required for detecting the error position of the code can be shortened to 1 / k.

According to the third aspect of the present invention, the first aspect
Also, there is an effect that the detection result obtained in the second aspect can be stored without requiring a large capacity.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a basic concept of a chain search circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a chain search circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating a first embodiment of the present invention.

FIG. 4 is a circuit diagram illustrating a first embodiment of the present invention.

FIG. 5 is a circuit diagram illustrating a first embodiment of the present invention.

FIG. 6 is a circuit diagram illustrating a first embodiment of the present invention.

FIG. 7 is a circuit diagram illustrating a first embodiment of the present invention.

FIG. 8 is a circuit diagram illustrating a first embodiment of the present invention.

FIG. 9 is a circuit diagram illustrating a first embodiment of the present invention.

FIG. 10 is a circuit diagram illustrating a first embodiment of the present invention.

FIG. 11 is a circuit diagram illustrating a first embodiment of the present invention.

FIG. 12 is a timing chart for explaining the operation of the conventional technique.

FIG. 13 is a timing chart for explaining the operation of the first embodiment of the present invention.

FIG. 14 is a circuit diagram showing a configuration of a chain search circuit according to a second embodiment of the present invention.

FIG. 15 is a timing chart explaining the operation of the conventional technique.

FIG. 16 is a timing chart for explaining the operation of the second embodiment of the present invention.

FIG. 17 is a circuit diagram showing a basic concept of a chain search circuit according to a third embodiment of the present invention.

FIG. 18 is a circuit diagram showing a configuration of a chain search circuit according to a third embodiment of the present invention.

FIG. 19 is a circuit diagram illustrating a third embodiment of the present invention.

FIG. 20 is a circuit diagram illustrating a conventional technique.

[Explanation of symbols]

R _i , R _j , R _{0 to} R ₈ : Order latch registers M _{i1 to} M _ik , M _{j1 to} M _jk , M ₀₁ , M ₀₂ , ..., M ₀₁ ,
M ₀₂ : Multipliers A _{01 to} A ₈₁ , A _{02 to} A ₈₂ : Adders 101a and 101b: OR gate 102a: AND gate 102e: Error position register

Claims (3)

[Claims] 1. A code error position detection circuit for detecting an error position of a Reed-Solomon code in which an nth-order error locator polynomial and an nth-order primitive polynomial are set, comprising: (a) in an initial state, The coefficient of each degree of the error locator polynomial is stored, and (a-1) the input end and the output end, and (a-2) the operation of giving the stored data to the output end and the input end. 0th to nth (n ≧ 1) degree correspondence storage means having a control input terminal to which a clock signal for newly storing data is input, and (b) the i-th (0 ≦ i) ≦ n), which is provided for each of the degree correspondence storage means and is connected in series between the input end and the output end of the i-th order correspondence storage means,
K multipliers M _ij (1 ≦ j ≦) that perform multiplication with a predetermined multiplier in the Galois field determined by the primitive polynomial.
k, 2 ≦ k), (c) first to k-th addition means for adding modulo 2 to the output of the multiplier M _ij , and (d) measuring the number of times the clock signal is activated. And a counter for performing the predetermined multiplier in the multiplier M _ij is equal to α ^{p + i} in all j, and α ^p is selected from an element of a finite field defined by the root of the primitive polynomial. A code error position detection circuit. 2. A code error position detection circuit for detecting an error position of a Reed-Solomon code in which an nth-order error locator polynomial and an nth-order primitive polynomial are set, wherein: (a) in the initial state, The coefficient of each degree of the error locator polynomial is stored, and (a-1) the input end and the output end, and (a-2) the operation of giving the stored data to the output end and the input end. 0th to n-th (n ≧ 1) degree correspondence storage means having a control input terminal to which a clock signal for newly storing data is input, and (b) the i-th (0 ≦ i) ≦ n) provided for each of the degree correspondence storage means, and connected to the input end of the i-th degree correspondence storage means,
K multipliers M _ij (1 ≦ j ≦) that perform multiplication with a predetermined multiplier in the Galois field determined by the primitive polynomial.
k, 2 ≦ k), (c) first to k-th addition means for adding modulo 2 to the output of the multiplier M _ij , and (d) measuring the number of times the clock signal is activated. And a counter for connecting the output of the multiplier M _{ik to} the output end of the i-th degree correspondence storage means, and the predetermined multiplier in the multiplier M _ij is α ^{(p + i) j} . Yes, the α ^p is selected from an element of a finite field defined by the root of the primitive polynomial, and a code error position detection circuit. 3. (e) a logical processing unit which obtains a logical product of outputs of the first to kth adding means; and (f) an output of the first to kth adding means is coded to identify an error position. Error position specifying data generating means for generating data, and (g) the clock signal as error position basic data,
The error position storage means for storing the error position identification data at a predetermined address, and (h) address generation means for generating the predetermined address based on the output of the logic processing unit. Alternatively, the code error position detection circuit according to item 2.