JPS63123231A - Error location detector - Google Patents

Abstract

PURPOSE:To decrease the clock pulse and the processing time by providing plural sets of a coefficient device group multiplying a constant with a register output, adders and zero detectors so as to obtain the result of substitution of elements to plural error location polynomial at the same time. CONSTITUTION:Plural register groups 5-8 store coefficients sigma3-1 of each term of an error location polynomial inputted to input terminals 1-4. In giving a clock pulse to registers 5-8, the content of registers 6-8 is revised to a value multiplied with coefficients alpha<2>-alpha<6> set to coefficient devices 9-11. An adder 5 sums outputs of each said register and an adder 16 sums outputs of the said registers multiplied by coefficients alpha-alpha<3> of coefficient devices 12-14. The obtained total sum is discriminated by zero detection means 17, 18 and when the total sum is zero, the detection output is stored in the error location register 11 as the error location.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention is used for decoding BCH codes and Reed-Solomon codes to correct code errors in digital data transmission systems and recording/reproducing systems. The present invention relates to an error position detection device.

BACKGROUND OF THE INVENTION In recent years, digitalization has been rapidly progressing in the fields of information transmission and information recording. In particular, although there has been a remarkable increase in speed and density in terms of transmission speed and recording density, code errors in digital data that occur during transmission or recording/reproduction are becoming inevitable. In this trend, error correction codes and their encoding/decoding systems for detecting and correcting code errors are becoming important, but BCH codes and Reed-Solomon codes are especially important. From a practical standpoint, it can be said to be the most important code.

In the process of decoding BCH codes and Reed-Solomon codes, the procedure is generally to find the error position polynomial from the syndrome and find the error position from the root of the error position polynomial. The error position detection device for finding the root of the input error position polynomial and outputting the error position can be said to be one of the most important elements in the code decoding process described above.

Conventionally, Cheno's algorithm has generally been used for such error position detection, but it has also been made into a device and widely used (for example, Miyayo, Iwadare, ``Coding Theory'')
(Sho 48), Shokodo, pp. 262-264).

The conventional error position detection apparatus as described above will be described below with reference to the drawings, but here, as an example, a case will be considered in which three error positions are determined from a third-order error position polynomial. Also, considering the code as a non-binary code,
Suppose that it is an element of a finite field CF (2q).

FIG. 2 is a block diagram showing the configuration of a conventional error position detection device, in which 31 to 34 are input terminals for coefficients of each term of the error position polynomial, and 35 to 38 are connected to input terminals 31 to 34. , q-bit wide register, 39 is register 360
Coefficient multiplier, 4o, connected between input/output and multiplying by constant α
is a coefficient unit connected between the input and output of register 37 to multiply by a constant α, 41 is a coefficient unit connected between the input and output of register 38 and is multiplied by constant α, and 42 is an adder connected to the output of each register. 43 is a zero detector connected to the output of the adder 42, 44 is an error position register connected to the zero detector 43, and 45 is an output terminal for outputting the error position.

Next, the operation of the error position detection device configured as described above will be explained.

First, the third-order error locator polynomial to be solved is σ(x)=x +σ1x+σ2x+σ5...
...Place it as (1). Since this error location polynomial has three error locations as three roots, the process of determining the error location is nothing but solving the equation: σ(X)=O...僻). The simplest method to solve this equation is to sequentially substitute 2-1 elements excluding zero into equation (1), and take the element whose result is zero as the root. According to this method, no matter how high-order the error locator polynomial is, it can be solved as long as the long processing time is not a problem.

The error position detection device shown in FIG. 2 is a device based on the method described above. First, the coefficient σ3 of each term of the error position polynomial is calculated. σ2. σ1 and 1 are input to registers 36-38 through input terminals 31-34, respectively. The adder 42 is for calculating the sum of the outputs of each register, and in this state, the output of the adder 42 is 1+σ1+σ2+σ5=σ(1), that is, 1 is substituted into equation (1). It will be hail.

Next, when a clock pulse is applied once to each register 35 to 3B, there is no change in the register 35 since its input and output are directly connected, but the input/output of the register 36 does not change.
Since a coefficient multiplier 39 for multiplying by a constant α is connected between the outputs, the contents stored in the register 36 change to the contents before the clock pulse is applied multiplied by α. Similarly, the contents of the register 37 are multiplied by α by the coefficient unit 4o, and the contents of the register 38 are changed by the coefficient unit 41 by α.

Here, α is the primitive light of the finite field GF (2q), and therefore all elements of the finite field GF (2q) are raised to the power of α. Now, if we consider the output of the adder 42 in this state, we can see that α+ασ1+ασ2+σ3=σ(α), which is obtained by substituting α into equation (1).

In the same way, when clock pulses are sequentially applied to each register, the output of the adder 42 is sequentially expressed as α in equation (1).
, α, ...... will be changed, so
By applying 2q-1 clock pulses, it is possible to obtain the value obtained by substituting all elements into equation (1) at the output of the adder 42. The reason why this value becomes zero is
That is, since it is the root of the equation (2), the zero detector 4
3, the error position can be obtained by
It will be output from 6.

Problems to be Solved by the Invention However, in the above configuration, it is essential to input the clock pulse 2-1 times, and therefore, when q becomes large to a certain extent, the time required for processing becomes extremely large. It had a serious problem.

In view of the above problems, the present invention provides an error position detection device that can reduce the required clock pulses by half and significantly shorten processing time.

Means for Solving the Problems In order to solve the above problems, the error position detection device of the present invention includes an adder and a zero detector that simply add register outputs, as well as a device that multiplies the register outputs by a constant. By providing a plurality of sets of coefficient units, adders, and zero detectors, it is possible to perform a plurality of assignment operations at the same time.

Effect of the Invention With the above-described configuration, the present invention greatly reduces the number of required clock pulses by simultaneously obtaining a plurality of original assignment results to error locator polynomials by inputting a single clock pulse. Processing time can be significantly reduced.

Embodiment Hereinafter, an error position detection device according to an embodiment of the present invention will be described with reference to the drawings.

Figure 1 shows the configuration of an error position detection device in an embodiment of the present invention. In Figure 1, 1 to 4 are input terminals for the coefficients of each term of the error locator polynomial, 6 to 8 are q-bit wide registers connected to input terminals 1 to 4, and 9 is between the input and output of register 6. 10 is a coefficient machine connected between the input/output of register 7 and multiplies it by a constant α4. 11 is a coefficient machine connected between the input/output of register 8 and multiplies it by a constant α. , 16 is an adder connected to the output of each register, and 18 is a zero detector connected to the output of the adder 15.

The above configuration is similar to the conventional configuration already described.

Further, 12 is a coefficient unit that multiplies the output of register 6 by a constant α, 13 is a coefficient unit that is connected to the output of register 7 and is multiplied by a constant α, and 14 is a coefficient unit that multiplies the output of register 8 by a constant α. Coefficient unit, 16 is an adder connected to each coefficient unit output and the output of the register, 17 is adder 1
A zero detector connected to the output of 6. Further, 19 is an error position register connected to the zero detector 17 and the zero detector 18, and 20 is an output terminal for outputting the error position.

The operation of the error position detection device configured as described above will be described below. Again, find the roots of the third order error locator polynomial, i.e. the equation σ(x)=x+σ1x
+σ2x+σ5=.

Consider solving the equation to detect three error positions.

First, the coefficient σ3 of each term of the error locator polynomial. σ2. σ1° and 1 are input to registers 5-8 through input terminals 1-4, respectively. Considering the output of the adder 15 in this state, the output obtained by substituting 1 for σ(X), ie, σ(1)=1+σ1+σ2+σ5, is obtained as in the conventional configuration.

At the same time, the adder 16 receives the output of the register 6 and the coefficient unit 1.
The output of register 6 multiplied by α by 2, the output of register 7 multiplied by α by coefficient unit 13, and the output of register 8 multiplied by α by coefficient unit 14 are added, so the output is is the result of substituting α into σ(X), that is, σ(α)=α +ασ1+ασ2+σ
5 hail.

Next, when a clock pulse is applied to each register once, there is no change in register 6 since its input and output are directly connected, but a coefficient multiplier 9 multiplies the input and output of register 6 by a constant α. is connected, the contents stored in the register 6 change to the contents before the clock pulse is applied multiplied by α. Similarly, the contents of register 7 are multiplied by α by coefficient unit 1o, and the contents of register 8 are changed by coefficient unit 11 by α.

Therefore, the output of the adder 15 is σ(X) substituted with α2, and similarly, the output of the adder 16 is σ(X)
Substituting α into will result in hail. The substitution results obtained in this way are
It is determined whether or not it is a root by detecting zero, and the obtained root position is sequentially stored in the error position register 19 and output from the output terminal 2o.

In this way, according to this embodiment, two substitution results can be obtained by inputting one clock pulse, so processing can be performed with half the number of clock pulses compared to the conventional method, and processing time can be shortened. .

In this embodiment, two substitution results are obtained at the same time, but an error position detection device that obtains four substitution results at the same time can be easily configured in the same manner. In this case, although the scale of the apparatus becomes larger, processing can be performed in a shorter time.

Effects of the Invention As described above, the present invention includes, in addition to an adder and a zero detector that simply add register outputs, a plurality of sets of coefficient units, adders, and zero detectors that multiply register outputs by a constant. An error position detection device that can significantly reduce the number of required clock pulses and significantly shorten processing time by simultaneously obtaining the results of original assignment to multiple error position polynomials. It is.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the configuration of an error position detection apparatus according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional error position detection apparatus. 5-8.35-38...Register, 9-11゜39-41...Coefficient unit, 15,16.42...
... Adder, 17.18.43 ... Zero detector, 19°44 ... Error position register. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2

Claims (1)

[Claims] It includes a register group for inputting and storing the coefficients of each term of the error locator polynomial, and a coefficient unit group for updating each term of the register group by multiplying it by a constant, and outputs each term of the register group. It is equipped with two or more sets of means for calculating the sum directly or after multiplying by a constant, and zero detecting means for determining whether the sum is zero, and further, the zero detecting output of each of the above zero detecting means is An error position detection device comprising an error position register for storing an error position.