SU1062752A1 - Adaptive device for redundant information processing - Google Patents

Abstract

1. ADAPTIVE DEVICE FOR PROCESSING EXCESS INFORMATION, containing the receiver, whose input is connected to the device input, the receiver output is connected to the first inputs of the subtractor, the first threshold selector and the first memory block, the output of the first threshold selector is connected to the input of the first register block, the first decoder input and the second input of the subtractor, the output of the subtractor is connected to the input of the second memory block, the outputs of which are connected respectively to the first inputs of the first keys and simultaneously with the outputs of the first sum Ora, the output of the first sumator is connected to the input of the second threshold selector, the outputs of the first keys are connected respectively to the first inputs of amplifiers, the first outputs of which are connected respectively to the first input m of the third threshold selector, the output of which is connected to the second input through a generator. m amplifiers, the second outputs of the amplifiers are connected respectively to the first inputs of the second adders, the second inputs of which are connected respectively to the outputs of the first block of registers, the outputs of the second adders connect Naturally, with the first inputs of the fourth threshold selector, the outputs of which are connected respectively to the second inputs of the decoder, the output of the decoder is connected to the first input of the second register block, the first output of which is connected to the output of the device, the output of the first memory block is connected to the first inputs of m1 correlators , the second inputs of which are connected respectively to the second outputs .m of the second block of registers, the outputs of the correlators are connected respectively to the first inputs; block determining the maximum signal, the outputs of which are connected respectively to the second inputs of the second register block, characterized in that, in order to increase the reliability of information processing, delays, second and third keys, pulse generator, register, fifth threshold selection (L the torus, the multiplier and the third adder, the output of the first threshold selector is connected via a delay line to the first input of the second key, the output of which is connected to the second inputs of the first keys and the maximum sig block The output of the first block of the pa.mti is connected to the first input of the third adder, the output of which is connected via a serially connected multiplier and fifth threshold selector to the second input of the second key, the output from the decoder is connected to the first input of the third key whose output is connected to the first input of the register, the first output of the register is connected to the second input of the third summation switch, the second outputs of the register are connected respectively to the inputs of the pulse former, the first output of which is connected to the second input of the third key cha, the second output is connected to the second inputs of the register and the first memory block. 2. The device according to claim 1, characterized in that the pulse shaper comprises an element AND, a counter, a key and a trigger, inputs of the cement And are connected to the inputs of the driver and pulses, the output of the element And soy

Description

dinene with the first inputs of the key and through the counter - trigger, the trigger output is connected to the second key input and the first output of the emulsifier, the key output is connected to the second trigger input and the second output of the pulse former.

The invention relates to telecommunications, in particular, to devices for receiving redundant signals as a whole, and may find application in discrete information transmission systems using redundant high power codes. Devices are known for optimal processing of composite signals with redundancy, generated on the basis of error-correcting codes. These devices contain multipliers, integrators and decision blocks. The devices implement the method of receiving as a whole composite signals with redundancy and provide high noise immunity of receiving 1 and 3. However, due to the complexity of the circuit implementation when processing composite signals with redundancy formed on the basis of redundant codes with the number of information symbols, more than thirty, the known devices are practically unrealizable . A device .T.IH is known for nonaggimal processing of composite signals with redundancy, the actual method of character-by-character reception of signals and containing a threshold selector, a comparator unit, a crucial unit 2. The disadvantage of such a device is; 1, the low noise immunity of receiving redundant signals. The closest to the invention in its technical essence is an adaptive device for receiving redundant information, its receiver, whose input is connected to the device input, the receiver output is connected to the first inputs of the subtractor, the first threshold selector and the first memory block, the output of the first threshold the selector is connected to the input of the first block of registers, the first input of the decoder and the second input of the subtractor, the output of the subtractor is connected to the input of the second memory block, the outputs of which are connected respectively to the first input By the first keys and simultaneously with the inputs of the first summator, the output of the first adder is connected to the input of the second threshold selector, the outputs of the first keys are connected respectively to the first inputs of the amplifiers, the first outputs of which are connected respectively to the first inputs of the third threshold threshold, the output of which through the generator is connected to the second inputs of the amplifier, the second outputs of the usi, 1itsley connected respectively to the first input (dami second adders, the second input1 1 1 kotori connected respectively to the output.m of the first b, 1 As registers, the outputs of the second cyMMaiopoB are connected respectively to the first1 1 1 and inputs of the fourth threshold), the vector, the outputs of which are connected respectively to the second inputs of the decoder, the output of the decoder is connected to the first input of the second block of registers, the first output KOiOpoiO the output of the device, the output of the first memory block is connected to the first inputs of the correlators, BTOpijie which are connected respectively to ito) 1s1m outputs of the second peiMicTpo unit), output () E1) 1 correlators are connected respectively to ne |) Zym11 inputs block poppds.leii poppy imalnogo signal k (MGO) th connected respectively to Z1 Auto |) WMOs. Bioporo b, current registers, output nepiic.iri) iiopiifOBoro selector connected to the second) cm1; 1influxes of the first keys and the block determining the maximum signal The device is characterized by a high level of information processing in information systems, data transmission systems, automated systems; telecontrol systems; ii, te signaling; telemetry information transmission systems; and other discrete information transmission systems, using composite signals with redundancy, generated on the oenove long and super-long noise-resistant codes 4. The disadvantage (w of the known device is. there is low reliability of information processing, in the case when the gradient module of the function the likelihood exceeds the specified value, which is caused by the relative stiffness of the repcmti algorithm implemented in it. It does not depend on the distance from the input composite signal with redundancy to the signal corresponding to the conversion of the first binary code combination to the regular one, when the gradient modulus is at a predetermined value, the algorithm of functioning of the known device is fixed. However, situations are possible in which, and by, the modulus of the gradient exceeds acheni raging

the binary code pattern corresponding to the first binary code pattern is not true.

The maximum likelihood criterion used in the known device implies the decisions made in favor of the allowed combination, to which the distance from the input excess signal (or its evaluation) is the smallest. With a fixed channel (for example, Gauss - the channel you can set the signal-noise ratio), the type of electrical channel signals and the known parameters of the error-correcting code, you can specify the distance Oz between the redundant signal and the output allowed code combination, the excess of which indicates ( with a certain probability) about the fallacy of the decision. Accordingly, it is possible to calculate, with the above limitations, the value of the correlation coefficient Kj. If the correlation coefficient K between the allowed code combination and the redundant signal К Кз, then the decision in favor of this resolved combination is erroneous.

In the known device, if the module exceeds the gradient of a given value, the decision is always taken in favor of the allowed combination corresponding to the input (first) binary decoder combination. It does not take into account the marked ratio of distances (correlation coefficients). If, for example, the correlation coefficient is less than the specified one, the decision on this combination is erroneous, and this reduces the accuracy of information processing.

The purpose of the invention is to increase the reliability of processing information by taking into account when making a decision information about the magnitude of the correlation coefficient between the first allowed code combination and the redundant signal if the module exceeds the likelihood function of a given value.

This goal is achieved by the fact that in an adaptive device for processing redundant information containing a receiver whose input is connected to the input of the device, the output of the receiver is connected to the first inputs of the subtractor, the first threshold selector and the first memory block, the output of the first threshold selector is connected to the input of the first block registers, the first input of the decoder and the second input of the subtractor, the output of the subtractor is connected to the input of the second p.m.t. block, the outputs of which are connected respectively to the first inputs of the first keys and single TERM first su.mmatora with inputs, the first adder output is connected to the input of the second threshold selector, the outputs of the first keys are respectively connected to first inputs of amplifiers, the first outputs of which are connected respectively to the first inputs of the third threshold selector, the output

which through the generator is connected to the second inputs of the amplifiers, the second outputs of the amplifiers are connected respectively to the first inputs of the second adders, the second inputs of which are connected respectively to the outputs of the first block of registers, the outputs of the second adders are connected respectively to the first inputs of the fourth threshold selector, the outputs of which are connected respectively to the second inputs decoder, the decoder output is connected to the first input of the second block of registers, the first output of which is connected to the output of the device, the output of the first the memory unit is connected to the first inputs of the correlators, the second inputs of which are connected respectively to the second outputs of the second register register, the outputs of the correlators are connected respectively to the first inputs of the maximum-range detection unit, the outputs of which are connected respectively to the second inputs of the second register register, delay lines are entered , second and third keys, pulse generator, register, fifth threshold selector, multiplier and third adder, the output of the first threshold selector is connected via a delay line With the input input m of the second key, the output of which is connected to the second inputs of the first keys 11 of the maximum signal determination unit, the output of the first memory block is connected to the first input of the third adder, the output of which is connected through a serially connected multiplier and fifth nor -s selector connected to the second input of the second key; the output of the deco.chera is connected to the first input of the third Q.1K) clock, the output of which is connected to the black register register, the first output of the register; connected to the second in () of the third adder, the second Biiixo. The pciHctra is connected respectively to the inputs of the pulse former, the nerve output of which is connected to the second input of the third key, the second is connected to the second inputs of the register and the first memory block. And formatimy nmih. contains the element And, the counter, the key and the trigger, the inputs of the eucept 12 and the keys to the inputs of the 1MPU mapper: 1c () c, the output of the eIptem AND is connected to the first key inputs n via the counter trigger, the output of the trigger is connected to the second input. of the key and the first output of the driver and pulse, the key input is connected to the second trigger input and the second output of the driver.

FIG. 1 shows the structural scheme of the adaptive apparatus for processing redundant information; in fig. 2 - functional diagram of the fop nonates of impulses; on with | zpg. 3 is a functional diagram of the second pciiiCTpoB block.

The antithetical ycTpoiicTBo for processing redundant information contains receiver 1 (analog demodulator), threshold selector 2, e.c..msp 3 comparison, source 4 threshold voltage, B1z reader; 1 5, blocks 6 and 7, (| ) e) 11th memory, b.yuk 8 amplifiers. amplifier1 9, generator K) linear measurement of common world, block 11 adders, sum i4 j) i) i 12, block 13 registers, threshold selector 14. e.k-meit 15 cpaBiieni, source I) threshold nanron, n p01ch) B1) 1Y unit 17, threshold selector 18, element alee 19 comparison, source 20 poro | O 5th na11 () marriage. block 21 ister. pe1T-1. 22. black 23 nor | | -w) C, nanotechnologies, block 21 regnstro.v, reshstry 22, block 23 unrav.cheni by issue of information, corre.t that) s 24, b.yuk 25 onderecheniya maximum, decoder 26, block 27 keys, keys 28. adder 29, norgov1) 1st selector 30, .mini 31: 1delays, keys 32 and 22 formate; 1ь.: 1sov 34, registr) 35 shift, threshold (bit ii (). block 37 solution quality bumpers, multiply PL 38, eummator 39, -Ltement 40 AND, binary counter 41, key 42, 43, registers 44. When converted into a triggering siga.t of adder 29 noporoiioro values. B1 (workable) in i | 10 ov selector 30, at the exit Soonly, it is a driving signal S1L1a.1, but which with nomoi). PIC 26: Determining the maximum signal from block 21 to read the device reads the first signal code combination. In the proposed device, the combination of 21 of 1) counts1) 1 to.chko in C.chuchas (with the same limitations), when the output sigpa.b.klo 37 b.chshe and. w is equal to the given value. With JTOM, the decision is made no longer by one (JJ (as in the well-known “KIT”)) of the binary Ko; ioBoii combination ;. and in combination, which gives rise to an increase in the credibility of irishmay iifomaiii (and, moreover, the decision is made with iioMonibio on the whole gradient dexchtion procedure). It is obvious that, as in the well-known h-triple, the algorithms of fuzzion and the devices available have the greater advantages, the longer the codes. isolimu1l1e d.t formirova 1i and compo n g signal; 1ov with redundancy. Adaptive system1) pa6cjTaeT way in a single way. To the input of the aa.trade demodule} G1O K 1 comes a complex connection of s1T1a.t. On the output of the analog decmodulator 1, there appears (for example, Jos. Consumer in time) a scoop of analogs 1) 1x signals corresponding to the input elements of 1). Each of the analogs1) 1Y is fed to the input of the threshold ee.ieKTopa 2, namely to the input of the comparison element 3, to the other input of which the threshold voltage from the source 4 of the threshold signal is received (the value of this nanometer is set manually as in the known device). The magnitude of the yurog voltage is determined by the ratio of the signal, the noise in the channel, now, 11 parameters for the beating code, and the method for processing the elementary signals in the analog demodulator 1. In the element of comparison 3, the comparison of the input signals. If the value of the input (JGo ana; 1nogo si1l1 la is less than the value of iorog Hai- pn / i uHHH, at the output of elec1g; c) the signal “o, in contrast | 1 st p.1chue - signal ,; "1, determined by H (j value of the signal-to-noise ratio, parameters of the redundant code and reception method. G1;) 1 example, its voltage amplitude may be equal to N. It will respond to the undistorted single signal, 1y (this is considered to be the length; 1NoT1- (T c-C o | nyoNiee signal - I1um not ime 5: e s. | -De C e.tit.neet e: 1 elementary canal, 11O1Ч; siglla). Thus, m, afia, i oi sy1 iia.i is converted to the DEAR EIC. In the iare; ie 5 calculation from the high-speed analogue of the halogen cHiTia.ia, the deduction of the binary signal is computed. As a result, in the decoder 26 later the next one is recorded. 1 () va com.mbiia11p. correspondence; PI1I posi.mv (;, 11L1omu jeiiieiMK) 1 each anaergic route CHifia.iy. Decoder after executing the corresponding operations |) Adyi in regieter 22 ziisyvaye -; and) cotton.) a binary time) is a single code code that is closest to a binary and one character. In bkk 13 | 1gierov, the knowledge of X 1a1 is also known; it’s this; 1.1 "and chg; and the code combination .IN. In b, 1 7 6y (.j) epiioii and aa.m., we are not enough to coiiOKx for the anohyugic icHHiViX with a vyhchcha vychcha at11 o.ijKu / erg1 ciiina.iij paralla.chno podjugs 1P on | in the initial state of the keys 28 and on the inputs of a multitude of the sum of the math 29, in whom) computed.) t of the absolute block of the large block 7 (weekend and in / 1 C with sweating al yny d, ge.CH .notes | selector signal liiiiie of the magnitude of the threshold; .. h ;; lr:;: vak) your keys b.moke 27 sec.chector 30 do not turn off this signal according to; ei1 from block 23 i; i (4 equal to 1 signal, device output stored in liCM pn Here is the code combination (and its information part). If the input signal of the selector 30 turns out to be less than the threshold voltage, the signal from the output of the selector 30 is turned off. When it is, it is also removed from the input blocks 23 and 27, as a result of which the operation of the block 23 is the same as in the prior device. The keys 28 of the block 27 are opened and from block 7 the signals are also fed to the amplifiers 9. However, the output signal of the threshold selector 30 is fed to the control inputs of the block -27 keys and information control unit 23 through the delay line 31 and the open source key 32. Therefore, in addition to the described one (i.e. to the case when the key 32 is open), consider the situation when the key 32 is closed. The first enabled binary code combination from the output of the decoder 26, through the open key in the initial state, is also sequentially written to the binary shift register 35. After filling all the memory cells of register 35 at the output of element 40 I, a signal is generated, which is fed to the counting input of the binary counter 41 and to the information input of the key 42 (opened in its initial state). The public key pass, this signal changes the state of the trigger 43. (its initial state is one) to zero and is applied to the read signal in blocks 6, 35. The output signal of the trigger 43 closes the keys 42 and 33. The trigger 43 returns to the initial state (and, consequently, the keys 42 and 33 of the overflow pulse of the counter 41 (it appears after the decoder processes the nth binary combination.) The read signal generated in the pulse driver 34 synchronously reads from register 35 and 6 to the inputs of the multiplier 39, respectively first permissive binary code combination and analog composite signal with redundancy. The multiplication results are accumulated in adder 39. Upon completion of processing the input composite signals, the signal that is compared in the selector 36 with the threshold signal is output at the output of the form block 37. If the output signal of the block 37 is less than the threshold , at the output of the selector 36, a control signal is formed, closing the key 32. Otherwise, the key 32 remains in the initial (open) state. After the signals from the block 7 are applied in parallel to the amplifiers 9, a generator 10 of the linear-varying voltage is started and the gain of the amplifiers 9 increases (the initial gain factor is 1). The output signals of the amplifiers 9 are fed to the comparison elements 15, to the other inputs of which the source 16 of the threshold voltage is connected. As soon as in any comparison element 15 the output signal of the amplifier exceeds the threshold voltage, the threshold unit 17 is triggered and the linearly varying voltage generator 10 is turned off. The amplified signals from the outputs of the amplifiers 9 are fed to the inputs of the corresponding single-digit adders 12, where they are summed up with the values of the signals arriving at the other inputs of the adders 12 from the memory cells of the block 13 of registers. The resulting signals are then converted into binary signals by means of comparison elements 19 and threshold voltage source 20, and then parallel to decoder 26. The resolving binary code pattern closest to that obtained by the decoder 26 is written to register 22, shifting the first combination to register 222 Thereafter, the generator 10 of the linearly alternating voltage is again started, carried out — the operations described above, and the next permitted binary combination is written to the register 22, and previously toboggan combination perepisyvayuts registers 222 and 22, and so on until all are filled claim registers. Next, the maximum signal determination unit 25 reads from the registers 22 the combination (with regeneration) into the correlators 24, to the other inputs of which a combination of analog values is fed from the block 6 of the buffer memory. The magnitudes of the output signals of the correlators 24 correspond to the correlation coefficients of the corresponding combinations. These signals enter the maximal signal determination unit 25, in which the maximum of them is determined, and the corresponding binary code combination from the block 21 is read into the output of the device. Further, all the memory elements are cleared and the device is ready for processing the next signal. The proposed device has higher technical and economic indicators in comparison with the known device. The technical advantage of the invention in comparison with the basic object is that in the proposed device, the decision on the first allowed code combination is taken only in the case when the degree of similarity of this combination to the input signal with redundancy is not less than the specified one. The positive effect of the invention, as compared with the basic object-object, is to increase the reliability of information processing by more accurately accepting the software of the first allowed binary code combination. An approximate gain based on the reliability of the decision can be estimated as .1: CPC1-P) - jyur 1. i cl

in the case when n - 1 () 2; 5, 1, P -., Pnr - -2 10,; 1 CONFIRMATION | -РЫ11

EqualArD - 10

Thus, iipe / waracMoe device 10

in possesses higher technical and economic || (Ms. I mi io compared with lime I, IM device.

2

five

P

Claims (2)

1. ADAPTIVE DEVICE FOR PROCESSING EXCESS INFORMATION, containing a receiver, the input of which is connected to the input of the device, the output of the receiver is connected to the first inputs of the subtractor, the first threshold selector and the first memory block, the output of the first threshold selector is connected to the input of the first register block, the first input of the decoder and the second input of the subtractor, the output of the subtractor is connected to the input of the second memory block, the outputs of which are connected respectively to the first inputs of the first keys and simultaneously with the outputs of the first adder, the output of the first adder is connected to the input of the second threshold selector, the outputs of the first keys are connected respectively to the first inputs of the amplifiers, the first outputs of which are connected respectively to the first inputs of the third threshold selector, the output of which through the generator is connected to the second inputs of the amplifiers, the second outputs of the amplifiers are connected respectively to the first inputs second adders, the second inputs of which are connected respectively to the outputs of the first block of registers, the outputs of the second adders are connected respectively to ne the ditch inputs of the fourth threshold selector. the outputs of which are connected respectively to the second inputs of the decoder, the output of the decoder is connected to the first input of the second block of registers, the first output of which is connected to the output of the device, the output of the first memory block is connected to the first inputs of the correlators, the second inputs of which are connected respectively to the second outputs of the second block of registers, the outputs of the correlators are connected respectively to the first inputs of the unit for determining the maximum signal, the outputs of which are connected respectively to the second inputs of the second block of registers, ex characterized in that, in order to increase the reliability of information processing, a delay line, a second and third key, a pulse shaper, a register, a fifth threshold selector, a multiplier and a third adder are introduced into it, the output of the first threshold selector is connected through the delay line to the first input of the second key , the output of which is connected to the second inputs of the first keys and the maximum signal determination unit, the output of the first memory unit is connected to the first input of the third adder, the output of which through series-connected multiplies the fir tree and the fifth threshold selector are connected to the second input of the second key, the decoder output is connected to the first input of the third key, the output of which is connected to the first input of the register, the first output of the register is connected to the second input of the third adder. the second outputs of the register are connected respectively to the inputs of the pulse shaper, the first output of which is connected to the second input of the third key, the second output is connected to the second inputs of the register and the first memory block. 2. The device according to π. 1, characterized in that the pulse shaper contains an element And, a counter, a key and a trigger, the inputs of the element And are connected to the inputs of the pulse shaper, the output of the element And is connected to the first inputs of the key and through the counter trigger, the output of the trigger is connected to the second input of the key and the first output of the pulse shaper, the key output is connected to the second input of the trigger and the second output of the pulse shaper.