SU1193713A1 - Device for reception and processing of redundant signals - Google Patents

Abstract

A DEVICE FOR RECEIVING AND PROCESSING EXCESS SIGNALS containing a receiver whose input is an input of the device, the receiver output is connected to the input of the first threshold unit and the first inputs of the reader and the first memory block, the output of which is connected to the input of the first register block, the second input of the reader and the first the input of the decoder, the output of which is connected to the first input of the second block of registers and the first input of the first key, the output of which is connected to the first input of the register, the first output of which is connected to the first input of the block When assessing the quality of the decision, the output of which is connected through the second threshold unit to the first input of the second key, the second outputs of the register are connected to the corresponding inputs of the pulse generator, the first output of which is connected to the second input of the first key, the second output to the second inputs of the register and the first memory block whose output is connected to the first input of the control unit and the second input of the decision quality evaluation unit, the outputs and the second inputs of the control unit are connected respectively to the second inputs and the first outputs of the second a register block, the second output of which is an output of the device, the output of the subtractor is connected to the input of the second memory block, the outputs of which are connected respectively to the first inputs of the key block and the inputs of the adder, the output of which is connected via serially connected third threshold block and the first delay element to the second input the second key, the output of which is connected to the third input of the control unit and the second input of the key unit, the outputs of which are connected to the corresponding first inputs of the amplifier unit, the outputs and The input of which is connected respectively to the inputs and the first output of the fourth threshold unit, characterized in that, in order to increase the device noise immunity, an AND element, a second delay element (L ki, inverters and discriminators, each of which is made on a trigger, the key and the delay element, the trigger output is connected to the first key input, the output of which is connected through the delay element to the first trigger input, the outputs of the first register block are connected to the first inputs of the corresponding inverters, the output The inverters are connected to the corresponding inputs of the decoder, the second outputs of the fourth threshold block are connected to the corresponding in, the And element moves and the second inputs of the keys of the corresponding discriminators, the outputs of the discriminator keys are connected to the second inputs of the corresponding inverters, the output of the And element is connected through the second element delays with the third input of the amplifier unit and the second inputs of triggers of discriminators.

Description

The invention relates to telecommunications and can be used in receiving devices of information transmission systems using redundant high power codes.

The aim of the invention is to improve the noise immunity of receiving redundant signals transmitted over high quality channels.

The drawing shows a block diagram of the device.

The device for receiving and processing redundant signals contains a receiver 1 (analog demodulator), a threshold unit 2 consisting of a comparison element 3 and a source 4 of a threshold voltage, a subtractor 5, a block 6 and 7 of the buffer memory, an amplifier block 8, state Nigi from amplifiers 9 with adjustable gain and generator 10 linearly varying voltage, block 1 1 discriminators, consisting of discriminators 12, made on keys 13, triggers 14 and delay elements 5, Yurog block 16, consisting of element OR 17 , 18 elements of comparison and a voltage source 19 nopoiOBoro, a register block 20, a register block 21 consisting of registers 22, an information control control block 23 consisting of correlators 24 and a maximum signal detector 25, a decoder 26, a key block 27 consisting of keys 28, adder 29, threshold unit 30, delay element 31, keys 32 and 33, pulse generator 34 (logical unit), shift register 35, threshold unit 36, decision quality evaluation unit 37 consisting of adder 38 and multiplier 39, unit 40 control inverters consisting of controllable inventories41, performed on the key 42 and 43, element 44 and element 45, delay element 46 and element 47.

The device works in the following way.

To the input of the analog demodulator 1, a complex redundant one arrives. At the output of the analog demodulator 1, a set of analog signals appears corresponding to the elements of the input signal. Each analog signal is fed to the input of the reference element 3, to the other input of which the threshold voltage is supplied from the source 4 of the threshold voltage. If the value of the input analog signal is less than the threshold voltage, then the output of the comparison element 3 is the signal "O, otherwise the signal" 1. Thus, the analog signal is converted to a binary signal.

In subtractor 5, the magnitude of the binary signal is subtracted from the value of the analog signal. In decade 26, a binary code combination is sequentially recorded corresponding to the symbolical rough decision on the input signal. Decoder

26 writes to the register 22i a binary allowed codeword closest to the binary character. This binary code combination is also recorded in register block 20. In the buffer block 7, a set of analog signals generated in the subtractor 5 is recorded and stored.

From block 7, these signals are in parallel fed to the information inputs of the closed in the initial position keys 28 and to the inputs of the multi-input adder 29, in which the sum of the absolute values of the output signals of block 7 is calculated.

The output signal of the adder 29 is applied to the input of the threshold unit 30, where it is compared with the threshold voltage value. If the input signal of block 30 is equal to or larger than the threshold voltage, then the closing key 28 of block 27 does not turn off the output signal of block 30, and if this signal is present, a control signal is received from block 23 to block 21 to read the device output the permitted code combination (or its information part) stored in it. If the input signal of block 30 is less than the threshold voltage, the prohibition signal from the output of block 30 is turned off. At the same time, it is removed from the inputs of the unit 23 and 27, as a result of which the keys 28 of the unit 27 are opened and from the unit 7 the signals are also fed to the amplifiers 9 of the unit 8.

The output signal of the threshold unit 30 is supplied to the control inputs of the key unit 28 and the output control unit 23

information through the delay element 31 and the open source key 32. In addition to the above (i.e., the case when the key 32 is open), consider the case when the key 32 is closed. The first binary code combination from the output of the decoder 26 through the open key in the initial state of the key 33 is sequentially written into the binary shift register 35. After filling all the memory cells of register 35 at the output of logical block 34, which is connected to block 6 and register 35, a read signal is generated. Synchronously, from block 6 and register 35 to outputs of multiplier 39, the first allowed code combination and analog composite signal with

redundancy. The results of the multiplication are accumulated in adder 38. Upon completion of processing the input composite signals, a signal is generated at the output of block 37, which is compared in block 36 with a threshold signal. If the output signal

block 37 is less than the threshold, then at the output of block 36, a control signal is formed, closing the key 32. Otherwise, the key 32 is open.

After the signals from the block 7 are fed in parallel to the amplifiers 9, the generator 10 is started to linearly vary the voltage 10 and the gain of the amplifiers 9 increases (its initial value is 1). The output signals of the amplifiers 9 are fed to the comparison elements 18, to the other inputs of which the source 19 of the threshold voltage is connected. As soon as in some comparison element 18 the output signal of amplifier 9 exceeds the threshold voltage, the element OR 17 is triggered and the generator 10 "stops, i.e. the increase in the output voltage stops, a binary combination of one is formed at the outputs of the comparison element 18 weight. A single character is in the order of which the number is determined by the least reliable analog signal.

From the outputs of block 16, a parallel code combination is fed to the inputs of block 11 of discriminators. Each binary symbol enters the input of the corresponding discriminator 12. Consider the passage through the discriminator 12 of a single signal.

This signal passes through the open source key 13 at the discriminator output, and also through the delay element 15 enters the trigger input 14, which changes its state to the opposite, as a result of which the key 13 closes and the subsequent signals from the discriminator input 12 its output does not go through (until the trigger is reset).

The zero input signal of the discriminator 12 does not change the state of the key 13.

Thus, at the output of the discriminator block 1 1, a binary code unit of unit weight is generated.

The output combination of the discriminator block 1 1 is fed to the inputs of the block 40 of the controlled inverters, to the other inputs of which from the parallel outputs of the block 20 the binary code combination enters - a character-by-character estimate of the input signal. The signals of these binary combinations are fed to controlled inverters 41 of block 40.

The binary signal from the output of the block 1 1 is fed to the control inputs of the keys 42 and 43. If this binary signal is zero, then the key 42 is open, and the key 43 is closed. If the signal is single, then key 42 is closed for the duration of the signal, and key 43 is opened. At a zero signal, the information signals from the corresponding output of block 20 through key 42 and the element OR 45 are passed to the output of block 40 without change. With a single signal, information signals are passed through the corresponding key 43, inverted with. using the item NOT

44 and through the element OR 45 are passed to the output of the block 40.

Thus, the output combination of block 40 differs from the combination of block 13 in that bit whose number matches the number of a single character in the output combination of block 11. The output combination of block 40 in parallel code enters the decoder 26.

Decorated decoder 26 allowed

0, the binary code combination is written to register 22 |, the shift of the first allowed combination to register 22o.

After that, the generator 10 of block 8 is again started, as a result of which its output voltage continues to flow. The second comparison element triggers, causing the generator 10 to once again stop. At the output of block 16, a binary code combination with two unit symbols is generated. She is served on

Q inputs block 1 1 discriminators. The first unit to the output of the corresponding discriminator 12 does not pass, since the key 13 is driven. The second unit passes to the output of its discriminator 12, the key 13 of this discriminator is closed. On

5, a binary code unit of unit weight is generated by the output of block 1-1. It has all the characters of the binary combination of block 20. As a result, a binary code combination is formed at the output of block 40, which differs from the combination of block 20 by one bit whose number matches the number of the next least reliable symbol of the complex analog signal at the output of demodulator 1.

5 Similarly, the inversion of all symbols of a binary pattern of a buc 20 is performed in the order determined by the reliability of the analog signals.

The output combinations of block 40 with decoder 26 are converted into permitted combinations, which are written to the registers of block 21.

When all the characters of the output combination of block 16 are single, a signal appears at the output of AND 47. This signal passes through the delay element 46 and sets the generator 10 to the initial state, at which the gain factors of the amplifiers 9 are equal to one, set-. triggers 14 discriminators 12 into a state in which the keys 13 are open.

0 Next, the maximum signal detector 25 reads from the registers 22 allowed combinations into correlators 24, to the other inputs of which a combination of analog values is fed from block 6 of the buffer memory. The magnitudes of the output signals of the correlators 24 correspond to the correlation coefficients of the corresponding combinations. These signals enter detector 25, in which the maximum of them is determined.

The allowed combination corresponding to the maximum signal is read by the control signal from the detector 25 to the corresponding register 22. Then all the memory elements are reset and the device is ready for operation — processing the next redundant signal.

The proposed device has a higher technical and economic indicators compared with the known device.

The technical advantage of the proposed device is that only single weight vectors are formed in it and with their help the combination of a rough character-by-character estimate of the excess signal is corrected.

The positive effect that can be achieved as a result of using the invention is to increase the noise immunity of receiving redundant signals in high quality channels due to the fact that in such channels one-off errors of unit weight are the most likely errors.

Let us calculate the approximate gain of the probability of correct reception, which determines the noise immunity of the reception of redundant signals.

The known device corrects errors of different multiplicity, therefore the probability of correct reception of this device is proportional to the sum of the probabilities of the occurrence of the error vector of the specified multiplicities.

-R- (

Fnpaii "jp (l-p) -f p | p (1-pp-

where p is the probability of elementary signal distortion;

H is the number of elementary signals in the composite redundant signal. The probability of correct reception of the proposed device is proportional to the sum of the probabilities of the occurrence of one-time error vectors.

P (i-pf-4 ... + P (i-pf

pHos

g right

 Hp (1-p) - Exclude common members and find the relationship

R

(n-1) P (1-rG;

  Glrav

p () + p3 (... + p “.

rlzv prlv

Denote

A.-1-p

then

y (H-1) (a-1)

O -f-ranp

15

aa -1

Let P 1 10 then

--i-JO

/

1 - 1-10

20

(n-1) 1 lo

Let, 5, then

.one

25 1-0.5

Y "(H-1).

Let, 8, then

thirty

a 0-s .4 1 -0.8

H

Tg

Thus, if the original communication channel is of good quality, i.e. , 5, then the noise immunity of the proposed device is higher than the noise immunity of the known device. In the channels of low quality P 0.5, it is preferable to use a known device. The advantages of the proposed device are the better, the longer the code used (the greater the value of H) and the higher the quality of the communication channel (the smaller the value of P). ... U 28 H. r-F J3 / / 1 / J Y 0 /

Claims (1)

A device for receiving and processing redundant signals, containing a receiver, the input of which is the input of the device, the output of the receiver is connected to the input of the first threshold block and the first inputs of the subtractor and the first memory block, the output of which is connected to the input of the first register block, the second input of the subtractor and the first input of the decoder whose output is connected to the first input of the second block of registers and the first input of the first key, the output of which is connected to the first input of the register, the first output of which is connected to the first input of the open the quality of the solution, the output of which is connected through the second threshold block to the first input of the second key, the second outputs of the register are connected to the corresponding inputs of the pulse shaper, the first output of which is connected to the second input of the first key, the second output to the second inputs of the register and the first memory block, output which is connected to the first input of the control unit and the second input of the decision quality assessment unit, the outputs and second inputs of the control unit are connected respectively to the second inputs and first outputs of the second register block ditch, the second output of which is the output of the device, the output of the subtractor is connected to the input of the second memory block, the outputs of which are connected respectively to the first inputs of the key block and the inputs of the adder, the output of which is connected through a series of connected third threshold block and the first delay element to the second input of the second key, the output of which is connected to the third input of the control unit and the second input of the key block, the outputs of which are connected to the corresponding first inputs of the amplifier block, the outputs and the second input of which connected respectively to the inputs and the first output of the fourth threshold block, characterized in that, in order to increase the noise immunity of the device, an And element, a second delay element, inverters and discriminators, each of which is executed on a trigger, a key and a delay element, are introduced into it <g the trigger output is connected to the first input of the key, the output of which is connected through the delay element to the first input of the trigger, the outputs of the first block of registers are connected to the first inputs of the corresponding inverters, the outputs of the inverters are connected to the corresponding second inputs of the decoder, the second outputs of the fourth threshold block are connected to the corresponding inputs of the element And the second inputs of the keys of the respective discriminators, the outputs of the keys of the discriminators are connected to the second inputs of the corresponding inverters, the output of the element And is connected through the second delay element to the third input of the amplifier block and the second inputs of the triggers discriminators. SU, 1193713