SU1403380A2 - Decoder - Google Patents

Abstract

The invention relates to the field of telecommunications and m. Used in data transmission systems for error protection. The invention is improved noise immunity. The decoding device contains a quantizer 4, memory blocks 5, 8, multiplier 6, keys 7, 9, r-10 code words, comparison block 11, code word register 12. A two-threshold block (DPB) 1, an inverter 2 and an element 3 are entered in the device in series. At the output of the BPG 1, when processing each element of the signal vector, there is an erase signal. This signal is fed to the input of inverter 2 and then, in an inverted form, is applied to element 3. As a result, the unreliable characters are received completely if their amplitude does not exceed threshold 1, or partially, if the threshold is not exceeded only in part of the character are eliminated (: erased) and replaced with zeros. Thus, the received signal with erased characters of the bit enters the quantizer 4 and from its output to the input of the memory block 5. 1 Il. e ss (L

Description

N)

: The invention relates to telecommunications and can be used in data transmission systems for error protection.

The aim of the invention is to improve noise immunity.

The drawing shows a structural electrical circuit of a decoding device,

The decoding device contains a two-threshold block 1, an inverter 2, an AND 3 element, a quantizer 4, a block of 5, a multiplier 6, a first key 7, a second memory block 8, a second key 9, a code word generator 10, a comparison block 11, register 12 code words.

The decoder circuit works as follows.

At the beginning of operation, the number of tp + 1 is recorded in multiplication unit 6, where m is the number of quantization levels of each character of the received (input) signal, the number is the number of characters, and the second memory unit 8 records the O number

The received n-element vector of the signal corresponding to the n-bit word of the group code is successively fed to the element 3 and simultaneously to the two-threshold block 1. At the output of the two-threshold block 1, when processing each element (symbol) of the signal vector, a signal appears erase if the amplitude of the symbol, l,, j 1, n, where .1 is the threshold value, is equal to the value of the first quantization level (the number of levels in the quantizer 4 is equal to m).

The erase signal is fed to the input of the inverter 2 and then in the inverted form is fed to the second input of the element 3. As a result, unreliable characters are received completely, if their amplitude does not exceed the threshold 1, or partially, if the threshold 1 is not exceeded in part of the symbol, are eliminated (erased) and replaced with zeros. Thus, the received signal with erased symbols is transferred to the quantizer 4 and, from its output, to the input of the memory block 5. After receiving and quantizing at the level of all n pulses (symbols), the corresponding values are recorded in the memory block 5.

At the same time, in the generator 10 code layers, a bitwise

summation of the generating vectors of the code used with a sequential enumeration of all the combinations, with each combination of symbols 1 and O corresponds to its own combination of generating vectors.

The code vector written in generator 10, bitwise, comes from its outputs separately for values of bits 1 and 0, and the outputs of memory block 5 receives the digital value of the first bits of the received vector separately

m m for a value of 5 and.

After all n bits of the generated and received (where unreliable symbols are erased) vectors in TC at the output of the generator 10 and memory block 5, in the multiplication unit 6 a certain number is recorded that characterizes the measure of similarity of the compared vectors. lies between the numbers 1 and 1, If the value of the number is less than + 1, then it goes to the input of the comparison block 11 and since the initial value in the second memory block B is O, then the incoming value of the number is greater than HyjiH. In this case, the comparison unit with 11 (output) signals opens the first and second keys 7 and 9.

Through the first key 7, a new value of the number is fed to the input of the second memory block 8, and the corresponding code vector is written through the second key 9 to the register 12.

In the following, generator 10 alternately generates all code words that are multiplied scalarly by a received word with erased symbols stored in memory block 5. The result of the multiplication is fed to the input of the compare block 11, the second input of which receives the value of the number from the second memory block 8.

At the output of comparison block 11, a signal appears only if the number received at its input is greater than the number found in the second memory block 8. As a result, the first key and the second keys 7 and 9 are opened, through which the new values are recorded. measures of correspondence to the second memory block 8 and the new value of the code vector with corrected unreliable characters to the register 12. In each case 1403380

The time element in register 12 is stored by the fact that, in order to increase the noise-number, which has the greatest stability, a sequence of a received n-element vector connected two-threshold block, a pv signal. an inverter and an I element, whose output

 connected to the input of the quantizer.

Claims (1)

The claims of the second input element And connected to input two-threshold unit, and Decoder on auth. St. the input of the two-threshold block is # 590857, characterized by the Q input of the decoder.