SU1672577A1 - Receiving device for system with linear code multiplex operation - Google Patents

Abstract

The invention relates to telecommunications and can be used to seal communication lines of any type. The purpose of the invention is to improve the accuracy of signal separation and increase noise immunity. The receiver for the system with linear code channel multiplexing comprises a receiver 1, a compression and repetition block 2, a noise compensation compensation block 6, a channel selector 7, N decoders 9, N switches 8, a control block 4 and a sync block 3. The goal is achieved by introducing a comparison block 5 where the required number of mutual interference compensation cycles is determined. The device according to claim 2 is characterized by performing a block 2 for compressing and repeating a signal. The device according to claim 3 is characterized by the execution of the control unit 4. 2 hp f-ly, 1 ill.

Description

The invention relates to telecommunications and can be used to seal communication lines of any type.

The purpose of the invention is to improve the accuracy of signal separation and increase noise immunity.

The drawing shows a structural electrical circuit of the receiving device for a system with a linear code channel multiplexing.

The receiver for the system with linear code channel multiplexing comprises a receiver 1, a signal compression and repetition unit 2, a sync block 3, a control unit 4, a comparison unit 5, an interference compensation block 6, a channel selector 7, N switches 8, N decoders 9.

The signal compression and repetition unit 2 contains an analog-to-digital converter (ADC) 2., a buffer storage device 2l, a signal repetition unit 2.J, a digital-analogue converter 2.

The control unit 4 contains the first 4 and second 4.J. counters, element AND 4-j, trigger 4q., element OR 4, inverter 4g, unit 4g of frequency multiplication.

Device (works as follows.

An A / D converter 2 performs an analog-to-digital conversion of the input signal Urp (t) with a frequency of its elements fT. Digital samples of the elements of the signal Urp (t) are stored in the first memory cell of the buffer accumulator 22. After recording all

3

J

SPE SP

N i

In the case of a group signal of duration T, it is copied to the second memory cell of the buffer accumulator 2 by the signal from sync block 3. At this moment, all the information is shifted towards the higher numbers of the memory cells of the buffer accumulator 2. After the processing of the next implementation of the signal Urp (t) is completed in the block

The ke 6 and the channel selector 7 from the buffer accumulator signal Ugyj from the control unit 4 rewrites the subsequent implementation into the signal repetition unit 2, from where it is digitally elementalized at a speed K times the frequency F T of the input signal Urp ( t). Then it is converted into an analogous form in NAL 2 and is fed to the input of block 6. Next, the estimated-correlation-compensation processing of the received repeats of the group signal is performed. At the first stage, a first correlation is performed with the existing copies of the receiving X reference points (t) in the channel selector 7, which results in estimates at the output of the channel selector 7 (Ј | (Xfj). The noise compensation unit 6 is idling at the first stage, since its second information inputs are disconnected from the outputs of the channel selector 7 by switches 8. They are at this moment connected to the inputs of decoders 9 and give them decisions about receiving the previous implementation of the groups ovogo signal. In Single schom subsequent process step by repeating a comparison produ zvodit- oify solutions and Oin. ,, I obtained respectively in the processing and the q-th (q-1) th group signal repeats in the comparing unit 5.

If the solutions for at least one reception channel do not coincide, then they are made on the basis of solutions (Ј, generation of compensating signals for each reception channel, their compensation in the (ql) -M repetition of the signal U (-n (t) B block 6 and the mutual correlation processing in the channel selector 7.

The greater the number of channels that have $ 6, the greater the proportion of the total mutual interference (SVP) will be compensated. With # | (Y;, jN will occur complete compensation of mutual interference (COI). This fact can be detected

AL

live in case xl | txo.t, 1 1, n. At the same time, the output values of the signals with increasing q will remain constant, which indicates the safety of further compensation of mutual interference. If equality is performed in comparison block 5, is 0 (a., Ji 1 | N), it issues a signal to control unit 4 to start processing the next implementation of the signal Urp (t), which is copied from buffer store 2 to block 2l. Thus, the comparison block 5 determines the required number of cycles of the FEC q.

If q turns out to be greater than K,

i.e. compensation time T,

to MP

 (q +

+ 1) Tpo - (- (q + 1) T / K will become longer than the duration of the input signal Ufp (t), then the subsequent implementation of Urp (t) is stored in buffer store 2.

The device operation rhythm is set by frequency multiplier 4. Since repetition processing Urn (t) must be performed K times with a higher speed, then in block 4 there are two frequency multipliers with a multiplication factor K: one to multiply the clock frequency following the signal elements Urp (e), and the other is the frequency f following information symbols. These frequencies are provided to block 2j, interference cancellation unit 6, channel selector 7 and comparison unit 5.

The overall control of the entire device is carried out using the control unit 4. Its main elements are the first 4j and the second 4 counters. The second counter 4 stores the address of the implementation of the group signal, which follows the implementation, which is stored in block 2, j whose repetitions are being processed at a given time. This address in the form of a binary code is fed to the fourth input of the buffer accumulator 2. In addition, the second counter 4- outputs a control signal and

sch

in the case of zero state

counter, when the buffer drive 2Ј is empty, all implementations of the signal Urp (t) are already processed. The signal UC41 enters the frequency multiplier 4y, thereby stopping the output

frequency Кt K

and f and. To the Urp (t) signal repetition processing blocks. In case of filling all the memory cells of the buffer storage 2% of the second account

Chip 4 generates an overflow signal UC4a, which stops processing the next repetition of the signal being processed at this point in time and switches the device to processing the next realization of the group signal, thereby freeing the last memory cell in the buffer memory 2j. The state of the counter changes under the influence of two counting inputs. The first input receives pulses from the first output of the synchro-block 3 with the frequency i and they increase the state of the second counter 4 by one. The same pulses shift the stored signal implementations in the buffer storage by 2% by one cell by increasing their numbers. The state of the second counter 42 is reduced by one under the influence of the signal from the output of the element OR b.g when the device switches to processing the next implementation Ur0 (t). j

The first counter 4. calculates the numbers of repetitions from the current implementation of the signal Urp (t) that is being processed at a given time and gives the following control signals. When counting the first pulse received from the second output of the frequency multiplying block 4, with the following frequency fM K, it outputs the signal UC4, which provides parallel reading of the next implementation Urp (t) to the signal repeater unit 23. Signal Uc45 When the counter switches to state 2 produces a inhibit signal through the inverter 4g to the AND 4- element, prohibiting the passage of the signal about the result of comparing the solutions after processing the first repeat Urp (t). This does not allow, prematurely before the start of the first phase of the FOC, to stop processing the implementation of the group signal if K | j C o, The same signal switches the trigger. to the zero state, thereby ensuring the termination of the issuance of decisions about the results of processing the previous implementation of the signal Ur "(t) and connecting the outputs of the channel selector to the first inputs of block 5 and to the second inputs of block 6 compensation. This ensures that the device switches to compensation processing mode. The ISC signal is issued when the first counter 4 is set to the state corresponding to the maximum

Q 5 5

0 o 5 0

five

five

.number of stages Q, OP compensation.

Thus, the termination of processing the next implementation of the signal Urp (t)

 and the transition to subsequent processing takes place in the device when one of the three conditions is satisfied: comparing solutions ci and tfa-ii of the buffer accumulator 2 2. overflow and at q Qiop if at least one of these conditions is fulfilled, the OR 4 5 element gives a logical unit that switches trigger into one state, zeroing the first counter 4 and subtracting the unit in the second counter L $. The trigger 4 in state 1 by means of the switches 8 connects the inputs of the decoders 9 to the outputs of the selector 7 channels.

Claims (3)

1. Receiver for a system with linear code channel multiplexing, containing a receiver connected in series, a signal compression and repetition unit, an interference compensation unit and a channel selector, N outputs each of which are connected to the first inputs of N switches, the first output of which is connected to the first input of the corresponding decoder, the second inputs of which are combined, the second output of each of the N switches is connected to one of the N second inputs of the interference compensation unit, the third input of which is connected to the second input of the selector The first output of the control unit, the second output of which is connected to the combined second inputs of N switches, and the sync block whose input is connected to the output of the receiver, and the first output of the sync block is connected to the first input of the control unit and the second input of the signal By the fact that, in order to improve the accuracy of separation of the group signal and increase the noise immunity, a comparison unit was inserted into it, the N first inputs of which are connected to the second output of the corresponding switch About which are connected to one of the N second inputs of the comparator unit, the third input of which is connected to the fourth input4 of the interference compensation unit, the third input of the channel selector and the third output of the control unit, the second outputs of the switches are connected to the second inputs of decoders, the third and fourth inputs of the compression unit and the signal repetitions are connected respectively to the first and second outputs of the sync block, the fifth and sixth inputs of the compression and repetition unit are connected respectively to the fourth and fifth outputs of the control unit, the third input to torogo connected to the second output of the sync and the seventh and eighth inputs despreader and a repetition signal - from, respectively, the first and third output control unit. 2. The device according to claim 1, is tlicking such that the signal compression and repetition unit contains serially connected analog-digital converter, buffer storage, signal repetition unit and digital-analog converter, the output of which is determined by the output of the unit compressing and repeating the signal, the first and second inputs of the analog-to-digital converter are respectively the first and second inputs of the compression and repetition unit, the second, third, fourth and fifth inputs of the buffer accumulator are the third, fourth, fifth and the sixth inputs of the compression and repetition unit; the second and third inputs of the repetition unit; are the seventh and eighth inputs of the block of compression and repetition of the signal. 3. The device according to claim 1, which is tlicitous in that the control unit comprises a frequency multiplication unit, the first and second inputs of which are respectively the first and second inputs of the control unit, and the first and second outputs of the frequency multiplying unit are the third inputs of the control unit, as well as serially connected first counter, inverter, AND element, OR element, trigger, the output of which is the second output of the control unit, and the second counter, the first input of which is connected to the first input of the frequency multiplying unit, the second output costly connected to the first input of the first counter, the second input of which is connected to the second input of the second counter and to the output of the OR element, the first output of the second counter is connected to the third input of the frequency multiplying unit, the second output of the second counter is the fourth output of the control unit, the fifth output is the second output of the first counter, the third output of which is connected to the second input of the OR element, the third input of which is connected to the third output of the second counter, and the second input of the trigger is connected to the input of the inverter, than the second input of the control unit is a second input member I.