SU1124446A1 - Device for demodulating binary signals - Google Patents

Abstract

DEVICE FOR DEM071UL1 (AI BINARY SIGNALS containing an input signal conversion unit whose output is connected to the input of a delay line, an evaluation unit evaluating the impulse response sequentially connected to the first slmmator, second adder, discriminator, key, relay and register, characterized in that In order to simplify the device by simplifying the signal processing units, controlled multipliers, switches, adders-subtractors, a control unit and a switch are introduced into it, the output of the input signal converting unit la is connected to the input of the impulse response estimator, the outputs of which are connected to the corresponding inputs of the first adder via corresponding serially connected controlled multipliers, switches, adders-subtractors, and the second inputs of controllable multipliers and switches, respectively, with the first and second outputs of the block control, the third and fourth outputs of which are connected to one of the inputs of the switch, the other inputs of which are connected to the outputs of the register, one of the outputs of which is with the output of the device, the output of the switch is connected to the second inputs of adders-subtractors, the outputs of which are connected to their third inputs, the third input of one switch is connected to the output of the input signal conversion unit, the third inputs of the remaining switches are connected to the output of the delay line, the output of the block. control is connected to another key input.

Description

The invention relates to electrical communication and can be used j telegraphy, data transmission and in systems for the transmission of discrete messages over channels with the energy dissipation of signals over time. A device for demodulating discrete signals is known, comprising a unit for measuring the impulse response of a channel, blocks for summing signals, a discriminator connected to the integrator of the computing unit, subtractors connected to the outputs of the delay line. However, the known device is very cumbersome. The closest to the proposed technical solution is a device for demodulating binary signals, containing an input signal conversion unit, the output of which is connected to the input of the delay line, a pulse response estimator unit, a series adder, a second adder, a second adder, a minator, a key, relay and register 2J. However, the known device has a complex structure. The purpose of the invention is to simplify the device by simplifying the signal processing units. The goal is achieved by the fact that the device for demodulating binary signals, containing the conversion unit, the input signal whose output is connected to the input of the delay line, the evaluation unit of the impulse response, are connected in series the first adder, the second adder, the discriminator, the key, the relay and the register controlled multipliers, switches, adders-subtractors, a control unit and a switch are introduced, the output of the input signal converting unit is connected to the input of the impulse response estimator, outputs to which through the corresponding serially connected controllable multipliers, switches and totalizer subtractors are connected to the corresponding inputs of the first adder, the second inputs of the controlled intelligent residents and the switches are connected respectively to the first and second outputs of the control unit, the third and fourth outputs of which are connected to the same inputs of the switch, The other inputs of which are connected to the outputs of the register, one of the outputs of which is the output of the device, the output of the switch is connected to the second. the inputs of adders-subtractors, the outputs of which are connected to their third inputs, the third input of one switch are connected to the output of the input signal conversion unit. the third inputs of the other switches are connected to the outputs of the delay line, the fifth output of the control unit is connected to another key input . FIG. 1 shows a structural electrical circuit of the device in FIG. 2 is a block diagram of the control unit. The device for demodulating binary signals contains an input signal conversion unit 1, an impulse response estimator 2, a delay line 3, controllable multipliers 4, switches 5, summation readers 6, adders 7 and 8, discriminator 9, key 10, relay 11, register 12 , control unit 13, switch 14. The device operates as follows. The signal from the output of the communication channel is fed to the input of the input signal conversion unit 1. This unit has T outputs that are removed. h digital sequences of samples of the input signal, taken with a period equal to one clock interval T and shifted each other relative to each other for a time interval, i.e. unit 1 combines the functions of a sampler and an analog-to-digital converter. The signals from the P outputs of block 1 are fed to the inputs L of the input signal processing branches, each of which contains a block 2 estimating the impulse response of the communication channel, a delay line 3, controlled multipliers 4, switches 5, adders-subtractors 6, an adder 7. Each From the processing branches, these signals are fed to the input unit 2 of the evaluation of the impulse response of the communication channel to a single station and to the input line 3 of the delay. The task of block 2 for estimating the impulse response of the channel is to calculate, based on the analysis of the received signal Z (t), the counts of the response of the channel

communication for a single parcel, taken over a time interval T.

o T) i, mV, w-r ClATl,

And the formation of these quantities of the following vectors:

9m-1

91 9g About

0; ..

M + 1

9i-1 O

So 91

Oh oh

  "

n

GK-I

9m-2

about

9o QH-I

The vectors are sets of responses of the communication channel to a single parcel, shifted relative to each other by a clock interval T and bounded by an interval of 0, T MT.

At the outputs of the delay line 3 there is a set of current samples of the vector of the received signal Z (t) taken through one clock interval-T in the analysis interval iT, (i + M-1) T During the clock interval T there are four stages of signal processing. In the first stage, the switches 5 connect the inputs of adders-subtractors 6 to the outputs of the line 3 delays. The control inputs of the adders of the subtractors 6 from the output of the control unit 13 through the switch 14 receive a signal corresponding to the operation mode Addition, and at the outputs of the summatord subtractors 6, the vector Z- is formed.

In the second stage, the switches 5

 .

connect the inputs of adders-readers 6 to the inputs of control multipliers 4, which at this stage of processing work in multiplication mode by 1. At the same time, from the output of block 2, the channel impulse response to the inputs of adders-subtractors 6 through controlled multipliers 4 and switches 5 are sequentially the vectors Sd ,,, Od,,.,. G, enter, and the control inputs of the totalizers 6 from the output of register 12 through the switch 14 are consistently received the values a-,.

which are decisions taken at previous rounds with respect to the signs of the packages that preceded the demodulated one. As a result, at the outputs of adders-subtractors 6, a vector of samples of a different signal Z, Z is formed; -a,., “which corresponds to the vector of samples of the received signal, from which the deductions from all the preceding demodulated signals are subtracted.

At the third stage, from the outputs of block 2, the estimate of the impulse response of the channel to the inputs of adders-subtractors 6 is through controlled multipliers 4 (in the Multiplication by 1 mode) and switches 5 successively supplied vectors. At the same time, the control inputs of adders-subtractors 6 are output the control unit 13 through the switch 14 receives a signal corresponding to the operation mode Subtraction. As a result, the outputs of adders-subtractors 6 form a vector (set of samples) of the comparison signal L of the difference signal Z. (t) and the original signal support a - - “I - (ij - - -., - Г - f О Л с) Vector S is a collection of samples of the segment of the expected useful signal, limited by the analysis interval i, T, (L + M-1 ) Tj, from which the after effects of all the packages preceding the demodulated one are subtracted, i.e. signal), hih) t +. a; +, l- ,, corresponding to the code combination, Iv..a ,,) + tЧiиn .. At the fourth stage, the controlled scramblers 4 go into operation mode Multiplication by 2, and to the inputs of adders-subtractors 6 through control Multipliers 4 and switches 5 to a specific sequencer ;; In this case, the vectors G, G ..., C are fed to the control inputs of the sum of tori-ereaders 6 from the output of the control unit 13 through the switch 1 is fed a sequence of control signals that transfer the totalizers-subtractors 6 from the Addition state to the Subtraction state and vice versa. As a result, at the outputs of adders-subtractors 6, successively are the vectors L, which are sets of samples of the comparison signal of the strength signal Z (t) and all possible reference signals Sy (t) ... Sj corresponding to all possiblecode combinations of binary symbols a-, a; .. G (l tJ Ka ady vector ... .L ... .b, is a set of values that appear on the accumulator of subtractors subtractors 6 Size 1 , .... 1 are fed to the inputs of the adder (geometric addition schemes) 7, whereupon ito.VJ f appear alternately at the output. These values are alternately fed to one of the inputs of the sigmmator 8, to the other inputs of which similar signals from the other branches of processing. As a result of this output of the adder 8, the values L rti.r are sequentially formed, where the index g denotes the number of the processing branch. The value in characterizes the square of the distance between the segment of the difference signal Z, (t) and the corresponding segment of the reference signal S (t) in the space of received signals in the analysis interval. The values 1) q alternately arrive at the input of the discriminator (comparison and selection schemes) 9, where they are successively compared to each other, as a result of which the choice is made, the minimum value corresponding to some code combination. At the same time, the pulse from the discriminator 9 closes the key 10 and the sign the first sending of the combination A., coming from the control unit 13, via the key 10 and the relay 11 is recorded in the first trigger of the register 12 (the value a is registered). The output of the entire device for demodulation is the first output of the register 12. The operation of the proposed device is provided by the control unit 13. It generates signals that produce the following actions: transfer the controlled multipliers 4 from the Multiply by 1 mode to the Multiply by 2 mode and vice versa, connect the outputs of the switches 5 to the delay line 3 or to the controlled multipliers 4, translate the totalizers 6 in Addition and Subtraction mode connects the output of the switch 14 to the control unit 13 or to one of the outputs of the register 12. In addition, the control unit outputs a sequence of characters of the first premises of the combinations A. One of the possible variants of the control unit circuit diagram is Razhen in figure 2. The generator 15 outputs an uninterrupted sequence of pulses with a period T. Counter 16 provides a sequence of numbers. In block 17, the sequence of numbers is converted into another sequence of 11244 numbers, i.e. block 17 is a code converter. It can be implemented, for example, on diodes, on AND and OR elements. The most economical is the use of a read-only memory (ROM) code as a converter. 5 6, 8 The positive effect of using this device is that, compared with limestone, the complexity of its implementation is reduced, which is especially noticeable in digital signal processing.

, Entrance

Claims (1)

DEVICE FOR DEMODULATION. BINARY SIGNALS, comprising an input signal conversion unit, the output of which is connected to a delay line input, an impulse response evaluation evaluation unit, a first adder, a second adder, a discriminator, a key, a relay and a register, which are characterized in that, in order to simplify the device by simplifying signal processing units ^ controlled multipliers, switches, adders-subtracters, a control unit and a switch are introduced into it; moreover, the output of the input signal conversion unit is connected to the input of the evaluation unit pulse reaction, the outputs of which through the corresponding sequentially connected controlled multipliers, switches, adders, subtracters. whether connected to the corresponding inputs of the first adder, the second 'inputs of controlled multipliers and switches connected respectively to the first and second outputs of the control unit, the third and fourth output of which are connected to one of the inputs of the switch, the other inputs of which are connected to the outputs of the register, one of the outputs of which is a device, the output of the switch is connected to the second inputs of the adders-subtracters, the outputs of which are connected to their third inputs, the third input of one switch is connected to the output of the unit As the input signal is converted, the third inputs of the remaining switches are connected to the outputs of the delay line, and the fifth output of the block. control is connected to another key input.