SU1499508A1 - Arrangement for monitoring communication channel quality - Google Patents

Abstract

The invention relates to communication technology. The purpose of the invention is to improve the accuracy of control. The device contains a band-pass filter 1, an amplitude detector 2, a low-frequency filter 3, quadrants 4 and 5, integrators 6 and 7, ADC 8 and 9, a synchro shaper 10, and an interference-signal calculator 11. The input of the device receives a mixture of signal, interference, and various out-of-band noise. Filter 1 filters out-of-band noise, then detector 2 extracts the envelope of the sum of the desired signal and interference. Filter 3 clears the envelope of the high-frequency components, but skips the beats due to a phase shift between the noise and the signal. Then, the voltages are converted by quadrants 4 and 5 and averaged over the period in integrators 6 and 7. Next, the A / D converters 8 and 9 convert these voltages into digital signals, which are fed to the calculator 11, where the interference-signal ratio is determined. If the interference is less than the instrumental noise or not, then logical zeros are output to both outputs of the device. If the interference and signal are equal or their difference is less than the instrumental noise, then the device will produce logical zeroes at the first output, and a logical unit at the second output. T.V. through the second output of the device, the highest bit of the result is issued, the lower bits of which are output through the first output. 1 hp f-ly, 3 ill.

Description

31499508

The invention relates to communication technology and can be used to control the quality of communication channels with passive and organized interference, as well as with multipath propagation of signals

The purpose of the invention is to increase the accuracy of the control.

FIG. Figure 1 shows the structure of a Q-ma electrical circuit of a communication quality control device; in fig. 2 - structural electrical: interference ratio - signal; in fig. 3 - voltage diagrams, j explaining the operation of the device.

The channel quality control device contains a bandpass filter 1, an amplitude detector 2, a low-frequency filter 3, quadrants 4 and 5, inte- graters 6 and 7, analog-to-digital converters 8 and 9, a driver

10 sync signals and calculator 11 interference-signal ratio. Calculator

11 (Fig. 2) contains registers 12-16, 25 j multiplexers 17 and 18, quad 19, desiccator 20, shift register 21, block

22 square root, divider 23, control signal generator 24, triggers 25-29, element OR 30, AND element 31 and inverter 32.

The device works as follows ..

A mixture of signal, interference and various out-of-band noise is input to the device input (Fig. 1).

The bandpass filter filters out-of-band noise (we assume that the interference band is the same as that of the signal). Amplitude detector 2 highlights the envelope of the sum of the desired signal and interference. In the case of angular modulation of a signal, its envelope practically changes little. In the absence of interference, the path of communication may introduce slight and slow changes in the signal envelope. However, in the presence of interference, the total signal envelope depends on the envelopes of the useful signal and the interference and the phase difference between them. Therefore, the envelope of the total signal can take on different values from minimum to maximum, depending on the phase difference. The low-pass filter 3 clears the envelope of the high-frequency components, but skips the beats due to a phase shift between the noise and the signal. After the first square 35

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The voltage applied to it is squared. After the second quad squared, the voltage is re-squared. In integrators 6 and 7, the voltage is averaged over the period defined by the signal (Fig. 3a) from the fourth output of the driver 10, and the signal from the third output (Fig. 36) of the integrators 6 and 7 are zeroed. Analog-to-digital converters 8 and 9, using signals (fig. Sv) from shaper 10, convert the corresponding voltages into digital signals.

The task of calculator 11 is to determine the interference-signal ratio from the square of the averaged signal voltage and the interference and the same voltage to the fourth power. The control input of the calculator 11 is fed from the first output of the driver 10, a start signal (Fig. 3g), which is formed before the end of the operation of the analog-digital converters 8 and 9 and by which the calculator 11 starts a processing cycle that goes to its first and second information inputs. From the outputs of analog-to-digital converters 8 and 9, the signals arrive at the information inputs of registers 13 and 12 (Fig. 2), where they are stored on the signal from the ninth output of the driver 24 (Fig. A). From the output of the register 13, the signal enters the input of the quad 19, where it is squared.

From the first output of the quadrant, through time T1 (Fig. 3p), the signal in the inverse binary code arrives at the first information input of the multiplexer 18, which passes this signal to the second input of the adder 20 according to the signal (Fig. Ze). This signal is coded, supplied via a bus consisting of two wires, from the eighth of the shaper of the driver 24 to the control inputs of the multiplexers 17 and 18, in which, depending on the code, it connects either the first (by code a) or the second (code c), or the third (code c) input to the output, or embedding the inputs of the adder 20 (in the absence of the specified codes). From the output of the register 12, the signal arrives at the first input of the multiplexer 17, which, according to the signal (FIG. 3), passes this signal to the first input of the adder 20. From the seventh output of the driver 24 to the input

Adder 20 (transfer entry to the lower bit of adder 20) is given a signal (FIG. 3) as a 1 1 lower order, which is an amendment when presenting an additional code subtracted through an inverse code. The adder 20 Raman, you can use the acceleration scheme

the root is stored in register 15, block 22 receives at its input register the amount of the sum of the signal (Fig. G3) and during the time T5 (Fig. F) produces the extraction of the root from this value.

The result goes to the information input of the multiplexer 18, where

transfers. In the adder 20, both the signal operand (FIG. Za) from the driver

/

Yes, they are added up in time Tg (Fig. 3c) and the result is fed to the information input of the shift register 21, to the control input of which you send a signal (Fig. 3a) from the sixth output of the imaging unit 24 (to shift the result by one bit to the left). multiply it by a factor of two. This result is stored in register 14 by a signal (Fig. 3i) coming from the fifth output of the shaper 24 to the control input of the register 14, and in the inverse code from the second output of the register 14 is fed to the input of the multiplexer 18 and through the multiplexer 18 goes to the second input of the adder 20 according to the signal (Fig. Ze) from the eighth output of the driver 24. By the same signal, the multiplexer 17 passes to the first input of the adder 20 a signal in the direct code, which arrives at the second input, of the multiplexer 17 from the second output of the quadrant 19. The adder 20 during the TK (Fig. 3c) Diet addition of these signals.

At the same time, the result of the previous addition and shift from the first output of the register 14 (in the forward code) is fed to the first information input of block 22 and the signal (FIG. GC) received from the third output of the imaging unit 24 to the control input of block 22 is stored .on the input register of block 22. This signal owner 15

20

25

thirty

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24 passes to the input of the adder 2 For the same signal, multiplexer 1 passes to the first input of the adder 20 a signal coming from register 1 to the information input of the multiplexer 17. The result of the addition obtained through time T6 (FIG. 3c) is through register 21 ( without shift) goes to register 14, where it is memorized by a signal (Fig. 3). The signal ... (Fig. 3m), coming from the quarter output of the mapper 24 to the control inputs of the divider 23 and the register 16, receives numbers from the output of the register 15 through the first information input of the divider 23 to its register from the output of the register 14 through the second information input of the divider 23 into the register of the divisor 23, and from the output of the divider 23 through the information input of the register 16 - into its register. The result is made through register 16 and the first output of the device in the next cycle of calculations.

Operations in quad 19, block 22 and divider 23 are performed only with positive numbers, therefore, the sign is not taken into account in them. In addition, the numbers that occur on divider 23 are such that the divisor is always greater than the dividend.

The outcome of the algorithm, there are two possible exceptions. When the disturbance is much less than the instrumental shooters for performing one or more, when it goes around

radios calculating the root. The result of the calculation obtained through time T4 (Fig. 3F) is fed to the information input of the register 15, where it is stored by the signal (Fig, 3L) received from the eleventh output of the imaging unit 24 to the control input of the register 15.

After determining the sum by the adder 20, the result is fed to the register 14 through the register 21 (without a shift), stored by the signal (Fig. 3i) and waits until the block 22 is released. After the result of the extraction

50

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Signals and interferences are equal or their difference is much less than instrumental noise. Both of these cases are considered separately in the device by analyzing the sign bit of the adder 20, the signal from the sign bit of the adder 20 is fed to the information inputs of the flip-flops 25 and 26, the control inputs of which are given signals (Fig, III and n) respectively the shaper outputs 24., which remember the signs of numbers. If the sign of a negative number is expressed as lo5

0

five

0

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24 is passed to the input of the adder 20. According to the same signal, multiplexer 17 passes to the first input of the adder 20 a signal from register 13 to information input of multiplexer 17. The result of the addition, obtained through time T6 (FIG. 3c), through register 21 ( without a shift) goes to register 14, where it is memorized by a signal (Fig. 3). The signal ... (Fig. 3m), coming from the fourth output of the imaging unit 24 to the control inputs of the divider 23 and the register 16, receives numbers from the output of the register 15 through the first information input of the divider 23 into its register from the output of the register 14 through the second information the input of the divider 23 into the register of the divider 23, and from the output of the divider 23 through the information input of the register 16 - into its register. The result is made through register 16 to the first output of the device in the following. cycle of calculations.

Operations in quad 19, block 22 and divider 23 are performed only with positive numbers, so the sign is not taken into account in them. In addition, the numbers attributed to divisor 23 are such that the divisor is always greater than the dividend.

The outcome of the algorithm, there are two possible exceptions. When the interference is much less hardware

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Signals and interferences are equal or their difference is much less than instrumental noise. Both of these cases are considered separately in the device by analyzing the sign bit of the adder 20, the signal from the sign bit of the adder 20 is fed to the information inputs of the flip-flops 25 and 26, the control inputs of which are given signals (Fig, III and n) respectively the shaper outputs 24., which remember the signs of numbers. If the sign is a negative number is expressed lo71

1 unit (zero), then the direct (inverse) outputs of the flip-flops 25 and 26 receive signals to the first and second inputs of the OR 30 element, respectively, and from the trigger 26 to the information input of the trigger 28. From the output of the OR 30 signal, the signal goes to trigger information input 27. The signal (fig. 3m) from the terminal 24 triggers 27 and 28 remember the signs of the numbers of this calculation cycle. But since the result is only output in the next cycle, the sign of the number from the output of the trigger 28 goes to the information input of the trigger 29, where it is stored on the signal (Fig. 3m) of the driver 24 and is output to the second output of the device. from the output of the trigger 27 is passed through the element 31 and through the inverter 32 is fed to the second control input of the register 16, if the sign of the number is negative, then this signal zeroes the register 16,

As a result, if the interference is less than instrumental noise or not, then register 16 is zeroed out, and logical zeros appear on both the first and second outputs of the device. If the interference and signal are equal or their difference is less than the instrumental noise, then register 16 is zeroed, and at the first output - logical zeros, at the second output - a logical one. Thus, the second bit of the result is obtained through the second output of the device, the lower bits of which are passed through the first output.

Claims (2)

1. A communication channel quality control device containing a series-connected band-pass filter, an amplitude detector, and a low-pass filter, the input of a band-pass filter being a device input, characterized in that, in order to improve the control accuracy, a sync signal generator is introduced the first quadrant, the first integrator, the first analog-to-digital converter and the interference-to-ratio calculator are connected in series, the first and second outputs of which are, respectively, the first and second outputs of the device and after eight the second quadrant, the second integrator, and the second analog-to-digital converter, whose output is connected to the second input of the calculator of the interference-signal ratio, the third input of which is connected to the first output of the clock signal generator, the second output of which is connected to the other inputs of the first and second analog-digital signals converters, and the third and fourth outputs are connected respectively to the combined in pairs of the second and third inputs of the first and second integrators, the output of the low-frequency filter is connected to the input of the first quadrant whose output is connected to the input of the second quadrant. 2. A device according to claim 1, characterized in that the interference ratio calculator is a signal comprising a first register, a second register connected in series, a first multiplexer, an adder, a shift register, a third register, a square root extraction unit, a quarter register, a divider and a fifth the register, the output of which is the first output of the interference ratio calculator, is a signal, and the first and second inputs of which are the first inputs of the second and first registers, respectively, connected in series to the control driver, the first trigger, the OR element, the second trigger, the AND element and the inverter, the output of which is connected to the second input of the fifth register, are connected in series to the quadrant and the second multiplexer, the output of which is connected to the second input of the adder, and connected in series to the third, fourth and fifth triggers, the output of the latter is the second output of the interference ratio calculator — a signal, and the second input is combined with the second inputs of the AND element, the second and fourth triggers, with the third input of the fifth register, with the second input of the divider and nen to a second output of the control signals, which podklyunen third output to the second input of the square root, a fourth output is connected to the third input of the block extracting square, roots, to the third input of the divider and to a first input quadrant, the fifth output is connected to another input of the third register, the sixth output to another input of the shift register, the seventh output to the third input of the adder, the eighth output to the second inputs of the first and second multiplexers, the ninth output to the combined second inputs of the first and the second register and quad, the tenth output to the first input of the third trigger, the eleventh output to the other INPUT of the fourth register, and the first input is the third input of the interference disturbance ratio signal, the second output is the sum torus is connected to the combined second inputs of the first and third triggers, the output of which is connected to another input of the OR element, the third input of the quadrant is connected to the output of the second register, the second output is connected to the third input of the first multiplexer, the fourth input of which is connected to the output of the first register, the third input The second multiplexer is connected to the second output of the third register, and the fourth input is connected to the output of the square root extractor unit, the first input of which is combined with the fourth input of the divider.