SU780153A1 - Digital frequency discriminator - Google Patents

Description

(54) DIGITAL FREQUENCY DISCRIMINATOR

- one

The invention relates to radar and can be used in digital, frequency measurement devices.

Known digital frequency discriminator, made by a two-channel scheme, each channel of which contains a phase detector and an accumulator, where the reference source is connected to the phase detector of one of the channels directly, and to the phase detector of another channel through a phase shifter

However, the known discriminator has insufficient linearity and relatively low resolution.

The aim of the invention is to increase the linearity and resolution.

To do this in a digital frequency .discriminator, made on a two-channel scheme, the channel of which contains a phase detector and a combinator, the source of the reference signal being connected to the phase detector of one of the channels directly as well. to the phase detector of another channel — via a phase shifter, to both. the channel includes serially connected analog-to-digital converter, the input of which is connected to the output of the phase detector, the memory unit and the first multiplier, the averaging unit of signals whose input is connected to the output of the caster, and the second multiplier, as well as the inputs for are connected to the outputs of the averaging blocks of signals, and the output is the output of the Digital frequency discriminator, and the output of the first multiplier of each channel is connected to the first inputs of adders of the same Anal, koto 5 second inputs connected to the outputs ryh peremnozhitoley opposite second channel output of the analog-digital converter connected to the first channel Auto .rymi inputs of first multipliers,

20 and the output of the analog-to-digital converter of the second channel is connected to the first inputs of the second multipliers, the second inputs of which are connected to the outputs of blocks of the same name

25, where the decision block contains the first and second functional units connected in series, the module for determining the number modulus, the first adder and the sign assignment block, and

Claims (1)

30 also the first and second keys, the storage unit and the second adder, wherein the output of the first functional link is connected to the first input of the first key, the UMN block is connected to the second input of the first adder, the output of the sign assignment block is connected to the first key interconnected with the first input of the first functional link and are the first input of the decision block, the second input of which is connected to the second inputs of the sign assignment blocks and the first functional link, while the outputs to The switches are connected to the inputs of the second adder, the output of which is the output of the decision block. FIG. 1 shows the structural electrical circuit of the proposed discriminator) in FIG. 2 - structures on the electrical scheme of the decision block. Digital clock The final discriminator contains signal detectors 1 and 2, adders 3 and 4, phase shifter 5, decisive block 6, analog-digital converters 7 and 8, blocks 9 and 10 of memory, first multipliers 11, 14, and blocks 15 , 16 averaging signals, while the decision block b contains the first and second functional units 17 and 18, the module 19 for determining the modulus of the number, the first adder 20, the block 21 of the sign, the first and second keys 22. and 23, respectively, the second adder 24 and memory block 25. Digital frequency discriminator works as follows their way. The quadrature components of the received signal from the outputs of phase detectors 1 and 2 are fed to analog-to-digital converters 7 and 8, where they are quantized by time or amplitude, with the result that in each element of the time resolution M is generated. The arrival of the multipliers 11-14 current and delayed in blocks 9 and 10 for the repetition period are multiplied by two adjacent zones, the result is multiplied by adders. 3 and 4. The output signals of adders 3 and 4, which carry information from Doppler modulation of the received signal, arrive in blocks 15 and 16, where the received signal is accumulated from N adjacent elements of the time resolution, which allows to smooth the fluctuations of the parameters of the received signal and reduce the effect of the receiver's own noise. The functional link 17 divides the signals coming from blocks 15 and 16 / into each other, i.e. their ratio is determined, functional link 18 makes it possible to determine the average Doppler phase incursion of the generated signal over the Kth repetition period and implements the arc tg function. Block 19 of decision block 6 determines the modulus of the signal coming from the output of the functional link 18. Memorizing block 25 stores the binary code of value P. Block 21 assigns the sign of the signal coming from block 16 to the signal from the output of the first adder 20. The keys 22, 23 are controlled With a different discharge signal, the discriminator output signal is generated in the second adder 24. Thus, decision block 6 calculates the average Doppler phase shift of the received signal over the Kth repetition period, and hence the detuning frequency between the input signal and the reference, while the polarity of the output value of the decision block 6 indicates the detuning sign. The proposed discriminator allows increasing the linear part of the discriminating characteristic, significantly increasing the time resolution and eliminates the dependence of the measurement accuracy on the level of the incoming signal. Claim 1. Digital frequency discriminator, made by a two-channel scheme, each channel of which contains a phase detector and an adder. Moreover, the reference signal source is connected to the phase detector of one of the OGGs directly, and to the phase detector of the other channel through a phase shifter, characterized in that, in order to increase linearity and resolution, the analog-to-digital converter, which input the codec is connected to the output of the phase detector, the memory unit and the first multiplier, the averaging block. The signals, the input of which is connected to the output of the adder, and the second multiplier, as well as the common channel for both a deciding unit whose inputs are connected to outputs of the signal averaging units and the output is the output of the digital frequency discriminator, the output of the first multiplier of each channel is connected to first inputs of adders of similar channels, the second inputs of which the outputs Con OCheny second multipliers opposing channels; the output of the analog-digital converter of the first channel is connected to the second inputs of the first multipliers, and the output of the analog-digital converter of the second channel is connected to the first inputs of the second multipliers, the second inputs of which are connected from the output