SU1646070A1 - Digital multichannel receiver - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to increase the amount of received information. The receiver contains analog-to-digital converter 1, 47 two group adders 2 and 3, shaper 4 character bits, shaper 5 address signal, memory block 6, multichannel compressor 7, two multichannel adders 8 and 9, analyzer 10 signals, accumulating adder 11 , decisive block 12. two group decompressors 13 and 14, reference generator 15, switch 16, multichannel decompressor 17 and block 18 of the reference generator. The increase in the number of channels processed is achieved by increasing the speed of signal processing by changing the signal processing algorithm. 1 il.

Description

The invention relates to telecommunications and can be used in information transmission systems.

The purpose of the invention is to increase the amount of received information.

The drawing shows a structural electrical circuit of the proposed receiver.

Digital multichannel receiver contains analog-to-digital converter 1, first and second group adders 2 and 3, shaper 4 sign bits, shaper 5 address signal, memory block 6, multichannel compressor 7, first and second multichannel adders 8 and 9, analyzer 10 signals, accumulating adder 11, decision block 12, first and second group decompressors 13 and 14, reference generator 15, switch 16, multichannel decompressor 17 and block 18 of reference oscillators.

The receiver works as follows.

The input group signal using converter 1 is converted to digital and is fed to the input of group adder 3, on. the second input of which is synchronous receives the reference signal from the output of switch 16, converted by group decompressor 14, thus, the inputs of group adder 3 receive two digital sequences: logaA - input sequence and 1dgV - reference signal. At the output of the group adder 3, we get logaA + logzB - 1092 A-B, after passing through the decompressor channel 13 we get the value А В, from the output of the group decompressor 13, the signal samples go to the second input of the adder 2. To the first input of the adder 2 through the former 4, accumulated ny e counts come

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from operational block 6 of memory. From the output of the adder 2, the samples are returned to the memory block 6. The blocks (4, 2, 6, 5) collapse the baseband signal. The folding is carried out as follows. For each group, n - bit memory cells are reserved, and their addresses are written to shaper 5. The order of alteration of the signs of algebraic summation is remembered (or generated) in shaper 4.

The first count ai from the orthogonality interval, the boundaries of which are determined by the clock synchronization system, is fed to the input of group adder 2, the first input of which from the output of shaper 4 successively receives 2n samples, which are read from memory block 6 by addresses corresponding to the first of Ui cells each of the subchannels. Each of the counts is summed with ai, and the results are sequentially recorded in the cells from which the counts are calculated. Since at the beginning of the test, the memory block 6 is cleared (O are written), the countdown ai2n is actually summed with zero and written into the memory cells of each subchannel. Then, the second count 32 arrives at the first input of the group adder 2, which, similarly to the count ai, is rewritten into the second cells of the memory block 6 of each subchannel. Similarly, the recording process will continue until all cells are stored.

the memory of one of the channels, after which the reading order of readings from memory block 6 of this channel is reversed, i.e., at the next read cycle, the readout recorded in the last Ln cell is sent to adder 2, where it is summed up with the next input sample an, and the result is written back to the Ln cell. On the next cycle, the counting from the cell is described, etc. The cell addressing of the memory block 6 of other channels changes in the same way. Initially, the address of the cells increases from the address of the first cell to Ln, then the addressing order is reversed — from the address Ln of the cell to the first. In accordance with the change in the addressing order, the algebraic summing signs change.

After the last input sample, Ah, is summed with the Ln samples of the channel groups, the samples are read from the memory b block and, via the multi-channel compressor 7, go to the multi-channel adder 9, which is multiplied with the corresponding reference signal samples. Each reference signal is represented by a number of samples equal to Ln. An intermediate memory block is needed to store the group counts at the time of the summation with the reference signals. As an intermediate memory block, a memory block 6 is used. From the multichannel output

The adder 9 counts the signals, after decompression, it enters the inputs of the multichannel adder 8, in which the counts of each subchannel are summed. From the output of the multi-channel adder 8, the calculated correlation coefficients are fed to the inputs of the analyzer 10, the decision block 12, the adder 11. The analyzer 10 evaluates the signal quality and produces

respective signals controlling the switch 16.

The proposed receiver, in comparison with the prototype, allows to increase the speed of signal processing, thereby increasing the number of channels processed, the speed of the device, and also the costs per channel processed sharply.

Claims (1)

Invention Formula A digital multi-channel receiver containing an analog-to-digital converter, an address signal shaper, the output of which is connected to the address input of a memory unit, the output of which is connected to the first input of the first group adder, the output of which is connected to the memory input of the memory block, is reference. the generator, the first multi-channel adder, the output of which is connected to the first input of the decision block, to the first input of the signal analyzer and to the input of the accumulating adder, the output of which is dklyuchen to the second inputs of the decision block and the signal analyzer, the output of which is connected to the control input of the switch, the reference inputs of which are connected to the outputs of the block of reference oscillators, is also different because, in order to increase the amount of received information, the second multichannel adder, multichannel decompressor, two group the decompressor and the second group adder, the output of which is connected to the input of the first group decompressor, the output of which is connected to the second input of the first group adder, the output of the memory unit is connected to the input of the multi-channel compressor, the output of which is connected to the first input of the second multi-channel adder, the output of which the national decompressor is connected to the input of the first multi-channel adder, with this output of the reference generator is connected to the second input of the second multi-channel adder, and the switch output through the second group decompressor is connected to the second input of the second rpyhnoeoro adder, the first input of which is connected to the output of the analog-digital converter.  -, c ГГН гН iQJ Liiyj