SU1640742A1 - Group digital receiver of multifrequency codes with adaptive delta modulation - Google Patents

Abstract

This invention relates to digital receivers of multi-frequency codes with adaptive delta modulation. The goal is to increase noise immunity, accuracy and simplify the device. The goal is achieved by the joint use of sequential signal processing with the help of the 2 address switch and the RAM block 3 controlled by the master oscillator 1. The quadrature reception is carried out in the decisive blocks 5 whose reference signals are stored in the quadrature component memory block 4. Interference immunity and reception accuracy are provided by forming an adaptive threshold in register 10, a minimum level decoder 11, and an adaptive threshold driver 12, 1 sludge.

Description

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The invention relates to telecommunications and can be used to receive signals in tone frequency channels.

The purpose of the invention is to improve the noise immunity and accuracy of reception and simplify the device.

The drawing shows a structural electrical circuit of a group digital receiver of a multi-frequency code with adaptive delta modulation.

The group digital receiver contains a master oscillator 1, a switch 2 addresses, a RAM block 3, a quadrature component memory 4 and M decision blocks 5, each of which contains two quadrature signal processing circuits consisting of modulator 6, counter 7 and block 8 the module allocation, as well as the adder 9, the register 10, the minimum level decoder 11, the adaptive threshold driver 12 and the threshold code comparator 13.

The group digital receiver of the multi-frequency code with adaptive delta modulation operates as follows.

At the receiver input, namely, at the input of block 3, a group digital stream is generated, formed by multiplexing delta-modulated multi-frequency code signals. The sequence of samples of the group digital delta stream is recorded in block 3 as it arrives at the addresses corresponding to each channel, formed in switch 2. The cycle of synchronization of the master oscillator 1 is provided by supplying a pulse sequence with a cycle frequency to its input.

The analysis time of the two-frequency signal segment is determined by the minimum burst duration. Since the moments of the change of parcels are unknown and independent of the analysis interval, the latter chooses the outcome from half the minimum duration of the two-frequency mark.

To simplify the receiver, sequential single-channel processing of a multi-channel signal is performed. Here, the delta samples of the channels recorded in block 3 are analyzed in turn.

Since the entire write and read cycle from block 3 of all previously recorded information must be completed during the analysis, each clock period is divided in half. In the first half of the time, the signal is recorded in block 3 of the delta reference of signal 1 or O as it arrives in real time at the address of the next channel, and in the second half of the time reading occurs

from block 3 of another signal reference at the address of the channel that is to be processed at a given time interval.

In block 4, the recorded in block 3 delta counts of the signal of this channel are sequentially read to the inputs of modulators 6, which are signal multipliers. In the event of a coincidence of the delta-count sign recorded at this address, and

the sign of the reference of the sinus sequence of a given frequency from the output of block 4 at the output of the modulator b appears the level of logic O, increasing the unit of indication of the counter 7. Accordingly, when

the mismatch of the delta reference signs and the sine sequence, at the output of the modulator 6, a logic level appears, decreasing by one unit the readings of this counter 7 as a part of the decisive

block 5.

All of the above relates to the modulator 6 of the cosine component, associated with the input of the corresponding counter 7 of the second quadrature signal processing circuit.

The accumulation of information in the counters 7 of each of the crucial blocks lasts for half the time allotted for processing this channel. In block 8

by the high-order sign of the counters 7, the signs of the binary numbers written in each counter are determined. If the high order sign is positive, the code from the outputs of the counter 7 to the inputs of the adder 9 passes

without inversion; otherwise, it is inverted, which provides modulo addition of the sine and cosine components. From the outputs of the adder 9 information about the signal level of this frequency

rewritten to register 10, where it is remembered until the end of the processing time of a given channel. Writing information into all registers 10 of decision blocks 5 at the right time is provided by feeding to their combined inputs a write pulse from the output of master oscillator 1.

Recorded in each of the registers 10 code, taking into account the signal generated in

decoder 11, allows forming in the driver 12 an adaptive threshold proportional to the signal level of a given frequency, according to the results of the analysis for the first half of the information processing time

this channel. This adaptive threshold is used to make the final decision about the presence or absence of a component of a given frequency in a two-frequency signal at the end of the processing time of the given channel. Final

Claims (1)

The decision to receive a code is made in the decider 5 comparators 5. Claims of the invention A group digital receiver of the multi-frequency code with adaptive delta modulation, containing a master oscillator, a quadrature memory block and M deciding blocks, each of which contains two quadrature signal processing circuits consisting of a series-connected modulator, a counter and a module for calculating the module, the outputs of the modules for calculating the module of the sine and cosine signal processing circuits are connected to the inputs of the adder, The outputs of which are connected to the first inputs of a threshold code comparator, the output of which is the output of a decision block, the first and second inputs of which are the first inputs of the modulators of each circuit, the second inputs of which are respectively the third and fourth inputs of the decision block, the installation input of which is The combined installation inputs of the meters connected to the installation output of the master oscillator, and the first and second inputs of all decision blocks are connected to the corresponding 2M outputs of the quad memory module Saturn component, characterized in that, in order to increase noise immunity and accuracy of reception and simplification of the device; an address switch and a block of RAM are entered, and each of the M decision blocks are entered a register, a minimum level decoder and an adaptive threshold driver, the address outputs of the master oscillator are connected to the pairwise combined inputs of the quadrature memory block} component and the address switch, the outputs of which are connected to the address inputs of the operational memory whose output is connected to the combined third and fourth, the inputs of all decision blocks, the clock inputs of the master oscillator, the memory block of the quadrature components, the address switch and the memory block are combined, and the control output of the master oscillator is connected to the write inputs of all decision blocks in which it is a register write input, the inputs of which are connected to the outputs of the adder, the outputs of the register are connected to the pairwise combined inputs of the imager adaptive threshold and a minimum level decoder, the output of which is connected to the control input of the adaptive threshold generator, the outputs of which are connected to the second inputs of the code comparator threshold.