SU1501298A1 - Discrete information receiver - Google Patents

Abstract

The invention relates to a technique for transmitting discrete information. The purpose of the invention is to improve noise immunity. The device for receiving discrete information contains an amplifier-limiter 8, an automatic gain control unit 9 (AGC), an address signal extracting unit 10, an ADC unit 11, FORMING UNIT 12, COUNT POINT, SUPPORTING GENERATOR 13, GALOU FIELD, 14 AND BLOCK 16 FAST TRANSFORMATION (FBP) by WALSH. THE PURPOSE IS ACHIEVED BY PROVIDING DIGITAL TREATMENT OF THE RECEIVED SIGNAL WITH THE HELP OF A PROCESSING CHANNEL CONSISTING FROM ARU 9, ADC 11, multiplier 15 and BBP 16.

Description

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.315

The ejection relates to the technique of transmitting discrete information and can be used in the construction of synchronous and asynchronous systems for transmitting discrete information.

The aim of the invention is to improve noise immunity by digitally processing the received signal.

FIG. 1 shows a structural electrical circuit of the device for transmitting discrete information; in fig. 2 is a diagram of an apparatus for receiving discrete information; in fig. 3 shows a fast Walsh transform block; FIG. 4 - analog-digital conversion unit; in fig. 5 is an address signal allocation unit; in FIG. 6, a unit for forming reference points; in fig. 7 - generator Galois; in fig. 8 is a diagram of the first switch; in fig. 9 — shaper of control signals; in fig. 10 is a diagram of the second switch; in fig. 11 - solver; in fig. 12 - time diagrams of device operation; in fig. 13 shows timing diagrams of the Walsh Fast Transformation Block.

The device for transmitting discrete information contains block 1 of memory, block 2 of recording, registers 3, 4 of shift, blocks 5, 6 modulo two adders, cyi METOp 7 modulo two.

The device for receiving discrete information contains an amplifier-limiter 8, an automatic gain control unit 9 (AGC), an address signal extracting unit 10, an analog-to-digital conversion unit 11., A reference point generating unit 12, a reference generator 13, a generator 14 field Galois multiplier 15, fast Walsh transform block 16.

The fast Walsh transform unit 16 comprises a counter 17, an elemer1 OR block 18, a first switch 19, random access memory (RAM) 20 and 21, a control signal generator 22, an adder 23, a second switch 24, a resolver 25.

Block 11 of LCP of gotskit ADC 26, block 27 of comparison, block 28 of separation, adders 29, 30, registers 31-34 of memory, block 35 of comparison.

The address signal extracting unit 10 comprises a shift register 36, modulators 37 and 38.

The reference point shaping unit 12 comprises a clock synchronization unit 39, a recirculator 40, a key 41, a shift register 42, a copy generator 43, a multiplier 44, a counter 45

pulses, word block 46, adder 47 modulo two, decoder 48, averaging element 49, control element 50, block 51 of phase, controlled divider 52, frequency grid generator 53.

The generator 14 floor Galois contains the trigger 54, the adder 55 modulo two, the register 56 shift.

The first switch I9 contains D flip-flop 57. switching cells 58.

Shaper 22 control1 {x signals contains a synchronized generator 59, a frequency divider 60, a decoder 61, a decoder 62 iterations.

The second switch 24 contains the element HE 63, the elements AND 64, 65, the registers 66., 67 of the memory, the switching cell 68, the inversion block 69.

Solver 25 contains memory register 70, keys 71 and 72, memory register 73, comparison block 74, o

A device for receiving discrete information works as follows.

On the transmission side (Fig. 1), a message in the form of a sequence of characters is recorded in memory block 1. Then, through block 2, records are entered into the first shift register 3 with logical feedback through modulo-two adders block 5, where they are converted into an information signal sequence. The information sequence is summed modulo two with the address in the accumulator 7. The phase matching of the address sequence with respect to the information is established by entering the start code in the second shift register 4 with feedback through block 6 at the moment of writing the word in the first shift register 3.

On the receiving side (Fig. 2), the address sequence, which simultaneously serves to synchronize the receiving device according to words, is selected from the cumulative sequence that passed through the limiting amplifier 8, using block 10 (Fig. 5). By address

The signals and 6: ioKe 12 forming reference points provide the formation of marking pulses according to words that are synchronous with respect to the same marking pulses of a transmitting device. In this case, a synchronization pulse is extracted by the decoder 48 (Fig. 6), which, through block 51, performs coarse phasing on the word by setting the controlled divider 52 to the appropriate state) |

For this, a sample of the address signal from the output of block 10 through the key 41 g is recorded in the first digit of the register 42 of the circulator. The input of register 42 is then closed for F cycles (F is the duration of the address signal). following with frequency f x f.

g

(where f is the clock frequency of the input signal), the sample is recirculated. Since the length of register 42 is equal to F - 1 bits, then at the moment of entering the next sample into the first digit the previous one appears in the second bit. When register 42 is completely filled with samples of the address signal, the first sample is last fed to the multiplier 44 and disappears, and a new sample is entered for the first time.

A copy signal is generated at the output of the generator 43. promotion in which is carried out with the same clock pulses as in register 42, recirculator 40. Therefore, the input signal is compressed with time F, and the samples are slid relative to the copy signal. During the period of the address signal, the phases of the copy and the samples of the address signal coincide. The correlation integral is calculated using a multiplier 44, a pulse counter 45, and a decimator 48.

The synchronization pulses from the output of the descrambler 48 are fed to the input of the phasing unit 51 and provide the synchronism establishment mode. The signal from the multiplier 44 also enters the input of the adder 47 of the synchronization unit 46 according to the word, where it is added to the signal generated at the output of the controlled divider 52. The signal from the output of the adder 47 is information for accurate phasing and synchronization in block 46. In this In this case, all information stored in the address signal is used.

ten

20

le. The formation of the discriminatory characteristic is performed by summing modulo two signals from the code of the multiplier 44 and the controlled divider 52.

The overall mismatch of the signal from the output of the multiplier 44 with respect to the common-mode state results in the predominance of one or another sign. This fact is used to monitor the phase of the address signal. If the reference signal is lagging (ahead) from the center of the pulse defined by the 15th last bit of the address signal, then the output frequency of the element 50 is changed by adding (excluding) the pulses to the original sequence. The averaging element 49 serves to eliminate the influence on the synchronization accuracy of all the clock intervals of the address signal, except the last one. The clock synchronization is performed by the block 39 25 clock synchronization by a signal from the output of the amplifier-limiter 8.

The signals from the output of block 12 serve to advance the reference generator 12 and the generator 14 of the Galois field. In this case, the generators 13, 14 are set into the initial state (by signals from the output of divider 52) and the information is promoted in the registers of the generators 13, 14. The clock synchronization pulses also define the interval, integrated in the ADC block 11.

Signal processing is performed by analog-to-digital conversion. The input signal (Fig. 12a) through the AGC block 9 is fed to the input of the A / D converter 26 of the block 11 (Fig. 4), where it is converted into a digital form (Fig. 125). Comparison unit 27 is used to determine the polarity of the signal. The code from output 45 of the ADC 26 is compared with a threshold number corresponding to the average value of the dynamic range of the 9 AGC block. In the case that the threshold number is exceeded by the code, a single potential is formed at the output of the comparison unit 27. Otherwise, the potential at the output of block 27 is zero. The sequence of sample codes from the outputs of the separation unit 28 (Fig. 12b, d) gg are processed by an integrator made according to a two-pole scheme. The integration is carried out by summing the samples, taking into account their sign, and the integration interval is 30

35

40

50

The period of the clock pulse from the output of block 12 is positive. Positive signals in the form of codes arrive at the input of the adder 29, where at the first moment they are added to the zero code. The resulting amount is through the record register 31 and the register 33 is fed to the second input of the adder 29 and added (Fig. 12a with the value of the subsequent counting, etc. Thus, the positive counts are accumulated with the accumulation. The accumulation operation with the accumulation of negative counts (Fig. 12e) Essence is in the second shoulder of the integrator (elements 30, 32, 34). The results of the summation of positive and negative samples are compared in element 35. As a result, the reconstructed normalized signal of the information sequence is formed. elnosti (FIG. 12).

The sequence from the output of block 11 is multiplied in multiplier 15 by the address sequence, which is synthesized by the reference generator 13 (Fig. 2). As a result, an information sequence of characters is extracted from the combined one, which is fed to the input of the fast Walsh transform unit 16. Depending on the phase shift of each bishop on the information sequence, at the output of block 16 goat transformation factors are formed that carry information about the transmitted message.

The process of isolating the message is to cast the M-sequence to the Walsh function and then apply the Walsh transform. Prize; the processed sequence to the Walsh function is provided by permuting the M-sequence symbols in accordance with the addresses specified by the Galois floor generator 14, and adding a null component, with address 000.

The Walsh transform is to determine the number of the function of the bush from the ordered Hadamard matrix. The function number uniquely identifies the information above the content of the transmitted message encoded in the M-sequence.

The i-ro sequence of words arrives t (a input of the switch 19 (Fig. 3 of the Walsh Fast Transformation Block 16. Arr; 1 word is processed using the fast conversion algorithm)

five

0

five

0

five

0

five

0

five

The formation of control signals.ch in block 22, the pulses of the clock frequency T from the output of block 12 (the normalization of the reference points sets the generator 59 to its initial state (Fig. 9), thus linking the output C) of the sequence the following 8 G) to the phase of the synchronizing signals (f), using the functions of 1 body 60, the decoder 61 and the decoder 62 iterations, control signals (Fig.) are generated that are suitable for the operation of the fast Walsh transform unit 16.

Under air: T jueNi synchronized (by word and tact) signals (Fig. 136) s to r-: oder 22 via trigger 57 (4) ig. 8) Osuskhos P - ts (with the help of 14 (.op;) 8 commutation Opportunity to connect,:; sol l 1 AFIII to information 1) ZU 20 and character-by-word saiiuci. ((mi. Hzb) syllable 2a in accordance with the stress specified by (synchronous) 14 14 Galois pop. On entering i + 1 words, the entry was made in s in RAM 21. This is: the time is realized; ((i) ro words. For example, when the length of the code word is 511, the elementary characters perform nine iteration procedures. At the first iteration, the character is read from the memory 20 (FIG. 13e

). recorded in the cell with the address 000. The address is set by the counter 17. This (5 according to the recording signal from the output of the element 64 AND (Fig. 10) enters the memory register 66 of the switch 24. Then the contents of the cell with the address 256 are read. This address The SPS-1M mode is generated. Counter 17 generates the number 000, which is 1 in the block 18 with the number 256 (from the output of block 22), represented in binary code. RAM 20 with address 256 in register 67.

In this case, the write enable signal in the register 67 is inverted in the HE element 63. In the adder 23, the drying operation is a summation operation of the numbers in the registers 66 and 67. In this case, the inversion unit 69 passes the number from the output of the register 67 to the input of the adder 23 no change. This is ensured by filing a zero code with

output le1Sh frator (S2 iteratssh to the input of block 69,

Cyr-iMa numbers are entered into a cell of 000 RAM 20, then a subtraction operation is performed over the numbers of registers 66, 67. The subtracted number X: from the output of register 67 is inverted in block 69 modulo 1. This operation is represented as 1 X: (j is the address of a number) and is implemented in block 69 using an adder, the OR element and the block of elements EXCLUSIVE OR OR, Number 1 in the inverse code goes to the adder of block 69 from the output of the decoder 62 iterations, and the number X; from the output of register 67. The difference of numbers

recorded in registers 66, 67 using switching cells 68, is entered in RAM 20 at address 256,

In the next processing cycle (Fig. 13a), the output of the counter 17 is formed. Address 001 is generated. Next, the described operations are repeated, and so on. When the number 511 (in binary code) appears at the output of block 18, the counter 17 is set to this state. The installation is performed according to the signal of the decoder 62 iterations (Fig. 13k).

The processing algorithm in the first iteration is written as follows:

000 256 000

oo (oo (

000 256 256

001

- X

251

where X - is the result of processing.

At the second iteration, the same actions are performed on the iXj symbols recorded in RAM 20. In this case, the decoder 62 iterations of the block 22 sets the control mode of the second iteration, i.e. to addresses configured

117 455 f2-f

41

255

"55

where X is the result of operations on the second

 iteration.

On the Kth iteration algorithm, the control algorithm is determined as follows: counter 17 addresses are summed up in block 18 with LC number 256/2, counter 17 is installed simultaneously with processing at the ninth iteration, decider 25 decodes information (using the maximum likelihood method), t . finds the maximum) patient

J5S 5P 7SS

V Y -I Y 255 511

Install counter 18 End of iteration

the counter 17 adds the number 128. The symbols Xj are inverted in block 69 modulo two (operation 2-X;), and the installation of the counter 17 is performed twice as often.

The processing at the second iteration is written as:

"6 ser

.- X

594

: X5 „- X

at

tet

Install counter 1B End of the iteration

the cut B 512/2 processing cycles the inversion of the subtracted number in block 69 is performed modulo 2 and is provided by the operation - X. At the last, ninth iteration

the results of the control unit (Yj) are defined as follows.

511

X

5m

 Sio

5M

Installation

counter

18

the end

iterations

55 Y transforms: and its address defining the received information symbol. The conversion factors Yj are successively input to the comparison unit 74 (Fig. 11).

eleven

and on the input of the retra 70. At the same time, the corresponding address j is written to the register 73. Writing YJ and addresses j (Fig. 13k) to registers 70, 73 is performed if Y. Y:. | , by signals from the output of the keys 71, 72. The recording resolution is determined by the block 74 of the comparison.

Thus, at the end of processing, register 70 contains Y; in register 73, the corresponding address specifies the receiving information symbol.

Upon completion of processing the i.-ro word using the switch 19, the RAM 20 is connected to the outputs of the block 11 and the i + 2 words are written, and the i + 1 words written in the RAM 21 are processed according to the indicated algorithm.

Formula and 3 about b e e} and

Claims (2)

one . ycTpoiicTBO for receiving discrete information, containing a series-connected limiting amplifier and an address signal extracting unit, as well as a unit for forming reference points, the input of the limiting amplifier being an input of the device, characterized in that, in order to improve noise immunity by digitally processing the received signal , introduced in series are an automatic gain control unit, an analog-to-digital conversion unit, a multiplier and a fast U. Walsh conversion unit, a generator The first input of the automatic gain control unit is connected to the amplifier amplifier input, the output of which is connected to the first input block of the formation of reference points, the output of the address signal allocator is connected to the second one. the input of the unit of formation of reference points, the output of which is connected to the second input of the analog-to-digital unit; transducer, to the input of the reference generator and to the second input of the fast Walsh conversion unit, the output of the analog-digital conversion unit is connected to the second input of the automatic gain control unit, and the generator output of the Galois floor is connected to the third input of the fast 1Q Walsh transform, the output of which is the output of the device. 2. The device according to claim 1, about tl and - that the block of fast Walsh transformation contains | 5 serially connected counter, OR block and first switch, serially connected control driver, adder and second switch, as well as the first and second operative memory and solver, whose output is the output of the fast Walsh transducer, the first input form yuwatel The 25 control signals and the second and third inputs of the first switch are respectively the second, third and first inputs of the fast Walsh transform unit, the first and second The 3Q outputs of the first switch are connected to the inputs of the first and second random access memory, the inputs / output of the first switch are connected to the inputs and outputs of the first and second random access memory and the second switch and to the first input of the solver, the output of the OR block of the elements with the second entrance 35 0 and with the second input of the control signal generator, the second output of which is connected to the third input of the resolver, the third output - to the second input of the second switch, the fourth move - to the third input of the counter and the fifth output - to the second input, block of OR elements, the third output of the first switch is connected to the third input of the control signal generator, and the second output of the second switch is connected to the second input of the adder. 0 Fig.Z Physical 5 $ 49.6 Fiz.7 Otgsf About TOS and 61 SI Phases. ten IS 18 Fiu.i  four