SU1026144A1 - Correlator - Google Patents

Abstract

CORRELOMETER, containing a p-bit counter, the outputs of which bits are connected to the corresponding inputs of the fixed memory block and the memory block, the control of the KOToi orb input is combined with during the counter and the synchronizer input of the adder and connect it to the output of the generator a mountain of clock pulses, information inputs and outputs of the memory block are connected respectively to the corresponding outputs and the first information inputs from: the mmator, the mode switching input of which is connected to the output of the last digit of the counter, the K-th output The DAC of which is connected to the control input of an analog-digital converter, whose information input is a device input, characterized in that, in order to improve speed, a block of general registers is entered, the write address inputs, the address read inputs and the control input are connected correspondingly, with the corresponding high-current moves of the counter bits, the corresponding outputs of the fixed memory unit and the control input of the analog-digital converter, and the outputs of the block general registers are connected to the corresponding second information inputs of the adder.

Description

The invention relates to specialized computer aids and can be used in automatic control systems for detecting a reference frequency modulated signal in a random signal being analyzed. A known digital correlator for detecting echoes, comprising an analog-to-digital converter, digital delay lines, a reference signal generator, a pulse generator, a multiplication unit, and a fl3 averaging unit. The disadvantage of this correlator is relatively low fast action, i closest to the technical essence to the proposed is a correlometer containing an analog-to-digital converter, the input of which is the input of the device, and the outputs are connected through the element AND to the inputs of the additional elements OR and AND, - the outputs of which are connected via OR elements to the inputs of the adder, the outputs of additional elements OR are connected to the inputs of the fixture block of the standard deviation, the code of which is connected to the input of the control unit containing the pulse generator and the counter whose outputs are connected respectively to the inputs of the analog-digital converter unit a fixed memory in which a reference signal quantized into two levels is recorded, an adder and a memory unit in which the sums generated in the adder, the information The memory inputs and inputs of the memory unit are connected respectively to the outputs and inputs of the adder, the outputs of the fixed memory unit are connected to the inputs of the elements. However, the correlometer has an insufficiently high speed associated with the need to perform, over a period of time sampling, N operations of multiplying the values of a quantized two levels of a single signal to the output code of an analog-digital converter and N addition operations of received works with current sums. Here is the number of evaluation points for the mutual correlation function.-. The purpose of the invention is to increase the speed of detection of signals. The goal is achieved by the fact that a correlometer containing a W -pas is a random counter, the outputs and bits of which are connected to the corresponding address inputs of the fixed memory unit and the memory unit, the control input of which is combined with the input of the counter and input 4 synchronization of the adder and connected to the output of the generator of clock pulses, information inputs and outputs of the memory unit are connected respectively to the corresponding outputs and the first information inputs of the adder, the mode switching input of which is connected to the output Om of the last digit of the counter, the output of the tth digit of which is connected by the control input of the analog-digital converter whose information input is the device input, a block of general purpose registers, the write address entries, the address read inputs, and the control input are entered the input, which is connected respectively with the corresponding outputs (and "-P senior bits .. L counter, the corresponding inputs of the memory block and the control output of the analog-digital converter, and the outputs of the general-purpose register unit and are connected to respective second inputs of the adder information. Figure 1 shows the structural diagram of the device; Fig. 2 shows the formation of constants of the reference frequency-modulated signal. The correlometer contains an analog-to-diffraction converter (ASCH1) 1, a unit 2 of general purpose registers (RON), an adder 3, a block 4 of a permanent memory, a block 5 of memory, and a discharge counter b and a generator of 7 clock pulses. The random signal X under study (-b in the device (Fig. 1) is fed to the information input of the A / D converter 1, the control input of which is connected to the control input of the RON unit 2 and .disable to the output of the Cth digit of the counter 6. Information the input of the RON block 2, the read write address inputs are connected respectively to the corresponding ADC 1 outputs, the outputs (, and-8) of the higher bits of counter 6 and the outputs of the fixed memory 4, the address inputs of which are combined with the address inputs of the block 5 memory and connected to the corresponding outputs of the bits of the account A key b, the input of which is combined with the control-input of the memory block 5, the synchronization input of the adder 3 and connected to the output of the generator 7 clock pulses. The outputs of the 2 TON block are connected to the corresponding first information inputs of the adder 3 the second information inputs of the adder 3 are connected to the outputs of memory block 5. The correlometer works as follows: To detect in a random signal X. (- fc) reference frequency-modulated signals of the form j (t) 51MLtlbt) .3 of duration T in. block 4 of the permanent memory is recorded by characterizing the reference signal V W binary G-type Bi (ЬЬ, ..- bw,), where -1 0,1, ..., U "-11. The process for 4I bans, dl is shown in FIG. 2. The signal (t) is preliminarily filled in time with a period of a prerequisite of L 1 / t; where fj is equal to the clock frequency from the first synchronization output of the counter 6. The obtained sequence of signal ordinates splits C into 2 blocks by M through 2 ordinates f r-de j-0.1,.,. (M - i.: -..:: These ordinates are quantized into two levels, with the unit value being assigned to the ordinates having the maximum value in the following way: yt () 6l- 3tiMi jiOu3 other cases, so we get 2 blocks of 2 numbers Y | d in each block. Since in any period of the reference signal there are large M counts, then in each block only one number can be equal. Each block of V-ij numbers, as shown in Figure 2, corresponds to the binary number B Ctfeb -f.-brn a and if in the 1st block j Dg then i (bob4.v-bm-Jtfe If In this block all the numbers yjj are If the zero value, then 8 O-Number characterizes the presence and location of the max galum reference signal in the V-th block. A random input signal x (t) is formed in A / D converter 1 in a c-bit binary code with a quantization frequency. the signal is divided into blocks of M samples 5 yjWoi - K-) ai I where, 1,2, ... is the block number of the input signal; - the count number in the block. For detection: reference signal of the modulated signal in a random nominal signal kCt) in the correlometer Forms of the sum of-t1 -h,; i Jo | o i - “-. where p g -N t 1 i Si, Exceeding the value S of a given threshold SP is a criterion for detecting a signal. For narrowband signals xft) and Vft) with slowly varying amplitudes and phases, the estimates | t, y-Sy, / M are linearly related to the estimates of the correlation function R) (j, calculated by the relay correlator; Rj uslRx}. -batch counter b from the generator output 7 clock pulses pschtupat pulses with the following sequence 0, the frequency of the pulses from the outputs of the t-th and I-th bits of the counter, respectively, equal to / 2 and f n-bit outputs of the counter-b fyrmirzg with frequency f BINARY code. 1 0.1 ,,, (N -1J numbers of the stroke, where,, and at the output ht (Vi-6) of the most significant bits - at frequency f, j The binary code is J 0,1 j ,,,,. (M-1) the numbers of the number of the Hgm block,: each block with ns of 1 g contains .M 2; NUMBER B of l B left 1 g is recorded in block 2 ROY consisting of the two halves, each of which contains M memory cells of the size to. For one device operation cycle with frequency ff, M numbers of the nth block i are written to the memory cells of the first half of the RON block 2, whose addresses are binary numbers a code at the outputs (w-CV of the higher bits of counter 6, during this cycle, from the second half of block 2, JPOH with frequency o is produced. reading from the cells whose addresses are determined by the output of the 1 {th-th-bit code of the block 4 of the permanent memory. During the following cycle) -i, the input signal block is recorded in the second half, and the reading is performed from the first half of block 2 POH. After each cycle of operation of the device occurs. The switching of the halves of the PQi block 2 .: Each cycle is calculated and composed. cycles with numbers 1 / 0,1, ... (H-1). The binary code of the cycle number from the outputs of the Y-bits of counter 6 with the frequency fo is fed to the address inputs of the block 4 of the constant pa, mta and block 5 of the memory. The constants B, coming from the output of block 4 of the permanent memory to block 2 of the ROH, are read from it by the values of X.J. + B. Thus, in the 1st cycle of the calculation cycle, in the axis of the block 2 RON is generated. For the calculation of 8), a partial sum | -:, -., -. . -h (.CV-i) G where V is 1,2 ,,,. (N-1). Partial sums are recorded in memory E block, with the cell number of memory block 5 coinciding with the number of partial dry / located in it; When adding a term to a partial sum with a number (V, it moves to the cell of memory block 5 with number t (4i) r equal to the number of digits 4x in partial sum. Memory block 5 works in read mode, with values of clock pulses 1 and mode records / at values of pulses equal to 0. Read 43 blocks of memory 5 and save information on its outputs until the arrival of the next efficient pulse.

The synchro1I input and the switching input of the adder mode, 3, are fed, respectively, from the generator of 7 TMo pulses and the pulses of the start of the TIdS cycle of the old discharge of the counter b. The frequency of tracking TI pulses is a. 4/2. After the arrival of the leading edge of the pulse, the type of Gkbto coincides with the beginning of the zero cycle, the content of the adder 3 is compared with the code, the threshold Sp. And this information from the code of the RON 2 comes directly; . The output of the adder is 3. In the remaining cycles with spacings i, 2, r .. (N-l), the adder 3 works in the direction of addition of the codes from the outputs of block 2 RON and the block “5 neiMHti. After passing the leading edge of the TI-p pulses, the contents of the fiontopa 3 are recorded on its outlets, and on the information output of counter 6, a tick number code is formed, in a zero cycle of the cycle with number f the sum of Sr-V is compared to noporosM, and on the output of the block. 2 RON, the value of the clock cycle is formed by issuing 5 at the output of the adder 3, calling the partial cell from the first cell of block 5 partially, and generating at the RON output 2 values, Sj, xg. After passing a pulse TI (Tio-0), the sum of $ f .; is written to the first cell of the memory block 5. The first cycle ends with the form1, {yi ova2H, in the sugmatorer 3 sukma d «Myug in the second cycle of calculation B, the adder 3 forms a partial cy: ". and $ I4 is fixed on its I-output and, after the birth, the TL is entered into the memory cell of the memory unit 5. And the last cycle of the cycle in the summator.3 & o1 is determined by cyi "iMa Yy - 5, -. 4, + h-, and in the last cell of block 5, the sum of Sy ;,.

Thus, for one cycle of operation of the device, a comparison is made with the sum threshold (forgating r and updating partial sums; t; i.e., with every y1 shift of the input signal hX Ct) by the time Tg. These points estimate the correlation of the analyzed and reference signals.

Introduction of unit 2 RON and additional. compounds can significantly improve the performance of the correlometer. Indeed, if in the prototype for the formation of B, -X it is required to perform M addition operations, then in the proposed device they are replaced by a single-stroke read operation from the general-purpose register X-j-.j with noler b4, i.e., bstrodysteistb increases by M times. For example, with M 8 / K 8, W 256, using serial chips, the correlometer allows analyzing signals with a high frequency of up to 15 kHz, which is eight times higher than the frequency of the signals processed in devices implementing the prototype circuit.

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Claims (1)

CORRELOMETER containing an η-bit counter, the outputs of η discharges of which are connected to the corresponding address inputs of the read-only memory block and memory tank, the control input of which is combined with the counter input and the synchronization input of the adder and connected to the output of the clock generator, the information inputs and outputs of the memory block are connected respectively, with the corresponding outputs and the first information inputs of the adder, the mode switching input of which is connected to the output of the last digit of the counter, the output of the 8th bit and is connected to the control input of the analog-converter, whose data input is input "! devices, characterized in that, in order to improve performance, a general-purpose register block is introduced into it, the address entries of the record, the address inputs of reading and the control input of which are connected respectively with the corresponding outputs (I ~ 6) of the upper bits of the counter, the corresponding outputs a read-only memory block and with a control input of an analog-to-digital converter, and the outputs of the general-purpose register block are connected to the corresponding second information inputs of the adder. & 1026144 2