SU1617447A1 - Autocorrelator - Google Patents

Abstract

The invention relates to a technique for measuring the characteristics of random processes and is intended to determine the autocorrelation functions (ACFs) of current stationary processes. The aim of the invention is to improve the accuracy. In the autocorrelator torus, an ACF estimation algorithm with exponential smoothing is implemented. The autocorrelator includes a pulse generator, analog-to-digital converter, memory blocks, pulse formers, AND elements, OR elements, counters, frequency divider by three, triggers, adders, multipliers, subtractors, registers, delay elements accumulating adders. 1 il.

Description

The invention relates to a technique for measuring the characteristics of random processes and is intended to determine the autocorrelation functions of current squeezed processes.

The purpose of the invention is to improve accuracy.

The drawing shows the scheme of the proposed autocorrelator.

The autocorrelator includes a pulse generator 1, an analog-to-digital converter (ADC) 2, a memory block 3 for Jj cells, first 4 and second 5 pulse shapers, And 6 elements of the first and n elements And 7 of the second group, n elements OR 8 , (n-1) counters 9, divider 10 frequencies by three, n flip-flops 11, n blocks G2 of memory group, n adders 13, (n-I) multiplication blocks 14, (n + 1) subtract blocks 15, (n +1). Registers 16 second

groups, (n + 1) additional counters 17, (n + 1) registers 18 of the first group, (n + 1) elements of delay TE and (n + 1) accumulating 1 such adders 20.

The autocorrelator implements an algorithm for estimating the correlation function (QF) with exponential logarithmic smoothing. The type of algorithm is determined by the functional transformation over the signal samples.

The device works as follows.

Before you start, the memory block 3, memory blocks 12, triggers 11, score-. 9, registers 18 and accumulating adders 20 are zero. In i-x registers 16 and counters 17, a code is entered to log the number of pulses in the number system in which the device operates. For a binary number system, this is the code

S

(L

with

05

four

JJM..n ,, where m is the width of the registers 16. In the zero register 16 is the code

, 111 ... 0. A / D converter 2

temporalization of the input signal or its sign on the leading edges of the rectangular clock signals of the oscillator 1 of the pulses, which are used to receive the discrete input signal in the first cell of the memory block 3 and shift the contents of the memory cells of the memory block 3. The shapers of 4 and 5 pulses form short pulses along the leading edges of every second clock sync pulse, starting from the first and second clock sync, respectively. In this way, a series of short sync pulses of a half clock frequency clock shifted 180 relative to each other is carried out. With the arrival of the first leading edge of the first clock signal of the pulse generator 1, the first sampled signal is received in the first cell of the memory block 3, and the first multiplication unit 14, the first subtraction unit 15, the first register 18 and the first accumulator 20 starts to work accumulation of the sum of squares of samples of the input signal:

 . - H

(one)

where KX (O) f 0.

If a variant of KF evaluation algorithm is used, relay, polar, etc.

then the corresponding functional

the conversion can be performed before multiplication in block 14.

The cycle of operation is repeated with the arrival of each subsequent sync pulse. With the arrival of the leading edge of the third sync pulse, the first time triggers a frequency divider 10 and its output signal through the first element And 7 of the second group, opened with a single signal from the inverse output of the first trigger 11, and through the first element OR 8 enters the recording input of the second memory block 12 TI, which receives the trawl of the process readings or their signs, which are in its first cells. The same signal from the output of the first element OR 8 switches

trigger 11 into one state, locking the first element And 7 of the second group and opening the first element And 6 of the first group. Since the passage of the clock through the element AND 7 and the element OR 8 and the triggering of the trigger 11 takes some time, a short pulse from the output of the first driver 4 pulses, formed on the leading edge of the third clock signal of the pulse generator 1, does not have time to pass through the first element And 6 Groups The next short pulse is formed through two clock pulses of the pulse generator 1.

During this time, the sum is formed in the first adder 13.

f (i) + fCij), (2)

in the first block 14 - the product

f (x,) + f (xj). fCio), (3)

in block 15 subtraction - the difference

f (x,) + f (x,) f (i2) - K (1), (4)

 ABOUT

where Kj ((1) O (at the initial moment of the device operation).

The first clock pulse, which came from the output of the first element And 6 of the first group, allows the contents of the second subtraction unit 15 to be written to the register 18. After a delay time sufficient to operate the registers 18 and 16 and the counter 17, this same clock also allows the accumulation of the contents of the register 16 in the accumulating adder 20. The signal from the output of the first element AND 6 of the first group also goes through the first element OR 8 to the input of the record of the buffer storage unit 12, allowing reception of the next samples to this buffer storage unit 12. The cycle of operation of the first channel of the correlator is repeated every two sync pulses of the pulse generator 1.

With the arrival of the leading edge of the 3rd; clock signal synchronization j-th time divider 10 frequencies into three and its output signal through the j-th element And 7 of the second group, opened by a single signal from the inverse output j-ro trigger 11, and through j element 8 or 8 is fed to the counting input of the corresponding counter 9 with a conversion factor j. Since before this, the input of this account516

When the j-pulse arrives at the overflow output of this counter 9, a signal is generated that is fed to the recording input of the j-ro memory block 12, which receives 3J process samples or their signs located in the first 3 cells of the memory block 3. The same signal from the overflow output of the counter 9 with the recalculation coefficient j switches the jth trigger 11 to the unit state, locking the jth element AND 7 of the second group and opening the jth element AND 6 of the first group. If j is an odd number, then the first input of the j-ro element And 6 of the first group is connected to the output of the first driver 4 pulses. In this case, with the arrival of the 3j-ro sync signal, the first input of the j-ro element of AND 7 of the second group to the first input of the j-ro element of AND 6 of the first group comes (3jl1) / 2nd pulse of the first driver 4 pulse. However, since the passage of the 3j-ro clock through the jth element AND 7 of the second group and the jth element OR 8 and the activation of the j-ro control trigger 11 requires a certain time, a short (Jj + 1) / 2nd pulse from the output of the first driver 4 pulses does not have time to pass through the j-th element And b of the first group. The next short pulse in the code of the first shaper 4 pulses is generated through two clock sync signals.

During this time in the j-th adder 13 is formed the sum

f (x,) +, (5)

, .in j-M block 14 - product

f (x,) 4- f (x2j ,,) f (x.,), (6)

in j-M block 15 subtraction - the difference

f,). f (x, j. ,,) lf (x, - ,,) -K; (j), (7),

where Kjj (j) 0 (at the initial time of the device operation).

The first sync pulse passed from the output of the j-ro element And 6 of the first group allows the contents of the j-ro block 15 of the subtraction to be written to the j-th register 18. After a delay time sufficient to trigger the registers 18 and 16 and the counter 17, the same sync pulse allows the accumulation j-ro content

6

174476

register 16 in the j-adder 20. With the arrival of each i-ro sync-J pulse (i 1-fj) from the output of the j-ro element I 6 of the first group, the j-th accumulator 20 accumulates an intermediate transformation in accordance with the expression:

ten;

K (j)

  / J - Jeo. (X.;. I) x 4; (2; -2)) - k; (j)

(eight)

The cycle of the j-ro channel of the autocorrelator is repeated through the j sync pulses that came from the output of the first driver 4 pulses through the j-th element of I6 of the first group. After that (with the arrival (j + D-ro of the sync pulse from the output of the j-ro element I 6 of the first group in the j-th memory block 12

2, the following 3j samples of the input process are shifted by the clock signals in memory block 3 to 2J memory cells. With the arrival of the j-ro clock sync signal, at the output of the j-ro accumulating adder 20, an estimate KF of the input process is formed.

If j is even, the operation of the j-ro channel of the autocorrelator is similar to that with the difference 5 that the first input of the element And 6 of the first group comes from the output of the second driver 5 pulses.

Auxiliary je register 16 and counter 17 carry out the logarithmic number of pulses coming from the output of the j-ro element AND 6 of the first group corresponding to the number of averaged pairs of products of process counts based on gCg 2) and shift 5 of the contents of the j-ro register 18 by the amount. int (.m3). This happens as follows. Before starting work in the J-X register 16 and the counter 17, the code 111 ... 1 is located. With the arrival of 0 of the first clock pulse on the counting input of the j-counter of counter 17, corresponding to the moment of formation of the pair of factors (6), a signal appears at its overflow output, which 5 shifts the contents of j-ro register 18 by one bit to the right (which corresponds to dividing expressions (7) by two). The same signal enters the recording entry of the same counter 17 and writes the contents of the j-ro register 16 into it, i.e. code 11 ... 10, and then shifts the content of this register 16 by one bit to the left, to form the code 11 ... 10. With the arrival of the second clock pulse at the input of the j-ro counter 17, he again generates a signal on his overflow, shifts the content of the j-j of the 18 register 18 to the right by din bit (which corresponds to division by 4), accepts code 11 ... 10 from j-ro register 16 and shifts the content of this register 16, thus forming a code (1 ... 100, and tal) until the end of the work.

The first auxiliary register 16, counter 17, work similarly to the difference that counter 17 re-reads each clock pulse 20 from the clock of 1 pulses.

With the arrival of the last N-ro clock sync pulse at the outputs of the accumulating adders 20, the auto-KF estimates of the input process are formed. Moreover, with f (xj) signx; i.e. the sign function of the process reference, the resulting estimates of the polar auto-KF are formed. In this case, the concept is much simpler. zo

In addition, unlike the prototype, the proposed autocorrelator makes it possible to eliminate the methodological error of averaging the CF estimate of the input process, especially with a large number of CC ordinates,

Claims (1)

Invention Formula An autocorrelator containing an analog-to-digital converter, whose information input is the information input of an autocorrelator, a pulse generator, a memory block, a group, of n (n is the number of correlation samples function) of memory blocks, n summators, n − 1 counters, n flip-flops, n NLI elements, n elements of the first group, n elements of the second group, n + 1 multiplication blocks, n + 1 accumulating adders, frequency divider by three, the first pulse shaper, and the information input of the memory block is connected to the analog output digital converter, j-th information input (i 1, ..., 3j) j-ro. (j 1, ..., n) of the group memory block is connected to the i-th output of the memory block, the first output of which is connected to the first 35 the output and second inputs of the first multiplication unit, the recording enable input of the first group memory and the information input of the first trigger are connected to the output of the first element OR, the outputs JX of elements AND of the first and second groups are connected respectively to the first and second inputs of the j-ro element OR, output the pulse generator is connected to the clock inputs of the analog-digital converter and the memory block, through the first driver of the pulses to the first input (2k-1) -ro , (k 1, 2, ..., n + 1. element and the first 0 5 o d P five group and through a frequency divider by three - to the first inputs of elements AND of the second group, the output of the 1st (1 2, ..., p) of the element OR is connected to the counting input of the (1-1) th counter, the overflow output of which is connected to the write enable input of the 1st group memory block and the 1st trigger information input, the j-ro forward and inverse outputs of the flip-flop are connected to the second inputs of the j-ro element of the first and second groups respectively, the read control input of the j-ro memory block These groups are connected to the output of the j-ro element AND of the first group, the first, (2j + 1) -th and () -th outputs of the j-ro memory block g groups are connected respectively to the first, second inputs of the j-ro adder and the first input of the j-ro multiplication unit, the second input of which is connected to the output of the j-ro adder, the output of the t-th (t 1, ... n + 1) accumulates adder is the mth autocorrelator output, characterized in that, in order to improve accuracy, a second pulse driver is added to it, n + 1 registers of the first group, n + 1 additional counters, n + 1 blocks subtracting, n + 1 registers of the second group and n + 1 delay elements, with the output of the pulse generator connected to the counting one the input of the first additional counter, the resolution of the recording entry of the register of the first group, through the first delay element - with the synchronous input of the first accumulating adder, and through the second pulse generator - with the first input of the 2k-ro element And the first group, the output of the j-ro element And the first group is connected to counting input (j + 1) -ro of an additional counter, recording enable input (j + 1) 9161 the first register of the first group and qepeaf (j + 1) -H delay element - to the sync input (j + 1) -ro accumulating adder, the output of the nth accumulating adder is connected to the input of the deductible rth subtraction unit, the input of which is decremented is connected with the output of the t-th multiplication unit, and the output with the information input of the t-th register of the first group, the shift input of which is connected to the shift input of the t-th 710 the second group of registers, the enable input of the initial setting of the t-th additional counter and the overflow output of the t-th additional counter, the input of which the initial state is connected to the output of the t-th register of the second group, the information input of the th accumulating adder is connected to the output of the t-th register of the first group. "XW “H / U to (1) Кж101