SU1707566A1 - Digital meter - Google Patents

Abstract

The invention can be used to measure the average phase shift between signals of known frequency. The goal is to increase speed. The phase meter contains shapers 1 t; 2, the element OR 3, the elements AND k and 5, the reversible counter 6, the element NOT 1t triggers 8 and 10, the switch 9, the element 11 delay, the cumulative adder 12, the adder 13, RAM 1, the estimator 15 address, bus 16 set the accumulation interval , block 17 ELKS..ov :: output tires 18. 2 Il.

Description

The invention relates to a measurement technique and can be used to measure the average value of the phase shift between two harmonic oscillations of a known frequency.

The purpose of the invention is to increase the speed while maintaining measurement accuracy.

FIG. 1 shows a block diagram of a digital phase meter; in fig. 2 - time diagrams of his work.

The digital phase meter contains the first 1 and second 2 drivers, the inputs of which are the input buses of the device, the element OR 3, the first C and the second 5 elements whose POWER INPUTS are connected respectively to the inputs of the forward and reverse accounts of the reversing counter 6, and the first inputs are connected with the output of the element NOT 7, the input

which is connected to the output of the first shaper 1 and C-input. the first D-flip-flop 8, the second inputs of the elements And C and 5 are connected respectively to the direct and inverse outputs of the first D-flip-flop 8, and the third inputs to the output of the second Shaper 2, R- and D-inputs of the first D-flip-flop 8, first the input of the switch 9 and the C-input of the second D-flip-flop 10, the D-input of which is connected to the unit voltage bus, the R-input to the output of the delay element 11 and the first input of the element OR 3 | and the direct and inverse outputs of the second P-flip-flop 10 are connected respectively to the input of the delay element 11, strobe the input of the cumulative adder.) 12; the second input of the switch S, the third.: the fourth of which is connected to the bus of counting pulses and the fourth inputs of the elements And k and 5, and the input of the control V.

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with the control signal bus, the reset input of the accumulative adder 12 and the second input of the OR element 3 whose output is connected to the reset input of the reversing counter 6, the outputs of which are connected to the corresponding inputs of the adder 13 and the information inputs of the random access memory (RAM) 14, the control input of which connected to the second output of the switch 9, the first output of which is connected to the C input of the address counter 15, whose parallel write outputs are connected to the accumulation interval setting bus 16, the transfer output of the connection with its own control input, and the outputs of the address counter 15 are connected to the address inputs of RAM 1, the outputs of which are connected to a group of 17 NOT elements, the outputs of which are connected to the corresponding inputs of the adder 13f, the transfer input P of which is connected to the unit voltage bus, and the outputs the inputs of the cumulative adder 12, the outputs of which are connected to the output bus device 18 "

Digital phase meter works as follows.

The device is reset to the initial state by a single impulse on the control wheel, the duration of which for complete zeroing of RAM I must exceed the cycle of operation of the address counter 15 when the counting pulses are fed to its C input. In this case, the unit level on the control bus through the element OR 3 has wrapped the reversible counter 6, the a-counter 15 addresses reads the counting pulses passed to its C-input by the switch 9, taking all values from 0 to N, resulting in RAM I through zeros are written to all addresses from 0 to N. The switch 9 with a single level at its control input transmits counting pulses from the third and fourth inputs to both outputs, and with a zero level - information from the first input to the first output, and from the second input to the second output. To the inputs of the parallel recording of the counter 15 of the address, the sneaker N is fed to the accumulator interval setting bus 16,, el. m; from about. jwpcmir, y; those that are responsible for the formation of the average phase shift. The N code is installed on the inter 16 bus.

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the accumulator shaft before resetting the phase meter.

At the end of a single pulse v on the control bus, the phase meter goes into operating mode. At this time, the C-input of the counter of address 15 comes through the switch 9, the pulses from the output of the second driver 2, and to the control input of the RAM I - the pulses from the output of the second D-flip-flop 10. The second D-flip-flop 10 on the back edges of the pulses of the second driver 2 generates pulses whose duration is equal to the delay time of the delay element 11, since by a single level from the output of the delay element 11 the second D-flip-flop 1Q is set to the zero state at the R input.

A reversible counter 6 serves to determine the phase shift between two input harmonic oscillations 1G, | and Ig (cm0 fmg. 2) with respect to U4. Elements t and 5 pass counting pulses when the output of the first shaper 1 (hm. Fig. 2a) is the zero level (the output of the element is NOT 7 unit level), and at the output of the second shaper 2 - the RDY level. In the case when U2 is ahead of U, the first D-flip-flop 8 is set to a single state (see Fig. 2d) on the falling edge of the pulse of the first shaper 1, and the counting pulses pass through the first element And (see Fig 2d) n -e input of the direct counting of the reversible counter 6. Upon completion of a single pulse at the output of the second imaging unit 2 (see Fig. 26), the first D-flip-flop 8 is set at the R input to the zero initial state. In the case of t, when 11 lags behind U., the first D-flip-flop 8 (see FIG. 2c) is not set to one at the trailing edge of the pulse of the first shaper 1, remains in the zero state, and with the appearance of a single level at the output the second forma- tion / 2 counting pulses pass through the second element I 5 (see Fig. 2e) to the input of the counting counter of the reversible counter 6. Thus; the reversible counter 6 performs a direct counting of the counting pulses at the advance of the signal Lg and a reverse counting (reversible) when the signal Ua lags behind the signal U. After the end of the pulse of the second driver 2, the time is equal to the delay time of the And delay element (see Fig. 2k), a single pulse from the output of the delay element 11 through the OR element 3 (c. Fig. 2l) reversing counter 6 at the R input is set to the initial zero state.

The address counter 15 operates as follows. While at its transfer P output is a unit level, the address counter 15 performs a reversal count of pulses arriving at C-input0 When the transfer output is set at G and the associated address of the control of the counter, 15 the level is carried out parallel recording of the N code by the first positive voltage drop at the C input of the address counter 15. Consequently, the address counter 15 alternately iterates through all the code combinations from the N code to the 0 code. When the phase meter is reset, the address counter 15 is operated by counting pulses, and in the operating mode by the second driver 2 o

The operating mode of the digital phase meter can be divided into two stages: the first is the accumulation of (N + 1) -ro measurements of the phase shift, the second is the subsequent accumulation with processing „

At the first stage, it is time for each

the pulse of the second Shaper 2 determines the phase shift between U, and Ul. RAM 1 is in read mode, since its control descent has a single level due to a single level at the inverse output of the second T) -trigger 10, and hence the second output of the switch 9. First N + 1 clocks from RAM I1 will be read zeros that were written to all memory cells of RAM 1C from 0 to N-th when resetting the phase meter to the initial state Zero levels from the output of RAM AND are converted by a group of 17 elements NOT to single ones. The addition of units from the transfer input P in the adder 13 will give zero result. Consequently, the N-H cycle at the output of the adder 13 will be present without processing the codes of the Oal co-section count counted by the counter 6. At the end of the pulses of the second driver 2, the second D-flip-flop 10 and the

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At the moment 11, the top-ends form a zero pulse at the inverse output of the D-flip-flop 10 (see FIG. 2i) and, at its end, a single pulse at the output of the delay element 11. By the negative voltage drop at the inverse output of the P-trigger 10 in accumulator 12, the accumulated sum of the accumulated sum is fixed, taking into account the current measurement of the phase shift present at the output of the 13o Zero level, passing from the inverse output of the second D-trigger 10 through the switch 9 (see Fig. 2g, h) A recording of the current phase shift measurement is taken at the RAM control input to the RAM 14. After the zero pulse is terminated at the inverse output of the second D-flip-flop 10, a single pulse is output from the element 11 Support will go through the element OR 3 and reset the reversing counter 60 on the R input. Thus, after the (N + 1) -ro pulse from the output of the second driver 2 in RAM 1, at all addresses specified by the address counter 15, N will be written sequentially “-1 the results of the phase shift measurements, and in the cumulative adder 12, all these GL-1 - phase shift measurements are summed up.

The appearance of the next () -ro pulse at the output of the second driver 2 will cause the output of the counter 15 to address the address at which the output of RAM 1 (the result of the first phase shift is shown. Next, the code of the first measurement result is converted into an additional code by inverting of the first measurement code and the addition of the unit to it through the ESCROW of the transfer transfer P of adder 13, i.e., adder 13 calculates the difference (N + 2) -ro; and the first shift q q30ooro. The result of the subtraction goes to cumulative adder 12, where it is algebraically summed with the previously accumulated sum of N measurements. The impulse at the output of the delay element 11 writes the result (N + 2) -ro of the phase shift measurement to the RAM 1 at the perugo measurement address. Next, the device operates in the same way., Kg times from the RAM at the address assigned to the address counter 15, the information (jNl) -ro of the measurement of the phase shift is read and subtracted from the current j-ro measurement. The difference obtained is algebraically summed with the sum of the previous N last measurements, and then at the same address in RAM 14 instead of rezul Measure (j-N-l) -ro measurement records the j-ro result of the current phase shift measurement. Thus, the oldest of all measurements is always subtracted from the sum of the N + 1 measurements and a new current phase shift measurement is added. In accumulative adder 12, there is always a sum of N4-1 measurements. Therefore, if we divide the summation result stored in accumulative adder 12 by the number N + 1, then we obtain the average value of the phase shift between the signals 1 and U on the averaging interval (H – H) T, where T is the follow-up period of the signals U and U Since the change in the average value of the phase shift at the output of the cumulative adder 12 is performed at a time equal to T, and in the prototype at a time equal to (N + 1) .T, it follows that in the proposed device for a given accuracy of calculation NN times while maintaining accuracy measurements ,,

Claims (1)

Invention Formula A digital phase meter containing the first and second drivers, the inputs of which are the device input buses, the OR element, two triggers, the first and second AND elements, the outputs of which are connected respectively to the forward and reverse accounts of the reversible counter, and the first input connected to the generator terminal counting pulses, characterized by the fact that, in order to improve speed, they introduced the element NOT, the switch, the delay element, the cumulative adder, the adder, the random access memory, 0 0 five 0 5 0 the address counter and the group of elements are NOT, while the triggers are designed as D-flip-flops, the input of the element is NOT connected to the output of the first driver and the C-input of the first D-flip-flop, and the output is connected to the second inputs of the And elements, the third inputs of which are connected respectively to the pr my and inverse outputs of the first D-flip-flop, and the fourth inputs - with the output of the second shaper, R- and D-inputs of the first D-flip-flop, the first input of the switch and the C-input of the second D-flip-flop, the D-input of which is connected to a single bus, R input - to the output of the delay element and the first input OR, and the direct and inverse outputs of the second D-flip-flop are connected respectively to the input of the delay element and the gate input of the cumulative adder connected to the second input of the switch, the third and fourth inputs of which are connected to the first inputs of the AND elements, and the control input to the control bus and the second input of the OR element, the output of which is connected to the reset input of the reverse counter, the outputs of which are connected to the corresponding inputs of the adder and information inputs of the RAM, the control input of which is connected the second output of the switch, the control input of which is connected to the reset input of the cumulative adder, and the first output is connected to the C input of the address counter, the parallel write inputs of which are connected to the accumulation interval setting bus, the transfer output is connected to its own control input, and the outputs of the address counter are connected with the address inputs of the RAM, whose outputs are connected to the upper group of the elements NOT, the outputs of which are connected to the corresponding inputs of the adder, the transfer input of which is connected to the unit bus, and you stroke - to the corresponding inputs of the cumulative adder, the outputs of which are connected to the output bus of the device. VI ------ l ЖЛШШВШ -1 ГТ .... 3 .liillllllilHIIIISllliilllillll - U