SU1499375A1 - Device for estimating the amplitude of narrow-band random process - Google Patents

Abstract

The device provides an increase in the accuracy of the amplitude estimate with a high level of noise and a small correlation interval for high-frequency signals. For the process under study, a comparator estimates the sign function, which is delayed by the shift register, and the delayed value is used to generate an estimate of the sign correlation function and control the reversible counters, the inputs of which are fed by the pulse value of the absolute value of the input signal generated by the converter. The resulting evaluation codes are used to control the pulse-frequency divider division factors, which divide the number of pulses corresponding to the square of the half-period correlation coefficient estimate value by a half period, by this function estimates for the delay of the sign function by the period and by the sine modulus value of the sign correlate function formed by a constant memory element. The device contains a comparator 1, a zero-potential bus 2, information input 3 of the device, an inverter 4, a switch 5, first and second elements 6, 7, analog-digital converter 8, trigger 9, accumulator 10, counter 11, register 12, additional register 13, shift register 14, EQUITY 15, element 2И-OR 16, fixed memory blocks 17 and 18, dividing blocks 19 and 20, third AND 21 element, frequency multiplier 22, frequency divider 23, additional adder 24, input 25 start clock frequency shaper 26 pulses. 1 il.

Description

 . 1 / (99 by the shift register, and the delayed value is used to form the valuation of the sign correlation function and control the reversal counters, to the inputs of which a number of impulse absolute value codes of the input signal generated by the transducer are applied. The resulting evaluation codes are used to control the coefficients dividing the frequency dividers of pulses that provide a division of the number of pulses, corresponding to the earl square of the value of estimating the half-sign correlation coefficient d11 delay by half the period , for evaluating this function to delay the sign function for the period and for the value of the sine modulus of estimating the sign correlation function formed by the constant memory element. The device contains a comparator 1, a bus 2 of zero potential, an information input 3 of the device, an inverter 4 , switch 5, first and second elements Pi 6, And 7, analog-to-digital converter 8, trigger 9, accumulating adder 10, counter 11, register 12, additional register 13, shift register 1A, element DIFFERENTIAL 15, element 2I- ШШ 16, blocks 17 and 18 permanent memory , Blocks 19 and 20 dividing the third AND gate 21, a multiplier 22, frequency divider 23 frequency, the additional adder 24, the start input 25 of the clock frequency generator 26 pulses 1 yl.

The invention relates to devices for evaluating the characteristics of narrow-band random processes in the presence of noise and shunov and can be used in computer systems

ki and control devices.

The aim of the invention is to improve the accuracy of the device for estimating the amplitude of a narrowband random

process.

The drawing shows a block diagram of a device for estimating the amplitude of a narrowband random process.

A device for estimating the amplitude of a narrowband random process contains a comparator 1, a width 2 of zero potential and information input 3 of the device, which is connected directly and through inverter 4 to the information inputs of the switch 5, the first 6 and the second 7 elements AND, analog-to-digital converter 8 trigger 9, accumulating adder 10 counter 11 and register 12, whose information inputs are connected from the output of meter 11, whose counting input is connected to the output of the first element I 6, the first input of the second element I 7 is connected to direct trigger output .9, supplementary register 13 shift register 14, EQUITY 15 element, element 16, first fixed memory block 17, in which the sine modulus function is recorded, second fixed memory block 18, in which the erection function is recorded

in the square, the first block 19 and the second block 20 division, the third element And 21 frequency multiplier 22 and frequency divider 23, an additional accumulating adder 24, the outputs of which are with the inputs of the first permanent memory block 17, the outputs of which are connected to the inputs of the divider of the first block 19 division, the inputs of the dividend which are connected to the outputs of the second block 18 of the permanent memory, the inputs of which are connected to the outputs of the accumulating adder 10, the information inputs of which are connected to the outputs of the analog-digital converter 8, which are connected to ormatsionnymi additional inputs of the accumulator 24.

The outputs of the adder 24 are connected to the inputs of the divisible second dividing unit 20, the outputs and inputs of the divider are connected respectively to the inputs of the auxiliary register 13 and the outputs of the block 19. The clock input 25 is connected to the input of the frequency multiplier 22, the output of which is connected to the clock input of the analog-digital converter 8, the counting input of the trigger 9, whose direct output is connected to the first input of the first element 6, the clock inputs of the shift register 14 and the frequency divider 23, as well as the first input of the first group of inputs A 2I-OR 16 and the first inverse input of the second group of inputs on AND element 2I-OR 16, the output of which is connected

with the control input of the analog switch 5. The second inputs of the first and second groups of inputs of AND element 2I-IPA 16 are connected respectively to the first and second inverse outputs of the shift register 14, the information input of which is connected to the output of comparator 1 and the first input of UNIFORM 15, output and the second input of which is connected respectively to the second input of the first element AND 6 and the second inverse output of the shift register 14.

The output of the analog switch 5 is connected to the analog-digital input

|: U (t;) Sgn A

h rJlL, „,

„(Tf) Sgn U (t, -T) U Z.U (ti) Sign U (t; - T)

V -e.i 1

where U (t |) is the INPUT signal in

time ment T; T 1 / fg is the period corresponding to the central clock of the narrow-band random process; C - normalized (s factor, which depends on the selected dimension and the number of samples per period.

The device works as follows.

The signal characterizing the process under study is fed to the input 3 of the DEVICE. Comparator 1 generates a logical signal characterizing the sign function of the input signal. A clock signal is fed to the input 25 of the device, which ensures the start of frequency multiplier 22, which at its output generates a signal with a frequency ff that is N times the central frequency of the narrowband random process under study. The indicated signal with frequency f is delivered to the counting trigger 9, at the output of which the frequency of the pulses is equal to ff / 2. These pulses provide the shift of the values of the sign function in the shift register 14 so that at the inverse of this shift register the value of the sign function with | {hold by the period value is formed. Blessings

Converter 8, the output of frequency multiplier 22 is connected to the second input of the second element And 7 and the first Pokhod I of the third element And 21, the second input of which is connected to the inverse output of the trigger 9, the outputs of the second 7 and third 21 elements And connected to the clock inputs of the cumulative adder 10 and additional cumulative adder 24. The device also contains a driver 26 pulses,

I

In the case of the amplitude estimate can be obtained using the ratio

When inversion is performed, the EQUIDITY element 15 provides the formation of a coincidence function of sign functions, which at the time of arrival of clock pulses at the input of element 6 controls the count of counter 11, in which the estimate of the sign autocorrelation function G is formed, (T), which after completion of the formation is rewritten in register 12,

From the outputs of register 12, the evaluation code G (T) enters the permanent memory block 17, which ensures the generation of a code proportional to (sin GxCT) /. The signal under study also arrives at the switch 5, at the output of which the products of the signal under study are formed by the values of clock functions with delays by half the period T and period T, which are sequentially converted by analog-digital converter 8 and accumulated respectively in the adder 10 and the adder 24, where - to worldkgs estimates of the semi-autot correlation function R and R (t)

respectively. Evaluation

"(one

enters the block 18, which forms the code, the square of this value. Blocks 19 and 20. divisions provide the formation of a normalized estimate in accordance

 with the indicated ratio, the output code proportional to the amplitude of the spinning random number was written to the output register 13 by the pulse from the shape output, and the pulse is generated by 26 pulses, which is triggered by the formation ends corresponding estimates, providing a record in the register 12 and resetting the counter 11 and adders 10 and 2A.

Since the estimate is formed with rationing by R (T), it provides for the elimination of the effect of a time decrease in the autocorrelation function (a decrease in the exponential law is assumed)

R2

fJ- HZfel

(fr)

Since an estimate is formed for a function shifted in time (sign function, the effect of additive noise. Reduced, and rationing, according to ISin G (T) /, provides an exception to the influence of noise on the measurement results, on the amplitude estimate, the scoring is provided in accordance with the hCST-r (|) and taking into account (1) and yl o)

R.

R

sin

STU /

Thus, the bias of the amplitude estimate, which is associated with the effect of random noise, is eliminated, which ensures an increase in the accuracy and noise immunity,

Claims (1)

Invention Formula Device for estimating amgoshtuda of the echolopic random process, containing a trigger, the direct output of which is connected to the first input of the first element And, the output of which is connected to the counting input of the counter, the output of which is connected to information o five 0 five Q five 0 five 0 five to the register input, the forward trigger output is connected to the first input of the second element, And the pulse shaper, the output of which is connected to the clock input of the additional register, the comparator, the input of which is connected directly and through the inverter to the information inputs. The switch is the information input of the device, an analog-to-digital converter that accumulates the adder, characterized in that, in order to improve accuracy, the device contains a shift register, the EQUALITY element, the element 2И-OR, two blocks of permanent memory, two division blocks , the third element And, additional accumulating adder, multiplier and frequency divider, the output of which is connected to the input of the pulse shaper, with the installation input in O of the counter, accumulating adder, additional accumulating totalizer a, and the register, the output of which is connected to the address input of the first block of permanent memory, the unscramble of which is connected to the input of the divider of the first division block, the input of the dividend which is connected to the output of the second block of permanent memory, the address of which is connected to the output of the accumulating adder, the information input of which is combined with the information input of the additional accumulating adder and connected to the output of the analog-digital converter, the output of the additional accumulating adder is connected to the input of the cases The second divider unit, whose output and divider input are connected respectively to the input of an additional register and the first divider unit, the output of the frequency multiplier is connected to the clock input of the analog-digital converter, to: the trigger input, the forward output of which is co. one with the clock inputs of the shift register, and a frequency divider, with the first direct and inverse inputs of element 2И-ИПИ, the output of which is connected to the control input of the switch, the second inputs of element 2И-Ш1И are connected respectively with the inverse and direct outputs of the shift register, information the input of which is combined with the first input of the EQUAL ELEMENT element and connected to the output of the comparator1494 .4 torus, the output and the second input of the EQUALITY element are connected respectively to the second strokes of the first element And to the inverse output of the shift register, the switch output is connected to the information input of the analog-digital converter, the inverse output of the trigger is connected to the first input of the third And element, the second JQ AND) whose output is combined with the third input of the second element AND and connected to the output of the multiplier part, the outputs of the second and third elements AND are connected respectively to the clock and additional accumulating adders, the input of the frequency multiplier is the input of the device clock frequency.