SU1370643A2 - Time scale correction device - Google Patents

Abstract

The invention relates to a pulse technique and can be used in snc systems to correct the time scale. The purpose of the invention — extending the functionality — is achieved by introducing a correction of the time scales within the tolerance. For this, a memory block 14, three elements OR 13, 17 and 18, a delay element 16 and additional pulse shaper 15, a converter of 12 codes and command buses are added to the device. In addition, the device contains a generator 1, a phase shifter 2, a divider 3 frequencies, reversible counters 4 and 8, shift register 5, correction code converter 6, element 7, decoder 9, shaper 10 single pulses, shaper 11 of control signals. The device makes it possible to shorten the time correction process. 5 il. S (l

Description

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The invention relates to a pulse technique and can be used in synchronization systems for correcting the time scale.

The purpose of the invention is to expand the functionality by allowing the introduction of a time scale correction within the tolerance limits.

FIG. 1 is a functional block diagram of the device for correcting the timescale in FIG. 2 and 3 are time diagrams for his work; FIG 4 is a functional correction code converter circuit; in fig. 5 - time diagrams that show his work.

The device for correcting the time scale contains a series-connected generator 1, a phase-shifting unit 2 and a divider 3 frequencies as well as a reversible counter 4, a shift register 5, a correction code converter 6, element 7, counters 8, a decoder 9, a driver 10 single pulses, the control signal generator 11, the code converter 12, the OR element 13, the memory block 14, the pulse driver 15, the delay element 16 and the OR elements 17 and 18. The information and clock outputs of the converter 6 are connected respectively to the information and the clock The new inputs of the shift register 5, the output of the lower bit of which is connected to the first control input of the phase-shifting unit 2, and the outputs of the higher bits are connected to the recording inputs of the reversible counter 4. The input of the converter 6 is connected to the bus Correction code. The clock output of the converter 6 is connected to the counting input of the counter 8, the installation input of which is connected to the output of the element OR 17. The discharge outputs of the counter 8 are connected to the corresponding inputs of the decoder 9, the output of which through the element OR 18 is connected to the first input of the ramper 10. The second input of the rapper 10 connected to the first input element And 7, the output of the phase-shifting unit 2. The output of the element And 7 is connected to the counting input of the reversible counter 4, the output of which is connected to the first input of the imaging unit 11. The second input of the formate 11 is connected to the pre-recording input of the reversible counter 4 and with the output of the imaging device 10. The output of the imaging device 11 is connected to the second input of the AND 7 element and the second control input of the phase-shifting unit 2. The first input of the OR 17 element is connected to the Bus Correction input. The inputs of the code converter 12 are connected to the inputs of the element OR 13 and to the command shelters Correction 1 and Correction L. The outputs of the converter 12 code are connected to the inputs of the memory block 14,

5 outputs of which are connected to the inputs of the register 5 shift. The output of the OR element 13 is connected to another input of the OR element 17, the input of the delay element 16 and the input of the form-shifter 15, the output of which is connected to the preliminary recording input of the shift register 5. The output of the delay element 16 is connected to another input of the OR element 18.

5 Converter 6 code correction (Fig. 4) contains a trigger 19, the element OR 20 and the element 21 of the delay. In this case, the trigger inputs 19 are connected to the inputs of the OR element 20 and are connected to the input of the transducer 6. The trigger output 19 is the information output of the converter 6. The output of the OR element 20 is connected to the input of the delay element 21, the output of which is the clock output of the converter 6.

The device for the correction of the time scale works as follows.

The generator 1 is a source of pulses with a repetition period Tr (Fig. 2g) to start the phase-shifting unit 2, which is executed as a frequency divider with a variable division factor of In the initial state, the division factor is equal to K, which is determined by the presence on the second control input the phase-shifting unit 2 of the signal O (Fig. 2e) regardless of the signal at the first control input. From the output of the phase-shifting unit 2, pulses are applied to frequency divider 3 (Fig. 2h).

The device operates in two modes: correction of the time scale by the value determined by the introduced correction code; correction of the time scale by one of the fixed values stored in the memory block 14.

The first mode is realized in those cases when it is necessary to accurately store the stored and reference time scales. The second mode is used when the discrepancy between the stored and reference time scales significantly exceeds the correction range and it is necessary to quickly remove this discrepancy, or when it is necessary to maintain the discrepancy between the time scales within the specified limits. In this case, the value of permissible divergence with the corresponding sign is stored in memory block 14. When the stored time scale is out of tolerance, correction is made to the tolerance value without entering a correction code into the device.

In the first mode, the device operates as follows.

The correction input is sent to the bus (Fig. 2a), which passes through the OR input element to the installation input of the counter 8 "At that, the counter 8 is reset and the output of the decoder 9 shows the level O, which causes the appearance of O at the first input of the driver 10 (Fig. 2c).

On the bus The correction code is supplied by the number N with the sign in the form of an n-bit sequential binary code by the leading bits along two lines of communication in the form of a forward and inverse code. At that, the code units correspond to the presence of a pulse on the communication line of the direct code and the absence of a pulse on the communication line of the inverse code, and to zero of the code - the absence of a pulse on the communication line of the direct code and the presence of a pulse on the inverse code line. The low-order code contains information about the sign of the correction.

The pulses along the direct and inverse code lines are fed to the S and R inputs of the trigger 19 and to the inputs of the OR element 20 of the converter 6 (Fig. 5a, b). At the output of the trigger 19, a direct correction code is formed (FIG. 5c), with the duration of the code pulses extended to a period

the information input of the converter 6 bits of the direct correction code are alternately fed to the information input of the shift register 5, to the clock input of which pulses are fed from the clock output of the converter 6. At the same time, the delay of these pulses relative to the code pulses ensures reliable recording of information into the register 5 shift The forward correction code (number N) is written to shift register 5. At the same time, counter 8 counts the number of pulses, i.e. the number of code bits written to register 5. As soon as all n bits of code are written to register 5, the level 1 appears at decoder 9, which through OR 18 element is fed to the first input of formatter 10 (FIG. 2c). Shaper 10 selects from the clock pulse train (Fig. 2h), arriving at its second input, the second pulse (Fig. 2d) after appearance 1 at the first input. This pulse (Fig. 2 is fed to the second input of the imaging unit 11 and to the input of the preliminary recording of the reversible counter 4. In this case, the information is copied from the higher (n-1) rows of the shift register 5 to the reversible counter 4 on the front of the pulse. A reversible counter 4 of a number other than zero (N 0), level 1 appears at its output (Fig. 2e), which arriving at the first input of the form 11, allows the control signal to be generated at its output. level 1 p is at the output of shaper 1 by slice of the pulse at the output The frame 10 (Fig. 2e). The control signal is fed to the second control 1 st input of the phase-shifting unit 2 and changes its division factor by kll (fig 2z) depending on the sign coming to the first control; the output of the low bit of the shift register 5. At the same time, the control signal opens the element And 7, The pulses from the output of the phase-shifting unit 2 begin to pass to the input of the reversal counter

repetition of pulses of a clock series, which is formed at the output of the element OR 20 (Fig. 5d). Tacho pulses 5 j (Fig. 2i). When the coefficient of the howling series through the element 21, the dividing delay k-1 is the first after the change

-shipped to the clock output of the converter, call-taker 6 (Fig. 2b, Fig. 5e). WITH

the division rate of the pulse at the output of the phase shifter unit 2

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the information input of the converter 6, the bits of the direct correction code are alternately fed to the information input of the shift register 5, to the clock input of which pulses are fed from the clock output of the converter 6. At the same time, the delay of the clock pulses relative to the code pulses ensures reliable recording of information into the shift register 5. The forward correction code (number N) is written to shift register 5. At the same time, the counter 8 counts the number of pulses of pulses, i.e. The number of code bits written to register 5. Once all the code bits are written to register 5, the output of decoder 9 is Level 1, which, via OR 18, is applied to the first input of Shaper 10 (Fig. 2c). The imaging unit 10 extracts from the clock pulse train (Fig. 2h), arriving at its second input, the second pulse (Fig. 2d) after appearance 1 at the first input. This pulse (Fig. 2d) is fed to the second input of the imaging unit 11 and to the pre-recording input of the reversible counter 4. At the same time, the information is copied from the upper (p-1) bits of the shift register 5 to the reversible counter at the front of the pulse. a counter 4 of a number other than zero (N 0), level 1 appears at its output (Fig. 2e), which, arriving at the first input of shaper 11, allows the formation of a control signal at its output. A control signal in the form of a level 1 appears at the output of the shaper 1 1 through a cut of the pulse at the exit of the shaper 10 (Fig. 2e). The control signal is fed to the second control of the 1st input of the phase-shifting unit 2 and changes its division factor by kll (Fig. 2h) depending on the sign of the incoming control to the first control; iy input from the low-order output of the 5 shift register. At the same time, the control signal opens the element AND 7, The pulses from the output of the phase-shifting unit 2 begin to pass to the input of the subtraction of the reversible counter 5 j (Fig. 2i). With a division factor of k-1, the first after the change

the division ratio of the pulse at the output of the phase-shifting unit 2

at time T earlier than with the initial division factor, the second one 2T earlier, and so on; on the contrary, with the division factor k + l, on the contrary, the pulses are delayed, i.e. The i-th pulse at the output of phase-shifting unit 2 appears at the time of Early or later, which leads to a shift in the time scale. As soon as the number N recorded in the reversible counter 4 is considered, the level O appears on the output of the latter (Fig. 2e), which returns the generator 11 to the initial state. At its output, a level O appears (Fig. 2e), and the initial division ratio of the phase-shifting unit 2 is restored (Fig. 2e and the And 7 element is closed (Fig. 2i). Correction value

-It ± NTr,

where N is the number recorded in (n-1) most significant bits of shift register 5;

T is the pulse repetition period of the generator 1.

In the second mode, the device operates as follows.

If the time scales differ by the amount exceeding the permissible discrepancy, one of the command buses Correction 1 - Correction L is given a command corresponding to the permissible discrepancy (for example, the Coerek G command corresponds to the permissible discrepancy + 100 ISS, Correction 2 - minus 100 ISS, Correction 3 - +1000 µs, etc.). The command arrives at the i-th input of the code 12 converter (Fig. 3k) At the outputs of the code 12 converter, the address of the memory cell of the memory block 14 is stored, in which the correction code corresponding to this command is stored. The address is fed to the inputs of the memory block 14, at the outputs of which a correction code is formed. At the same time, the command through the OR elements 13 and 17 is fed to the installation input of the counter 8. At the same time, the counter 8 is reset, and O, which causes the appearance of the output of the OR element 18, appears at the output of the decoder 9 (figs Sv. Team Cher Without the element OR.13 (fig.Za

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is fed to the input of the imaging unit 15, at the output of which a pulse is formed (Fig. 3L). This pulse is fed to the input of the pre-recording register 5 shift. In this case, the correction code from the memory block 14 is written to the shift register 5. Command through the element OR 13, element 16

10 delay (Fig. 3m) and the OR element 17 is fed to the first input of the driver 10. The delay value of the delay element 16 must be greater than the response time of the driver 15

15 and more than the sum of the reset time of the counter 8, the delay of the decoder 9 and the element OR 18, and the preparation time for the operation of the former 10. The former 10 extracts the second 2Q pulse (Fig. 3g) from the clock series (Fig. 3h) at the second input after the occurrence 1 at the first entrance. Further, the device works in the same way as in the first mode (Fig. 2d-i).

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Claims (1)

Invention Formula A device for correcting the time scale by avtoSv. No. 1095431, in order to expand its functionality, a memory block, three OR elements, a delay element, and an additional pulse driver, a code converter, and command buses that are connected to the inputs of the first OR element and additional inputs are introduced into it. code converter whose outputs 4Q are connected to the address inputs of the memory unit, the outputs of which are connected to the write inputs of the shift register, the preliminary recording input of which is connected to the output of the additional g pulse generator, the input of which is connected to the output of the first OR element, the first input of the second OR element and through the delay element the first entry of the third element 35 that OR, the second input of which is connected to the output of the decoder, and the output of the third element OR is connected to the input of the single pulse generator, while the bus Correction input is connected to the second input of the second element OR, the output of which is connected to the installation input of the counter. I if ynnnnnn, jinnnnnnniinnnnnnnn ,, flnnnnnnnnnnnnnnnnj  -r T-., I. H- I. ir T-, 3D . and -1h m ch .. ch (. 2 nn fie.Z FIG. FIG. five