SU1185307A1 - Device for correcting time scale - Google Patents

Abstract

A DEVICE FOR THE CORRECTION OF THE SCALE OF TIME containing a generator, a time keeper, a shift register, a matching circuit, the first input of each of which is connected to the corresponding output of the shift register bit except for the first and last bits, a counter and two additional matching schemes, the first of which Connected to the input of the counter, characterized in that, in order to increase accuracy and speed, a frequency divider and two control signals are inserted into it, the generator output being an hour divider Ody connected to the input of the time store, the first input of the first additional matching circuit and clock inputs of two control signal drivers, the first control input of the frequency divider is connected to the output of the first digit of the shift register, the output of the last bit of which is connected to the control input of the second driver, signals, the first output connected to the second inputs of the coincidence circuit, the outputs of which are connected to the corresponding inputs of the installation of the bits of the counter, the second output of the second form The control signal generator is connected to the second input of the first additional matching circuit, the third one (L stroke to the first input of the second additional matching circuit, the second input connected to the counter output and the third input of the first additional matching circuit, the output of the second additional matching circuit is connected to the second control input of the frequency generator, the control input of the first driver of the control signals is connected to the command bus, and the output is connected to the input of the shift register bits, turn is connected to the input bus time-scale correction code.

Description

The device relates to radio engineering and can be used in the construction of a synchronization device and time keepers of autonomous devices. The purpose of the invention is to improve the accuracy and speed of the correction of the time scale. FIG. 1 shows a block diagram of the proposed device; in Fig.2 - time diagrams of his work; in fig. 3 - control signal driver circuit; in FIG. A are time diagrams of their work. “. The device for correcting the time scale consists of the generator 1, the output of which is connected to the input of the frequency divider 2, the time storage 3, the first additional matching circuit 4, the counter 5, the matching circuit 6-15, the shift register 16 and the two control drivers 17 and 18 signals, the output of the frequency divider 2 is connected to the first input of the first additional i matching circuit 4 and the tact inputs of the control signal drivers 17 and 18, the output of the first bit of the shift register 16 is connected to the first control input of the frequency divider 2, the second the control input of which is connected to the output of the second auxiliary matching circuit 19, the output of the last bit of the shift register 16 is connected to the control input of the control signal generator 18, the first output of which is connected to the second inputs of the matching circuit 6-15, the second output - to the second the input of the first additional circuit 4 coincidence; the third output with the first input of the second additional circuit 19; the second input of the second additional circuit 19 coincides with the output of the counter 5 and the third input of the first additional circuit. There are 4 matches, the output of which is connected to the input of counter 5, the control input of the control signal generator 17 is connected to the command bus, and the output is connected to the input of the bits of the shift register 16 whose input is connected to the correction code input bus. The driver 17 (18) of the control signals comprises a trigger 20, a coincidence circuit 21 and a trigger 22. moreover, the counting I input of the first trigger 20 and the first input of the coincidence circuit 21. connected to the clock input of the control signal generator, inputs of the trigger setter 20 and 22 and the second input of the coincidence circuit with the control input of the control signal generator 17 (18), the J and K inputs of the first trigger 20 are interconnected and connected to the inverse the output of the second trigger 22 and the third input of the matching circuit 21; the direct output of the first trigger 20 is connected to the fourth input of the circuit 21. the coincidence, the output of which is connected to the counting input of the second trigger 22 and is the first output of the control signal generator 17, the inverse output of the first trigger 20 is connected to the second output of the control signal generator 18, the direct output of the second trigger 22 is connected to the third output of the control signal generator 18 signals. The device for the correction of time scales works as follows. Generator 1 is a source of stable frequency pulses (Fig. 2a) for triggering frequency divider 2, the division ratio of which in the initial state is equal to K, which is determined by the presence of a control at the second input. From the output of the divider 2 frequencies, pulses are fed to the input of the guard 3 times (Fig. 2b). The time saver 3 performs de-pulse frequency repetition, arriving at its input, outputting intermediate-frequency pulses to consumers, forming an autonomous time scale. To correct the time scale, the Correction command is sent to the device's command input (Fig. 2c). By this command, arriving at the control input of the driver 17 of the control signals, is separated from the clock series of pulses arriving at the clock input of the driver 17, the second pulse after the arrival of the command (Fig. 2d). This pulse is applied to the input of the setting of the shift register 16, with 1 being written to the first bit of the 16-shift register, and the rest of the register, 0 zeros. The signal O from the output of the last bit of the shift register 16 (Fig. 2e) is fed to the control input of the control signal generator 18, while at the third output the last

o appears (fig. 2h), confirming the presence of o at the output of the circuit; we match 19 (fig. 2k). After that, an N-bit sequential correction code is written over the bus code input, which is given by the leading bits ahead, and the low-order code contains information about the sign of the correction. Shift register 16 contains (N + 1) bit. As the code bits are written into shift register 16 from 1 of the first bit, register 16 moves to the last bit. As soon as all N bits of the correction code are recorded in the shift register 16, the last (N + 1) -M bit of the register 16 is 1 (Fig. 2n), which is fed to the control input of the control signal generator 18. On the decline of the first clock pulse after the occurrence of 1, the level O appears at the control input of the driver 18 of the control signals at its second output (Fig. 2g). This signal is fed to the second input of circuit 4, and prohibits the passage of clock pulses from the first input of circuit 4 to input of counter 5. This is necessary because when writing the code from shift register 16 to counter 5, the last one appears at the output of the third input circuit 4 match to the end of the pulse frequency. In this case, due to the pulse decay, the counter 5 may be triggered even before the division factor 2 of the frequency divider divides, which can lead to a correction error.

On the first exit

18 controlling the signal; the second pulse after the appearance at the control input 1 of the clock frequency is highlighted (Fig. 2e). This impulse arrives at the second inputs of circuits 6-15, coinciding, allowing the passage of signals

from the outputs of the bits of the shift register 16 to the installation inputs of the counter 5; The correction value is written to the counter 5 in the reverse code. As soon as the correction value is recorded in the counter 5, the output of the last level 1 appears (Fig. 2i), which is fed to the second input of the circuit

19 matches and the third input of circuit 4 matches. By decay of the second after occurrence at the control input

74

1, a clock pulse at the second and third outputs of the driver 18, the control signals appears level 1 (Fig. 2g, h). This signal

From the second output of the driver 18, the control signals are fed to the second input of circuit 4 of coincidence, allowing the passage of clock pulses to the input of counter 5 (Fig. 2L).

The signal from the third output of the control signal generator 18 is fed to the first input of the coincidence circuit 19, permitting the change of the division factor of the divider 2 frequency to

(K + 1) depending on the sign

(Fig. 2a, b, k). FIG. Figure 2 shows the case of a correction when the coefficient of change of the division factor is changed by (K + 1). The sign of the correction is given from the exit of the first time.

row of the shift register 16 to the first control input of the splitter 2 frequency. Since the control signals at the second and third outputs of the driver control signals 18 are tied to

when the clock pulses fall, the possibility of distorting the correction value as a result of reducing the duration of the first pulse at the input of counter 5 is eliminated. Once in

the counter 5 in all the bits will have a level O at its output (Fig. 2i), which, entering the third input of the matching circuit 4 and the second input of the matching circuit 19, prohibits the passage of clock pulses to the input of the counter 5 (Fig. 2l) At the output of the coincidence circuit 19, O appears (FIG. 2k), and the initial division factor is set.

divider 2 frequency (Fig. 2a, b). Correction Amount & t + ptr

where T (, is the pulse repetition period

at the output of the generator 1; n is the number corresponding to the correction code.

In the proposed device, the maximum amount of correction that can be entered once is determined by the period of the pulses at the generator output and the size of the reversible counter, the shift register and the additional counter. Practically the maximum amount of correction that can be entered is not limited by anything, as the necessary correction value with a large care store

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be obtained by repeated repetition of the oscillator frequency, since

correction, while the magnitude of the core-controlled frequency divider realizes

The response is accumulated on digital elements, the instability of the correction in this device — the 5) delay rate of which neglect is determined only by the instability is small.

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Claims (1)

DEVICE FOR CORRECTION OF A TIME SCALE, containing a generator, a time keeper, a shift register, a matching circuit, the first input of each of which is connected to the corresponding output of the shift register except for the first and last bits, a counter and two additional matching circuits, the output of the first of which is connected to counter input, characterized in that, in order to improve accuracy and speed, a frequency divider and two shapers of control signals are introduced into it, and the generator output through a soy frequency divider is dined with the input of the time keeper, the first input of the first additional matching circuit and the clock inputs of the two shaper control signals, the first control input of the frequency divider is connected to the output of the first bit of the shift register, the output of the last bit of which is connected to the control input of the second shaper · control signals, the first the output connected to the second inputs of the matching circuits, the outputs of which are connected to the corresponding inputs of the setting bits of the counter, the second output of the second driver signal is connected to the second input of the first additional matching circuit, the third output is to the first input of the second additional matching circuit, the second input is connected to the counter output and the third input of the first additional matching circuit, the output of the second additional matching circuit is connected to the second control input of the divider frequency, the control input of the first driver of control signals is connected to the command bus, and the output is connected to the input of the setting bits of the shift register, the input of which is connected to the bus enter the timeline correction code.