SU518777A1 - Device for calculating standard deviation - Google Patents

Description

(54) A DEVICE FOR CALCULATING THE MEDIUM-SQUADRATIC OPENING of the corresponding outputs of the register of surrender, the outputs of the second and fourth triggers are connected to the corresponding inputs of the first element OR, the output of the third trigger is connected to one of the inputs of the second element OR, the other input of which is connected to the output of the separator; whose control input is connected to the input of the delay element. The drawing shows the proposed device. It contains shift register 1; combinational adder 2, counter-divider 3, counter Bbi6opKii 4, elements AND 5, 6, 7, elements OR 8, 9, 10, triggers 11, 12, 13, used as registers, generator 14 clock pulses, trigger 15, (-controllable) pulse generator 16 (the control allows or disrupts generation), delay 17, counter-divider 3 and select counter 4 can alter the coefficient for the amp & count to the same value of the required sample, in addition, counter-divider 3 reduces conversion factor to unity when issuing overflow pulse counter 4, Adder 2 ow It is combinational with several inputs: main, addition and subtraction. Such an adder can be dictated according to the truth table or it can be assembled from two one-digit adders to three inputs, in the second case the adder is simpler. The shifting register 1 can be performed as a register on MOS transistors, or as an ultrasonic delay line. By a shift cycle, we mean a complete single shift of the number written in the register, i.e. the number runs through all the register cells and assumes the initial state. By a shift stroke, we mean a shift of a number at a time in a row. It should be noted that the shift of a number occurs in lower bits of forward v (Ha drawing from left to right) continuously 4t through the adder and the And 5 element. At the same time, if the totalizer adds and subtracts no signals are given, the number in the shift register is saved. When the signal is sent, only in the lowest bit, the action is performed in the lower bit, and in the higher order the transfer is delayed by the delay element inside the adder. When applying to the main input and outputs of the AND (OR) subtraction of the numbers synchronized with the main one, the AND (OR) subtraction is performed in all digits, the transfer is formed and stored by the adder. Shifts 7 occur from the generator synchronized with the operation of the clock pulse generator 14 (the shift chains are not shown), and the latter is synchronized with the shift register. Shift register 1 is conventionally divided into three parts and has intermediate conclusions. The generator 14 generates pulses at the beginning and end of each part H and K, respectively, V, and during the clock cycles of each part (Roman numerals 1, I, W in the drawing in the field of generator 14) GW — clock pulse generator 14 is controlled by generator 16 { or from the outside). The device operates as follows. At the beginning of the conversion, all circuit elements are set to zero, except for counter-divider 3, which is set to one state. At the arrival of a series of measurement pulses, a measurement pulse simultaneously arrives. The pulse frequency is less than the frequency of the clock cycles by k times (k is the number of the shift register cells), t, e, the count pulses pass through the shift cycle, or in other words the jt pulses are synchronized with the operation of the circuit. The clock generator on the diagram is shown divided into two parts by the road, to clarify the operation of the circuit. The device has two modes of operation: data set and calculation, In the data set mode, generator A part 14 is working. When each pulse X arrives, the following occurs When the beginning of the first part of the shift register is found, a pulse is applied at the main input of the adder (output 1-14) through the OR element 11 to the addition input of the adder, when the beginning of the second part of the shift register is found, the pulse (HH) is fed through the main input of the adder AND And 9 to the counter-divider 3, the first pulse will overflow the counters and each n - the pulse will also overflow the counter, and through the element OR 8 the pulse is fed to the input of the addition of adder 2, After passing the n series of pulses X, cumulative, number: (1L ,,%, equal to the arithmetic average, where E (H) is the whole part of Number 2 in brackets In moments of time when there is no measurement impulse, the input of the element 5 And the generator 14 during the first part will give a locking impulse and The portion is erased each time. During the pulse

The measurement in the first part is recorded, accumulating in X | shear of the shift

 When the beginning of the W part of the shift register at the Eurasian input, the sum of the torus 2 is found, a pulse with the output W is fed to the triggers 12 and 13, preparing them for receiving the pulses, and in addition to the beginning of the W part, the pulses (output Shz) are fed to the addition inputs and glands through the corresponding elements OR,

Shift register 1 has intermediate outputs through KP, KP + K1 bits from the beginning of the shift register (to the left of the drawing), where KI and KT are the numbers of bits of G and I parts, triggers 12 and 13 delay the pulse from intermediate outputs by one cycle shear. Thus, the adder will be followed by the numbers delayed by one clock cycle from I and P parts of the adder via trigger 13, the element OR 8 and trigger 12, the element OR 10, respectively.

When recording the first series of X through the adder in the P part, it is written:

(2Xi-b1) xfx, 2

13 and 8:)

G2E (-)

, -ггЬД Л 1 12 and 10 where 2 is obtained by a shift towards the higher bit by one, since such a shift is equivalent to multiplying by two + I in brackets is obtained by the above generator 14 (output / I W)

The multiplication n by the expression in square brackets is obtained by tego that the contents of the second part of the shift register is subtracted from the third part tt times, until the pulse from the counter-divider 3 changes the content of the part ff, i.e. first, I times subtracted I, then 3 times - 3, then N times - 5, and so on.

With the arrival of the second series of impulses, + X proceeds through trigger 13 and healer 3,

 E ()

-I 2 (-) fx. n / through elements 12 and 10,

Thus, after the P series of pulses in Part III of the shift register, it will be written:

 | xf-nf bEC hihlxf-n

 I.f-n

2 and (yy-1),

where D THT CIXj-PX)

dispersion.

After the passage of a series of pulses, the sample sampling counter 4 will overflow and (turn on generator 16 and part B of the clock generator 3 4, turning on

5, part A, switches the counter-divider, reducing the coefficient of its disruption to the unit, and through the delay element 17 sets the counter 3 to the unit state,; Element And 7 is open zero output

IQ of the trigger 15, Pulses from the generator 16, synchronized with the operation of the circuit, so that its frequency is equal to the frequency of the shift cycle, controls the operation of the phek.y. The pulse at the beginning of the first part of register 1 through the element OR 9 is fed to the input of the counter-divisor 16 l 3, it opens up a pulse, and the pulse from the last is written to the first part of the register shifts, the number in the 11 part of the shift is saved.

2 {At the beginning of the third part (Hf c) is subtracted, One-Disposable 11 delays the number recorded in the G part by one measure. Similarly to that described previously, tt - 1 is subtracted from the third part.

And once the number of the first part shifted to the discharge, and in the first part, the number S is written, and the number is subtracted from the third part:

.- (n-l) Z: 2S-f-1 (g7-OZ

90

The process ends when a unit is generated at the end of the еди part at the output of the adder 2 (the shift register must be calculated so that normally in the last discharge of the part there is zero), which is generated by the loan, i.e. the number in 111 parts per cycle used to be zero, the pulse at the end of P1 part (IU j) polls the element AND 6, reflash trigger 15, which closes the element AND 7. The first part will contain the number S, which can be determined from equality:

(p-h) 5 d (p-1),

those. S y - equal to the average 45 square

unbiased deviation.

For normal operation, the number of bits in the III part of the Kill should be greater than 80 K J or K, and since the accumulation process does not contain the Xf value in the beginning of the dial, it is much larger

than P C) p,

Such a device is practically possible.

55 work with several and decimal sections; without significant circuitry with an increase in the number of bits, the problem is achieved by using a shift register that can be executed as one and a single one (tag (al7

circuitry, a combined adder, which will allow us to jointly reject cumbersome parallel adders or reversible counters, as in known devices. The counter-divider 3 carries a double load: it divides the number of pulses when calculating the arithmetic average, with its help it is multiplied by n ka-j drafts of arithmetic average in the accumulation mode and by - 1 mean square in the computation mode,

Such a device will occupy a volume several times smaller than the existing ones, and it works with any predetermined sample. The clock generator, shlpulsov conditionally shown in the drawing section 1-shmy into two parts, In fact, he is one, only on the outputs in aanucvfosti on the type of work produced different series of pulses. Such a generator can be performed using several methods, in particular, on the basis of meters with a dual encoder or a multiphase delay element.

Claims (1)

Invention Formula A device for calculating the mean square dramatic deviation, containing a sampling counter, connected by an input to a control input of a device, and an output to a control input of a pulse generator, a shift register, a combining controller, elements OR, elements AND, a delay element connected by a stroke to an input installation in the unit account eight; a divider divider, the control input of which is connected to the output of the selection counter, four triggers, clock generator, is different In order to simplify the device, in it the output of the first element I is connected to the input of the shift register, the output of which is connected to the first input of the combinational adder connected by the output to the first inputs of the first and second elements I, the output of the second element -. This AND is connected to the input of the first trigger .p connected to the first input of the third element AND, the second input of which is connected to the output of the pulse generator, the second and third inputs of the combinational adder are connected respectively to the outputs of the first and second elements OR, the output of the third element AND is connected to the input clock generator pulses, the outputs of which are connected respectively to the second input of the first element AND, to the inputs of the second element OR, to the inputs of the third element OR, to the installation inputs of the second, third and fourth triggers and to the second input of the second element AND, the second installation inputs of the second, third and fourth triggers are connected to the corresponding shift register outputs; exits second and fourth of the triggers are connected to the corresponding inputs of the first OR element; the output of the third trigger is connected to one of the inputs of the second element OR, the other input of which is connected to the output of the counter-divider, the control input of which is connected to the input of the element of the delay.