SU1350825A1 - Digital filter - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to increase the speed. The digital filter contains a block of RAM (BOP) i, counters 2 and 3, a block of permanent memory 4, adders 5 and 11, multiplier 6, buffer registers 7, 9 and 10, accumulating adder (NS) 8, RS-flip-flop 12, D-flip-flop 13, 1K-flip (. / Ger 14, decoder 15 and synchronizer 16. The filter is operated in a cyclic mode. At the beginning of the cycle, the information recording mode in BOP 1 is set, and then the convolution formation mode of input samples data and samples pulsed x-ki filter, which repeats the procedure for calculating the product of samples on the coefficients of the impulse filter x-ki and accumulation of the sum of products in NA 8. The goal is achieved by introducing the BOP 1, counters 2 and .3, registers 9 and 10, adder 11, triggers 12, 13 and 14, and decoder 15. Given the synchronizer 16. 3 ill. (L with

Description

The invention relates to radio engineering and can be used to filter data specified by a digital code.

The purpose of the invention is to increase the speed,

Figure 1 shows the electrical block diagram of a digital filter 15.

20

25

ra; in fig. 2 - synchronizer circuit; The 58 digital filter timing in FIG. 3 - timing diagrams for the operation of a digital filter.

The digital filter (Fig. 1) contains a block of 1 RAM, the first 2 and second 3 counters, block 4 constant memory, the first adder 5, the multiplier 6, the first buffer register 7, the accumulating adder 8, the second and third buffer registers 9 and 1Q, second adder II, RS-flip-flop 12, D-flip-flop 13, 1K-flip-flop 14, decoder 15, snifrozer 16, digital filter data input 17, digital filter synchronization input 18, digital filter clock input 19, output 20 digital filter.

The synchronizer 16 (Fig. 2) contains the elements NOT 21 and 22, the elements And 23-26.

The digital filter works as follows.

His work takes place in a cyclic mode. At the beginning of the digital filter operation cycle, block 1 of the RAM is set to record information with a signal from the 1K-trigger output 14. Input 7 of the digital filter data receives another input signal count, input 18 of the digital filter synchronization is a clock pulse, accompanying input readout. A clock pulse of the input signal records the next sample of the input signal in the RAM block 1 at the address generated at the output of the adder 11 as the sum of the output code of the first counter 2 and the zero code from the output of the permanent memory block 4. At the same time, a clock pulse accompanying the counting of the input signaling pulse accompanying the next counting of the input signal, a pulse normalized to the clock pulse period is formed at the output of the D-flip-flop 13 (the pulse and the edge of this pulse coincide with the edges of the auxiliary clock pulses (Fig. 3 a B C D E) .

The impulse from the output of the D-flip-flop 13 p steps on the signal input of the first counter 2, increasing the code on its output by one, on the reset inputs of the storage accumulator 8 and the second counter 3 and 1-input of the 1K-trigger 14. The next clock pulse translates 1K- trigger 14 in a single state. The signal from its output enables the digital filter to operate in the mode of forming the convolution of samples of input data and samples of the filter impulse response.

At the same time, the output signal 1K-trigger 14 switches the RAM unit 1 into read mode and resolves the operation of the synchronizer 16 and the second counter 3.

A digital filter records 2M + 1 of the last incoming digital data on Q in Q corresponding to samples of the input signal stored in RAM 1 and M + 1 pulses of the digital filter stored in C5 4 fixed memory, according to the ratio

. U :(.) H, (1

thirty

35

fn-o

i.

where h - coefficients modified

50

impulse response; h at at

This translates the RS flip-flop 12 into a single state, which is used as the start signal of the digital filter.

The output signal of the RS-flip-flop 12 is fed to the D-input of the B-flip-flop 13, the first clock pulse received at the clock input 19 of the digital-analog filter, sets in one state the D-flip-flop 13, the output signal of which is fed to the R-input of the RS flip-flop 12 and resets it to its original position. The next clock pulse translates the D-flip-flop 13 to its original position. Thus, regardless of the time of entry

58 sync digital filter

clock pulse, accompanying the next counting of the input signal, at the output of the D-flip-flop 13 a pulse is formed normalized, equal to the period of the clock pulses, duration. Moreover, the front and the cut of this pulse coincide with the fronts of the auxiliary clock pulses (Fig. 3 a, b, c, d, e).

The pulse from the output of the D-flip-flop 13 is fed to the signal input of the first counter 2, increasing the kOE at its output by one, to the reset inputs of the cumulative adder 8 and the second counter 3 and 1-input of the 1K flip-flop 14. The next clock pulse translates the 1K-flip- ger 14 in a single state. The signal from its output enables the digital filter to operate in the mode of forming the convolution of samples of input data and samples of the filter impulse response.

At the same time, the output signal of the 1K flip-flop 14 switches the RAM 1 unit to the readout mode and res. solves the operation of the synchronizer 16 and the second counter 3.

The digital filter performs the convolution of 2M + 1 of the last received data at the input of the digital fschtr, corresponding to the samples of the input signal stored in memory 1 and the M + 1 samples of the impulse response of the digital filter stored in memory 4. ti according to the ratio

. U :(.) H, (1)

fn-o

i.

where h - coefficients modified0

impulse response; h at at

h

n In the relation (1) is used

5E

symmetry property of the impulse response of a digital filter, according to which

When implementing such an algorithm for calculating convolution for

For each multiplication operation, from the array of (2M + 1) -th samples stored in memory block 1, you must select two samples that are symmetrically located with respect to the average (M + +1) -th sample. The output code of the first counter 2 determines the address of the last processed sample increased by one. Consequently, its arbitrary code, in the particular case of O,

If the corresponding address-shift constants arrive at the input of the second adder I1 from block 4 of the memory, this solves the problem of sampling the desired samples. If the convolution calculation starts from the extreme samples, then at the beginning of the convolution calculation, the output code of the second counter 3 determines the zero cell address of the fixed memory block 4, the output of which forms the constant offset of the address of the random memory block 1, is -1. In this case, the output

The described procedure of calculating the product of counts by the coefficients of the filter impulse response and accumulating the sum of the products in accumulative adder 8 is repeated (M + 1) times, at the time of the (I + 1) -th summation in the accumulating

The second adder 11 forms the address of the last recorded sample, 25 adder 8 triggers a decoder whose value is generated at the output 15, the output signal of which is fed to the K input of a 1K flip-flop 14. The next clock pulse resets the 1K flip-flop 14 to its initial position, the output signal of which prohibits the operation of the second counter 3, the synchronizer 16, and translates the block 1 of the operation of the RAM block and, using a pulse from the output of the synchronizer 16, writes to the second buffer register 9 (Fig. Ze, z, z, and k, l). After the arrival of the next clock pulse, the output code of the second counter 3 determines the address of the first cell of the permanent memory 4, and at the output 30

memory in recording mode, i.e. ends the formation cycle whose convolution forms the constant CMe - ,, g ki, and the digital filter goes into the address of the block 1 of the operative initial state, mi, is equal to (-2M-1). At the output of the second adder 1I, the address of the first of the (2M +) - GO processed samples of the input signal is generated, the value of which is generated at the output of the RAM unit 1 and using the pulse from the output of the synchronizer 16 is written to the third buffer register 10 (FIG. Well, h, and, m, n).

After the arrival of the next clock pulse, the output code of the second counter 3 determines the address of the second cell of the permanent memory 4, at the output

Claims (1)

Invention Formula 40 A digital filter containing a series-connected first adder and a multiplier, a first buffer register, a fixed memory block whose output is connected to another in the 5th multiplier, accumulating the sum and synchronizer, the first and second. the outputs of which are connected respectively to the synchronization inputs of the first buffer register and accumulate which forms the value of the first 50 Total adder, the code of which VL is the pulse characteristic characteristic of the digital filter output, about the filter ki fed to the input of multiplier 6, to the second input of which the sum of samples stored in the second and third buffer registers 9 and 10. At the output of the multiplier, the product of the sum of samples is formed by the coefficient of the impulse response, which, using a pulse with the output of synchronizer 16 is written to the first buffer register 7 (Fig. 3 g, o, p, p, c). After the arrival of the next clock pulse, the output code of the second counter 3 determines the address of the third cell of the permanent memory unit 4, at the output of which the output of the synchronizer 16 is generated, a pulse is formed that adds the content of the accumulating adder 8 to the value of the product stored in the first buffer register 7 (Fig. 3 t, y). The described procedure for calculating the product of the samples by the filter impulse response coefficients and accumulating the sum of the products in accumulator 8 is repeated (M + 1) times, at the time of the (And + 1) th summation in the accumulator The adder 8 triggers the decoder 15, the output of which is fed to the K input of the 1K flip-flop 14. Another clock pulse resets the 1K flip-flop 14 to the initial position, the output of which disables the operation of the second counter 3, the synchronizer 16 and translates the block 1 operation 25 thirty memory in recording mode, i.e. finishes the convolution formation cycle, and the digital filter returns to its original state, formula of invention A digital filter containing a series-connected first adder and a multiplier, a first buffer register, a block of permanent memory, the output of which is connected to another input of the multiplier, an accumulator and a synchronizer, the first and second outputs of which are connected respectively to the synchronization inputs of the first buffer register and accumulating55 characterized by the fact that, in order to improve speed, the first counter and the second adder, the RAM block, the data input and the synchronization input of which are the data input and the digital filter synchronization input, are entered in series, and the address input is connected to the output of the second adder, the second buffer register, the data input of which is connected to the output of the RAM block, the synchronization input is connected to the third output of the synchronizer, and the output is connected to the first input of the first adder, the third buffer register, whose data input is connected to the output memory unit, the synchronization input is connected to the fourth output of the synchronizer, and the output is connected to the second input of the first adder RS-trigger, whose S input is connected to the synchronization input of the digital filter pa, D-flip-flop, D-input of which is coupled to an output RS-flip-flop, and an output coupled to an input of the first counter, with the R-input of RS flip-flop and the reset input of the accumulator, 1K-flop, whose input is 1-soefig. 2 The dinene is with the D-flip-flop output, and the output is connected to the RAM memory mode selection input and the synchronizer control input, the second counter, whose signal input is combined with the C-inputs of the 1K flip-flop and the D-trigger and the clock input of the synchronizer and is the clock input pulses digital filter, a reset input is connected to the D-flip-flop output, and a control input is connected to the IK-flip-flop output, and a decoder, the input of which is combined with the address inputs of the fixed memory unit and the synchronizer and connected to the output of the second counter. -input 1K-trigger, while the output of the multiplier is connected to the data input of the first a buffer register whose output is connected to the data input of the accumulating adder.