SU1314445A1 - Digital for non-recursive odd-order filter - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to increase the speed. The device contains two switches 1 and 2, two shift registers (PC) 3 and 4, adder 5, two. accumulating adders 6 and 7, two multipliers 8 and 9, a block of memory 10 increments of coefficients, a block of memory of 11 digits of coefficients and a block of synchronization (BS) 12. The following operations are performed to form each output sample: the summation is symmetrical arranged samples of input signals, the formation of the product of the amounts obtained by the signs of the corresponding coefficients, of which then form the partial sums of the input samples, multiplying them by the corresponding increments of the coefficients and adding the results m between themselves. The goal is achieved by the introduction of switch 2, PC 4 and adder 5. Given the scheme BS 12. 2 ID. 1 tab. SL 8iao: 4 4 SL

Description

The invention relates to radio engineering and can be used in digital signal processing systems.

The purpose of the invention is to improve performance.

FIG. Figure 1 shows a structural electrical circuit of a digital non-periodic, italic filter of odd order; in fig. 2 - diagram of the synchronization unit

The digital non-recursive filter of odd order (Fig. 1) contains the first and second switches 1 and 2, the first and second registers 3 and 4 of the shift, the adder 5, the first and second accumulating adders 6 and 7, the second multiplier 8, the first multiplier 9, block 10 increment-coefficient memory, coefficient character memory block 11, synchronization block 12, synchronization block address output 13, synchronization block installation output 14, first synchronization block control output 15, synchronization block clock output 16, second control output 17 of block synchronized ation, input 18 and output 19 of the digital FIR filter of odd order.

Yn

The synchronization unit 12 (FIG. 2) comprises a clock pulse generator 20, a counter 21, a decoder 22j element AND 23.

fO

The digital non-recursive filter of odd order works as follows.

way i

Consider the algorithm of its work, which we obtain on the basis of the convolution algorithm:

15

m

 z:

X,

(ABOUT

20

Taking into account that the filter coefficients of non-recursive filters are usually symmetric, then (1) can be converted for the filter odd to the form

(M-and-1

Yn i; a

1gO

(X „., - X ,.„ .;).

(2)

7

Expression (2) can be converted by replacing the weighting factors a; their increments ua; but; - a, -, where yao a ,,. and their signs sign (a;)

(a6) (X + X, „) + (& a„ + ya,) sign (a,) (X „., + X,„ „) + + ... + ua“ + ua, -f ... + ua ,,,,,, (,,,,., x (,,, + X, j ,,,

(M-) / g-1 (M4) (2

 Il & aj 21 si8n (a;) (X, .. + X „,;). (3)

i - j

j o

From expression (3) it can be seen that for the formation in the right (output) cell of the formation of each output sample, 35 memories of the first shift register 3

It is necessary to sum up the symmetrically located samples of the input signals, form the products of the obtained sums by the signs of the corresponding coefficients, from which then form (M-f1) / 2 partial sums of the input samples, multiply them by the corresponding increment of the coefficients and add the results together, and the sum formation is symmetrical located input samples must be started with the sum of p- (M + 1) / 2-1 and p- (M + 1) / 2 counts, and finish with the sum of p and p-M counts.

This algorithm is implemented as follows.

At the beginning of each computation cycle, the signal comes from the installation output 14 of the synchronization unit 12.

produces zeroing of the first and second from the first control output of accumulating adders 6 and 7. 15 of the synchronization unit 12, switches the first switch 1 to the signal switching mode from input 18 and to the input of the first shift register 3

The recording in the first and second registers 3 and 4 of the shift is organized in such a way that at the beginning of each cycle there will be 13144452

The synchronization unit 12 (FIG. 2) comprises a clock pulse generator 20, a counter 21, a decoder 22j element AND 23.

The digital non-recursive filter of odd order works as follows.

way i

Consider the algorithm of its work, which we obtain on the basis of the convolution algorithm:

m

 z:

X,

(ABOUT

Taking into account that the filter coefficients of non-recursive filters are usually symmetric, then (1) can be converted for the filter odd to the form

(M-and-1

 i; a

1gO

(X „., - X ,.„ .;).

(2)

Expression (2) can be converted by replacing the weights a; their increments ua; but; - a, -, where yao a ,,. and their signs sign (a;):

The value of p- (M-b1) / 2-1-th input sample is stored, and in each cell to the left is the value of samples with numbers one less. At the same time

in the right cell of the second shift register 4, the value of n- (M + 1) / 2-nd input sample is written, and in each cell to the left is the value of samples with numbers one more. Therefore, in the first calculation cycle in: the first accumulating adder 6, the first multiplier 9 by -1-1 and the adder 5 from the outputs of the first and second registers 3 and 4 of the shift arrive the product of sum-1s n- (M + 1) / 2-1- go and

p- (M + 1) / 2-nd input samples, multiplied by the sign () / 2-1-th coefficient.

Simultaneously with this signal, post313

the value of the current input signal X „. The control input of the second switch 2 from the second control output 17 of the synchronization unit 12 begins to receive a signal that keeps the second switch 2 in the switching mode of the signal from the output of the second register 4, shifting until the beginning of the last calculation cycle. Therefore, at the end of the first calculation cycle, the value of n- (M-I) / 2nd input sample is written to the first cell of the second register 4 of the shift from the clock output 16 of the synchronization unit 12, and the value of the current first 3 cells of the first register 3 of the shift input sample X. Here, the value of the n- (M + 1) / 2-1th sample from the first shift register 3 is derived.

Starting from the beginning of the second calculation cycle and until the end of the last calculation cycle, the signal from the first control output 15 of the synchronization unit 12 to the control input of the first switch 1 keeps it in the switching mode of the signal from the output of the first shift register 3. Therefore, (M + 1) / 2 calculation cycles, the data from the outputs of the first and second registers 3 and 4 of the shift are cyclically rewritten into their first cells. In the last calculation cycle, the signal coming from the second control output 17 of the synchronization unit 12 transfers the second switch 2 to the switching mode of the signal from the output (M-1) / 2-1 of the first memory location of the first 3 shift register. As a result, at the end of the last calculation cycle, the value of the n- (M + 1) / 2-1th input sample is written to the first cell of the second shift register 4, and the n-th count from the second shift register 4 is output.

The table shows the location of the input n-i-x samples in each of the cycles of the n-th calculation cycle in registers 3 and 4 of the shift for the filter of the seventh order (the value of i is given).

-one

4231 1123

Table continuation

O 5

0 5 0 5 0

five

0

During (Mn-1) / 2 clock cycles of each calculation cycle, partial sums are formed at the output of the first accumulating adder 6:

(M + ll / 2-l

. 21 sign (a.) (X.; + X „.;;);

1 () / l-l (M + 1V7-I

. sign (a;) (X.; + X..j);

A (M + (l-2

CMti); 2 -1 i: sign (a;) (X,.; - b X.),

which BO of the second multiplier 8 is multiplied by the small-scale increments of the coefficients La ,,,,,

yad coming from block

0

the memory of the increments of the coefficients synchrony with partial sums from the output of the first accumulating adder 6. The calculated products for (M + 1) / 2 calculation cycles are summed in the second accumulating adder 7, where at the end of the last (M-1) / 2 cycles of each cycle the next counting of the output signal Y, arriving at the output 19, is calculated. With the arrival of the next input reference X, the cycle of the counting is repeated.

Claims (1)

Invention Formula An odd-order digital non-recursive filter containing a first switch connected in series, the first input of which is an odd-order digital non-recursive filter input, and a first shift register connected in series to the first multiplier, the first accumulating adder, the second multiplier, and the second accumulating adder, whose output is output, a digital non-recursive filter of odd order, as well as a memory of characters of coefficients, the output of which is connected to the first input of the first multiplier The unit, the memory unit of the increment coefficients, the output of which is connected to another input of the second multiplier, and the synchronization unit, the address output. krt, op (ego. connected with the inputs of the block. tam. order of coefficients and block pAM; tj. increments of coefficients, condition- The new output is connected to the inputs of the installation of the first and second accumulated C f- ..  The total adders, the first control f5 l, while the clock output of the unit star is connected to the control input of the switch, the clock output is connected to the clock inputs of the first synchronization is connected to the clock input of the second shift register, and in a swarm the control output is connected to the equal input of the second switchboard and BiiopiGjt o accumulating adders and 20 21 22 Editor M. Dylyn Compiled by E. Borisov Tehred V. KadarKorrektor M. Pojo Order 2219/55 Circulation 902 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 144456 of the first register, the first output of which is connected to the second input of the first switch, characterized in that, in order to increase the speed of 5 romances, a second switch, the first input of which is connected to the second output of the first shift register, is entered into it, the second shift register whose output O is connected to the second input of the second switch, and an adder, the other input of which is connected to the first output of the first shift register, and the output connected to the second input of the first multiplier, while the clock output of the block synchronization is connected to the clock input of the second shift register and the second control output is connected to the control input of the second switch. 23 H ± G 2 - 77 iv.2