SU1352622A1 - Digital filter - Google Patents

Abstract

The invention relates to radio engineering and can be used to filter signals defined by a digital code. The purpose of the invention is to expand the functionality by implementing the transfer function of even yo dka. Digital filter recursive filter contains switches 1, 2, 20, shift registers 3, 4, adder 5, accumulating accumulators 6, 7, multipliers 8, 9, block 10 of the memory increment coefficient, block 11 of the characters memory coef, block 12 of synchronization and block 21 of the ban. To form each output sample, it is necessary to sum up the symmetrically located samples of the input signals, to form the products of the obtained sums by the signs respectively. coefficients, from which to form М / 2 + 1 partial sums of input samples, multiply them by the corresponding. increments and the results add up among themselves. The formation of the sums of symmetrically located input samples must be started with the sum of (nM / 2) -th sample with zero, and finished with the sum of the nth and (nM) th samples. 2 Il. 1 tab. i (L S Fy

Description

 The invention relates to radio engineering and can be used to filter signals defined by a digital code.

The purpose of the invention is to enhance the functionality by implementing an even-order transfer function.

Fig. 1 is an electrical block diagram of a digital non-recursive filter; in fig. 2 is a block synchronization diagram.

Digital non-recursive filter (Fig. 1) contains the first and second switches 1 and 2, the first and second registers 3 and 4 of the shift, the adder 5, the first and second accumulating adders 6 and 7, the second and first multipliers 8 and 9, memory block 10 increments of the coefficients, block 11 of the memory characters of the coefficient, block 12 synchronization, address output 13 of the block

but; their increments ya; -a; -a;., and their signs sign (;)

M / 1-1

m1g-1

, signCO; ) (X; X „.,;)

G- ° 1

ten

15

20

M / 2

+ sign (a,) X, Schda ;. (3)

i 0

From the expression (3) it follows that in order to form each output sample, it is necessary to sum up symmetrically located samples of input signals (nM / 2 sample is summed by zero), to form products of the obtained sums by the signs of the corresponding coefficients, from which then form M / 2 + 1 partial sums of input samples multiply them by the corresponding increments of the coefficients and add the results to each other. With this, the summation is symmetrically located from the sum of the n-M / 2nd sample with zero, and finished with the sum of the rv-ro and the p-th counts.

sync, setup output 14

the synchronization unit, the first input 25x bix input selections need the initial output 15 of the synchronization unit, the second control output 16 of the synchronization unit 15, the clock output 17 of the synchronization unit, the input 18 of the digital non-recursive filter, the output 19 of the digital non-recursive filter, the third switch 20 and block 21 ban.

The synchronization unit 12 (FIG. 2) contains a counter 22 modulo M / 2 + 1, a decoder 23, an AND 24 element and a gene30

35

The first and second registers 3 and 4 of the shift carry out storage and through the first and second switches 1, and 2. cyclically shift the data stored in them. Via switches 1 and 2, the new registers 3 and 4 of the shift also record the new data from input 18 and the first register 3 of the shift, respectively. The adder 5 produces a summation of symmetrically arranged input samples, which with numbers from p to p-M / 2 are contained in the first shift register 3, and with numbers from p-M / 2 to p-M, in the second register 4 of the shift. The first multiplier 9 by +1 multiplies the sums received by 4g from the output of adder 5 by the signs of the respective coefficients, which are stored in block 11 of the memory of the signs of the coefficients. The resulting products are accumulated in the First accumulating adder 6 as partial sums, which are then multiplied in the second multiplier 8 by small-order increments of the coefficients stored in the coefficient increment memory 10, and the products obtained are accumulated in the second accumulating adder 7.

Rotor 25 clock pulses.

Digital non-recursive filter works as follows.

To determine the algorithm of the proposed filter, the initial one is the convolution algorithm.

M

; .

(one)

 Taking into account that the filter coefficients of non-recursive filters are usually symmetrical, the expression (1) for an even-order filter can be represented as H (1g

, .Vi n-M.i). (2)

Expression (2) can be converted by replacing weights.

but; their increments ya; -a; -a;., and their signs sign (;)

M / 1-1

m1g-1

, signCO; ) (X; X „.,;) NG- ° 1

M / 2

+ sign (a,) X, Schda ;. (3)

i 0

From the expression (3) it follows that to form each output sample, it is necessary to sum up the symmetrically located samples of the input signals (nM / 2 is the sum of zero samples), to form the products of the obtained sums by the signs of the corresponding coefficients, from which then form M / 2 +1 partial sums of input samples, multiply them by the corresponding increments of the coefficients and add the results to each other. With this, the summation is symmetrically located from the sum of the n-M / 2nd sample with zero, and finished with the sum of the rv-ro and the p-th counts.

"Bix input bleed need to start

"Bix input selections need to be initially

The first and second registers 3 and 4 of the shift carry out storage and through the first and second switches 1, and 2. cyclically shift the data stored in them. Via switches 1 and 2, the new registers 3 and 4 of the shift also record the new data from input 18 and the first register 3 of the shift, respectively. The adder 5 produces a summation of symmetrically arranged input samples, which with numbers from p to p-M / 2 are contained in the first shift register 3, and with numbers from p-M / 2 to p-M, in the second register 4 of the shift. The first multiplier 9 by +1 multiplies the sums coming from the output of the adder 5 by the signs of the respective coefficients, which are stored in block 11 of the memory of the coefficients. The resulting products are accumulated in the First accumulating adder 6 as partial sums, which are then multiplied in the second multiplier 8 by small-order increments of the coefficients stored in the coefficient increment memory 10, and the products obtained are accumulated in the second accumulating adder 7.

At the beginning of each calculation cycle, the signal coming from the setup

The first output 14 of the synchronization block 12 zeroes the first and second accumulating adders 6 and 7. The write to the shift registers 3 and 4 is organized so that at the beginning of each calculation cycle in the right (output) memory cell of the first shift register 3 the value P is stored -M / 2-d input count, and in each cell to the left is the value of the counts with the numbers one less. At the same time, in the right memory cell of the second register 4 shift, the value of p-M + 1-th input sample is written, in the next cell to the left is p-M / 2-second count, and in each next cell to the left is counts with numbers one more. In the first cycle of each calculation cycle, the signal from the first control output 15 of the synchronization unit 12 transfers the first, second and third switches 1, 2 and 20 to the signal switching mode, respectively, from input 18, output of the first shift register 3 and logical zero input non-recursive filter. At the end of the first calculation cycle, the value of the current input sample is recorded in the first memory cell of the first shift register 3, and the p / M value of the second count is output from the last cell, which is written in the first cell of the second shift register 4, from the last cell of which shift p-M + value of the 1st reference. During the first clock cycle, the p-M / 2nd count values from the output of the first shift register 3 arrive at the inputs of the adder 5 and the zero value from the output of the third switch 20. Therefore, at the end of the first calculation cycle, the product of the first accumulator 6 is written to the register -M / 2-r count on the sign of the M / 2 coefficient. At the same time, this product is multiplied in the second multiplier 8 by the value of the coefficient increment

u o M / i and the resulting product is recorded in the second accumulating adder 7.

Starting from the beginning of the second calculation cycle and until the end of the last calculation cycle, the signal coming from the first control output 15 of the synchronization unit 12 to the control inputs of the first, second and third switches 1, 2, 20 switches

0

0

five

the first switch 1 is in the mode, the switching signal from the output of the perpendicular register 3 shift, and the second and third switches 2 and 20 in the switching mode of the signal from the output of the second register 4 shift. During the M / 2-1 th clock cycle, under the action of the clock signals coming from the clock output 16 of the synchronization unit 12 and the output of the block 21, the clock inputs of the first and second shift registers 3 and 4, respectively, are cycled to 5 records information. During the last AND / 2 + 1 th clock cycle, the clock signal arrives only at the clock input of the first shift register 3, and in the second shift register 4 the information remains unchanged.

The table shows the location of the input n-i-x samples (the value of i is indicated) in each of the cycles of the n-th calculation cycle in registers 3 and 4 of the shift for the eighth-order filter, as well as the number of samples, in. Stepping on the input of the adder 5.

During the M / 2 + 1 clock cycles of each calculation cycle, partial sums are successively generated at the output of the first accumulating adder 6:

five

0

sign (a,) X signCa,.,) Х „,

(X.-i

. M / 4-1

signC O; ) "

+ X

n-AA -1

mg

sign (a “,) X., + 2signCa; ) "

(x „., + x

n-wfi

),

45

go

which in the second multiplier 8 are multiplied by small-bit increments

coefficients: “M / a-t icio. , received from the block 10 of the memory of the increments of the coefficients synchronously with the partial sums from the output of the first accumulating adder 6. The calculated products for 55 M / 2 + 1 calculation steps are summed up in the second accumulating adder 7, where at the end of the last M / 2 + Step 1 of each cycle of the calculation is formed the next count

the output signal of the Pack, enters the output 19 of the digital non-reversible filter. With the coming of the next

The input reference is neither repeated.

X

„+, Cycle calculated by Formula Of

p and e and

A digital non-recursive filter containing a serially connected first switch, the first input of which is an input of a digital non-recursive filter, a first shift register, the output of which is connected to the second input of the first switch, a second switch, and a second shift register, the output of which is connected to the second input of the second switch, sequentially connected adder, the first input of which is connected to the output of the first shift register, the first multiplier, the first accumulator, the second multiplier, and the second on aplivayuschy adder whose output is an output of the digital FIR filter, a block memory signs of the coefficients, KOTopo.ro vtorm output connected to a first input of multipliers, a memory unit increments coefficient whose output is connected to the second input of the second multiplier and unit sinhroni10

1352622.

The address output of which is connected to the address inputs of the memory block of the coefficients and the memory block of the increments of the coefficients, the installation output is connected to the installation inputs of the first and second accumulating adders, the clock output is connected to the clock inputs of the first shift register and the first and second accumulative inductors, and the first control output is connected to the control input of the first switch, characterized in that, in order to extend the functionality by implementing the transfer function In even order, a third switch is inserted in it, the first input of which is connected to the output of the second shift register, the second input is connected to the input of the logic zero of the digital non-recursive filter, the control input is connected to the first control output of the synchronization unit, and the output is connected to the second input an adder, and a prohibition unit, the input of which is connected to the second control output of the synchronization unit 15

20

25

and the output is with the clock input 30 of the second shift register, while the first control output of the synchronization unit is connected to the control input of the second switch.

and the output is with the clock input 30 of the second shift register, while the first control output of the synchronization unit is connected to the control input of the second switch.

25

22

Editor A. Lezhnin

Compiled by E. Borisov

Tehred M. Khodanich Proofreader A. Obruchar

Order 5575/55 Circulation 900 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company,. Uzhgorod, st. Design, And

23

f4

15

FI.2

L

Claims (1)

Claim A digital non-recursive filter containing a first switch connected in series, the first input of which is an input of a digital non-recursive filter, a first shift register, the output of which is connected to the second input of the first switch, a second switch and a second shift register, the output of which is connected to the second input of the second switch, connected in series an adder, the first input of which is connected to the output of the first shift register, the first multiplier, the first accumulating adder, the second multiplier and the second accumulating the adder whose output is the output of a digital non-recursive filter, a coefficient sign memory block whose output is connected to the second input of the first multiplier, a coefficient increment memory block whose output is connected to the second input of the second multiplier, as well as a synchronization block whose address output is connected with address inputs characters of the storage unit coefficients and block RAM memory pas _g increments coefficients tired · "· novochnyi output is connected to inputs of mounting the first and second accumulators, t the act output is connected to the clock inputs of the first> 10 shift register and the first and second accumulating adders, and the first control output is connected to the control input of the first switch, characterized in that 15, in order to expand the functionality by implementing the even order, the third switch is introduced into it, the first input of which is connected to the output of the second shift register, the second input is connected to the logic zero input of the digital non-recursive filter, the control input is connected to the the control output of the synchronization unit 25, and the output - with the second input of the adder, and the inhibit block, the input of which is connected to the second control output of the synchronization unit, and the output - with the clock input 30 of the second shift register, while the first control output of the synchronization unit is connected to the control the input of the second switch. -----— Cycle number 8888 Measure number Shift Register Cells Inputs the first second adder 5 1 1 ² 3 4 4 2 3 4 5 1 1 ² n-1 5 2 3 4 . 1· g 8 7 6  5 9 1- 9 1 1. 2 3 4 8 7 6 5 . 9 . 4 Zero 2 0 1 2 3 4 8 7 6 5' 3 5 · P 3 3 0 1 2 5 4 8 7 6 2 6 4 2 3 0 1 6 ' 5 4 8 7 1 7 5 1 '2 3 0 7 6 5 . 4 '· 8 0 8 n + 1 .1 0 1 2 3 7 6 5 4 8 3 Zero tpue.Z