SU1444751A1 - Multiplication device - Google Patents

Abstract

The invention relates to the field of computational technique and can be used to multiply g-bit numbers represented in Fibonacci codes, or numbers in which the multiplicand is represented in the Fibonacci code and the multiplier in the binary code. The purpose of the invention is to extend the functionality by multiplying the numbers represented in 1 Fibonacci code by the numbers represented in binary code. The device contains two registers 1.9, a generator 2 of a sequence of generalized Fibonacci numbers, two doubling blocks 3.10, five switches 4-8, a multiplier register 12, two adders 11, 13, a register of 14 partial products. The introduction of the second doubling unit and the three switches allows multiplication of the numbers represented in 1 Fibonacci code by the numbers represented in the binary code — without first converting them into 1 Fibonacci code. 2 tab., 1 Il. with b (L

Description

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The invention relates to computing and can be used to multiply the g-bit numbers represented in the I Fibonacci code by an n-bit binary number and the n-bit number represented in the I Fibonacci code.

The purpose of the invention is to expand the functionality of the device by multiplying the numbers represented in the I Fibonacci code by the numbers represented in the binary code.

The drawing shows a functional diagram of the proposed device. The device contains the first register (P) 1, designed to record doubled partial products, the generator 2 of the sequence of generalized Fibonacci numbers (GPCHF), intended for the sequential formation of generalized Fibonacci numbers with odd numbers, the first block of 3 doubling (B Udv), is intended for duplicating the generalized Fibonacci numbers with even numbers and the first term of the sequence of the generalized Fibonacci numbers or for doubling the previous partial product, switches (KM) 4-8, intended for comm Utions of information signals when multiplying by a binary factor or a Fibonacci factor, the second register (Pr) 9 is intended for storage formed by the adder and the unit 3 for doubling the sequence of generalized Fibonacci numbers, the second unit 10 for doubling (B Udv), intended for doubling the content of the second register, the first adder (CM) 11, designed to form a sequence of generalized Fibonacci numbers with even numbers or the sum of two partial products, the multiplier register 12 (RGNN), in which c multiplier code, second adder (CM) 13, intended for receiving the sum of partial products, register 14 partial products (PPP), intended for storing intermediate amounts, input 15 initial installation of the device, input 16 of the device synchronization, input 17 of writing the device code, input 18 multiplicable devices, input 19 of the sign of the device code, input 20

ten

15

20

25

thirty

35

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45

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multiplier device and output 21 devices.

The device works as follows.

Consider the operation of the device for multiplying integers with examples of multiplying the number 60 represented in the I Fibonacci code by the number 37 represented in one variant in the I Fibonacci code and in the second in the Binary code.

Consider the operation of the device when multiplying the number 60 by the number 37 represented in the I Fibonacci code, while at the input 19 of the device code feature there is a signal of a logical unit that connects the generator 2 output of the sequence of generalized Fibonacci numbers to the input of the adder 11 to the input of the doubling unit adder 11, the output of the adder -11 - to the input of the register 9, the output of the register - to the input of the unit 3 doubling.

In the initial state, the multiplier code is located at the input of 20 multipliers, the multiplicand code is at the multiplex input 18, the generator 2 output is of the sequence of generalized Fibonacci numbers, register 9, adder 13 and partial work register 14, the code is zero, the code record input 17 there is a enable signal for writing the multiplier codes to the generator 2 of the generalized Fibonacci numbers and to the multiplier register 12; at the output of the doubling unit 3 and the adder 11 there is the double multiplicand code. With the arrival at synchronization input 16 of the first synchronizing pulse generator; The 2 generalized Fibonacci numbers form the first number of a sequence of Fibonacci numbers, in this case, the double multiplied code is recorded in register 9, and the multiplier code 12 is recorded in the multiplier register 12. If the unit 12 registers the multiplier 12 in the decade 12 multiplier, the adder 13 adds the code from the output of the generator 2 to the sequence of generalized Fibonacci numbers and the code from the register of 14 partial products. If a unit is recorded in the (p-1) -th digit, the adder 13 adds the code from the output of register 9 and the code from the output of the register 14 partial products. If two lower bits of register 12 of the multiplier are written to two zeros, then switch 8 passes the zero signal to the input of the adder 13. Then, under the action of the next clock pulse, the multiplier code is shifted by two bits towards the lower bits in the register of the 12 multiplier and the next pair is formed Generalized Fibonacci numbers by a generator of 2 generalized Fibonacci numbers and. 3.Division unit in conjunction with adder 11.

The multiplication process ends after all 12 bits of the multiplier code are moved out of register 12 multiplier. The result of the multiplication will be in the register of 14 partial products, from where it enters the output 21 of the device. The states of the generator 2, generalized Fibonacci numbers, a doubling unit 3, an adder 11, a register 9, an adder 13, a multiplier register 12 and a register of 14 partial products corresponding to each device operation cycle are listed in Table 1.

Consider the operation of the device when multiplying the number 60 by the number 37, which is represented in binary code. At the same time, at the input 19 of the device code attribute there is a logical zero signal, which connects the output of register 1 to the input of adder 11 and to the input of switch 8, the output of doubling unit 10 to input of register 1 and to doubling unit 3 input, doubling unit 3 output register input In the initial state, the multiplier code is at the input of the multiplier 20, the multiplicand code is at the multiplier input 18, the register 1 output, the duplication unit 10 output, the output of the adder 11, the output of the register 9, the output of the adder 13 and the output register 14 partial works nah Dietz code zero at the input 17 is the recording code enable signal recording codes in the multipliers and register 1 to the register 12, the output unit 3 code is twice the doubling of the multiplicand. With the arrival of the synchronization input to the first synchronizing pulse 16, a multiplicand code is written to register 1, and multiplier code is written to register 12. If in the lower nth dereg register 12 multiplier the unit is written, then sum0

five

0

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five

0

The matrix 13 performs the addition of the code coming from the output of the “register 1” and the code coming from the output of the register of 14 partial products. If a unit is recorded in the (p-1) -th digit, the adder 13 adds the code from the output of register 9 and the code from the output of the register 14 partial products. If two units are recorded in two lower bits of the register 12 multiplier, then the adder 13 adds the code from the output of the adder 11 and the code from the register of 14 partial products. If in the two lower bits of register 12 of the multiplier two zeros are written, then switch 8 passes the zero signal to the input of the adder 13. Then under the action of the following clock pulse, the multiplier code shifts by two bits to the side of the lower bits in the register of the 12 multiplier and the corresponding the code values of the multiplicand for the next cycle of the device. The multiplication process ends after all 12 bits of the multiplier register are removed from the register. Multiply results will be in the register of 14 partial products, from where it goes to the output 21 of the device. The state of register 1, blocks 3 and 10 doubling, adder 11, register 9, adder 13, register 12 multiplier and register 14 partial products, sorting each step of the device, are given in table 2.

Claims (1)

Invention Formula A device for multiplying, a generator of a sequence of generalized Fibonacci numbers, the first doubling unit, the first switch, the first register, the first and second adder, the multiplier and register of partial products, the output of which is connected to the output of the device and the second of the first adder, whose output connected to the input of the register of partial products, the input of the initial installation of which is connected to the inputs of the initial installation of the register of the multiplier and the first register :, whose output is En with the first information input of the first switch, the output of which is connected to the input of the second term of the first adder, the information input of the register of the multiplier is connected to the input of the multiplier of the device, the input of the multiplicand of which is connected to the first information inputs of the sequence generator of the generalized Fibonacci numbers and the first doubling unit, excellent In order to extend the functionality by multiplying the numbers represented in the I Fibonacci code by the numbers represented in the binary code, the second register, the second doubling unit, the second, the third, the fourth, and the fifth are entered into it. switches, the input of the initial installation of the device is connected to the inputs of the initial installation of the second register, the generator of the sequence of generalized Fibonacci numbers and the first register, the synchronization input of which is connected to the synchronization inputs of the device, register partial products, a generator of a sequence of generalized Fibonacci numbers and a second register, the first information input of which is connected to the input of a multiplicand device, the input of a record of the code of which is connected to the inputs of a record of the register code of a multiplier, a sequence generator of a generalized Fibonacci number and a second register, the second information input of which is connected with the second information input of the first doubling unit, the output of the second switch and the second information input of the Sequence generator Fibonacci numbers, the output of which is connected to the first information input of the third switch, the output of which is connected to the second information input of the first switch and the input of the first term of the second adder, the output of which is connected to the third information input of the first switch and the first information input of the fourth switch, which output is connected with the information input of the first register, the output of which is connected to the first information inputs of the second block jKa doubling, the output of which is connected to the second The information input of the second switch, the control input of which is connected to the input of the device code and the control inputs of the third, fourth and fifth switch, the second information input of which is connected to the output of the first doubling unit and the second information input of the fourth switch; information inputs of the second and third switches are connected respectively to the outputs of the second doubling unit and the second register, the output of the fifth switch is connected to the input of the second term of the second adder , The outputs of the last and penultimate mpadshih bits multiplier register connected respectively to the first and second by the control inputs of the first switch, the fourth information input of which is connected to zero potential input devices. Table 120 120 000000 001000 000010 0 1 о о о 180,000 1 о 180 0000 о 2220 table 2