SU1254469A1 - Multiplying device - Google Patents

Abstract

The invention relates to the field of computing and can be used to multiply multi-digit numbers in Fibonacci p-codes. The purpose of the invention is to increase the speed of the device. The goal is achieved by multiplying the multiplier simultaneously by two multipliers, the duplicating unit, the switch, the second adder and the register are provided for the chegs. The device is an integral part of digital, computing and measuring equipment using codes with irrational bases. 2 nl. 3 tab.

Description

112544

The invention relates to computing and can be used to multiply multi-digit numbers in Fibonacci p-codes.

The purpose of the invention is to increase the speed of the device. -If the multiplier D is represented as

And a cfpCn) + a, .cfp (n - 1)

+ a, q-p (0),

then multiplication multiplier & will be equal

And on mn

B B- (n) + B- a., Cfp (n-1) + ... + B. a ifpCO),

where tfpCi) is a generalized Fibonacci number, which is defined as follows:

0 when i 0

1 at 1 0

Cfр (i-1) + (fp (i-p-1) with i О Partial product B-Cfp (i) with regard to relation (1) is defined as

In avg (i) B-Cf p (i-1) + B Cfp (i - P - O ..

Wed (1)

a, e 0, l (1)

This implies the following algorithm for multiplying integers in Fibonacci p-codes.

1 Form two columns of numbers, in the left of which is placed a sequence of generalized Fibonacci numbers with an initial condition equal to 1, it contains p-Fibonacci numbers that enclose the minimal Fibonacci p-code multiplier D. In the second column is placed a sequence of generalized Fibonacci numbers with an initial condition equal to multiple B. The result of multiplying A & i is formed by adding all the numbers in the second column to the corresponding Fibonacci p-numbers in the first column. At the same time, it is controlled that any allocated for addition the number of the second column is separated from the previous one and the following for selected for adding numbers not less than p of consecutive numbers of the second column. For the p-numbers, the following

ratio:

R

CfpCi + p-f 1) 2cf (i) + L Cfp (i - - j), J (2)

When p 1 formula (2) takes

view

five

0

20

15

25

thirty

five

40

55

45

50

692

Cf, (i + .2) - 2cp, (i) 4 cp (i - 1).

(3)

Based on expression (3), and since the minimum representation of numbers in two adjacent bits cannot be two units, it is possible to achieve the speed of the device for multiplying integer numbers in 1 Fibonacci codes by simultaneously considering two adjacent multiples of the numbers which only one bit can contain one.

Fig. 1 shows a functional diagram of an apparatus for multiplying integers; 2 is the same as the firmware control block.

The device (Fig. 1) contains a generator 1 of a sequence of generalized Fibonacci numbers, a doubling unit 2, an adder 3, a register 4, an adder 5, a partial work register 6, a switch 7, a multiplier register 8, a firmware control unit 9.

Unit 9 firmware control; neither (FIG. 2) contains the element OR 10, memory block 11, register 12, decoder 13, the i-th bit of the doubling unit, implements the following logic function:

,, A;, + A;., A;,; A; ,, - fA,., A;, A.4-H ,, - l / A,., A5, A; „1.,

where a; - value of the i-ro digit of the number B; - double the i-ro digit of the number.

The multiplier operates as follows.

Consider the operation of the device for multiplying integers using the example of multiplying the number 60 in 1 Fibonacci codes: by the number 37.

In the initial state in the register

8 the code of the number 37 is recorded in the minimal form of representation. The code of the number 60 sets the initial condition (zero number) of the sequence of generalized Fibonacci numbers, which is jointly formed by the generator 1 and the doubling unit 2 together with the Second adder 3, in the register 8 of the partial products the zero code is written.

According to the signal coming from the unit

9 microprogramming, generator 1 and doubling unit 2 together with the second adder 3 begin to form a sequence of generalized Fibonacci numbers. After that, as two consecutive numbers are formed.

3

 The firmware control unit 9 analyzes the positions of the two low-order bits of register 8 of the multiplier. If a unit is recorded in this group of bits in the lower order, the first adder 5 adds the code from the output of the generator 1 through the switch 7 and the code from the output of the register 6 partial products. If in this group of bits in the high order the unit is written, then the first adder adds the code from the register 4 output through the switch 7 and the code from the register 6 partial products. Then, the code is shifted by two bits in the direction of the lower ranks in register 8 multipliers and the formation of the next pair of generalized Fibonacci numbers by the generator 1 and doubling unit 2 together with the second adder 3.

If in the group of the lower bits of register 8 two zeros are recorded, block 9 of the microprogram control accumulates control signals, by which only a code shift by two bits in register 8 occurs and the next pair of numbers in the generator 1 and in block 2 are duplicated in conjunction with the second adder. The multiplication process ends next, as all bits of the multiplier code will be removed from register 8. In this case, the result of the multiplication will be in register 6, from where it enters the output of the device, multiply -.

The states of the generator 1, block 2, doubling, register 4, switch 7, register 8, multiplier and register 6 partial products, corresponding to each work cycle, are shown in Table 1.

Firmware control unit 9 operates in accordance with Table.

The control signals necessary for the operation of the device are listed in Table 3.

Claims (1)

Invention Formula A device for multiplying, containing the multiplier register, register products, the first totalizer of the sequence of generalized Fibonacci numbers and the microprogrammed control unit, the register output partial products connected to the output of the device and the first input of the first adder, the output of which is connected to the information input of the register of partial products, the register of the multiplier is connected to the input of the multiplier of the device, the input of the multiplicand of which is connected to the first information input of the generalized Fibonacci number generator, outputs of the register of the multiplier are connected to the input of the initial installation of the firmware control block, 15 20 Q 5 25 thirty five 0 five In addition, a doubling unit, a switch, a second adder, a register, an installation input in the register of the multiplier are connected to the installation inputs in the register of partial products and a register and connected to the first output of the firmware control unit, the second output of which is connected to the input write to the multiplier register, the input of the multiplicand device is connected to the first information input of the doubling unit, the control input of which is connected to the control input of the sequence generator Fibonacci numbers and is connected to the third output of the microprogram control unit, the fourth output of which is connected to the register entry input, the output of which is connected to the second information inputs of the Fibonacci generalized number generator and the first information input of the switch, the doubling unit output connected to the first input of the second adder, the fifth input of which is connected to the output of the generator of the sequence of generalized Fibonacci numbers and the second information input of the switch, p The first and second control inputs of which are connected respectively to the fifth and sixth outputs of the firmware control block, the seventh output of which is connected to the input of the register of partial products, the output of the second sum; the torus is connected to the information input of the register, the output of the switch is connected to the second input of the first adder , the shift control input of the multiplier register is connected to the eighth output of the micro-t software control unit. Table 1 table 2 0010010 00111001000 О О 00 ItrilTO 0000 001.0 011 00111001001 0000 1 1 1 1 1 I I 2 2 2 20010100001110010100000 0010101 00111001011 0000 00101,10001110011000000 0010111 00111 о .0 1 1 о 1 0-0 о о 0011000010010011100000 001100101001 About 1 1 1 1 0000 011 011 011 0.4 1 011 011 100 100 100 100 100 100 100 100 101 1o 1 101 101 101 about 1 about 01 1 About 1 about 1 1 1 about 111 000 about about 1 about 1 about 01 1 1 00 1 about 1 1 1 about 11 1 000 about about 1 about 1 about about 1 1 10 o 0100 0100 0100 010 o 0100 0100 1000 0101 0111 0101 1000 0101 01 1 1 o 1 01 0110 0110 0110 0110 0110 1010 1010 1010 1010 1010 1010 1010 1010 1011 1011 1011 1011 1011 1011 1011 1011 1100 1 1 about 1100 0000 0000 0000 000 0000 0000 0000 0000 0000 00 00 0000 0000 0000 0000 0000 0000 0000 0000 1011010110 11000110000 1011100110 1100100 0000 1011110110 11001010000 1 100 0010001100110 0000 1 100011000 1 1001 1 10000 11. 00101000 1101000 0000 11001110001101001 0000 110100loop 1101010 0000 1101011000 11010110000 Notation Name YT Zero Rg, PrgMn, PrgPP Y2 Record multiplier in PrgMn Y3 Management - work GPoFF and BUDv. Y4 Write result of addition in Pr Y5 Switching Km Y6 Switching Km Y7 Write result of addition to PRD Y8 Shift by two ratios of the contents of the RedMon Table 3 Note When Y5 1, the output of the HROCF is switched. When Y6 1, the output of Pg is switched FIG. g