SU1295415A1 - Device for calculating fourier-galois transform and convolution - Google Patents

Abstract

The invention relates to computing and technical cybernetics and can be used in digital computing systems intended for signal processing. The purpose of the invention is to increase speed. This goal is achieved due to the fact that the device for calculating the Fourier transform of Galois and convolution contains computational unit 1, multiplication unit 2, computational unit 3, accumulating adders unit 4, memory unit 5 and control unit 6. 18 il. Since 01 4 Cf FIG. one

Description

The invention relates to COMPUTATIONAL TECHNOLOGY and technical cybernetics and can be used in. digital computing systems for signal processing (in particular, for image processing).

The purpose of the invention is to increase speed.

Figure 1 shows the functional scheme of the device for calculating the Fourier-Galois transformation (PFG) and convolution; figure 2 - diagram of the computing unit; FIG. 3 is a diagram of the node accumulating cz maors modulo M; Fig. 4 is a block multiplication circuit; Fig. 3 is a block diagram of connections; Fig. 6 is a block diagram of a memory block; FIG. 7 is a block accumulator block diagram of FIG. 8 is a functional block diagram of the control unit; FIG. figure 9 is a diagram of the node mode; figure 10 is a diagram of the synchronizer computing unit; figure 11 - diagram of the synchronizer multipliers; Fig. 12 is a diagram of an address memory node; on Fig diagram synchronizer accumulating adders; Fig. 14 is a general time diagram of the operation of the device for calculating PFG and convolution; FIGS. 15 to 17 show the time diagrams of the operation of the units of the device for computing PFG and convolution, respectively, in the first and second. rum, the third and fourth, fifth and sixth stages of the device; FIG. 18 shows multiplication schemes for powers of two modulo M 2-1 in the case of P 7.

The functional diagram of the device for calculating PFG and convolution (Fig.) Contain computational unit 1 PFG, multiplication unit 2, computational unit 3, accumulation ditch unit 4, memory unit 5, control unit 6, information inputs 7 and 8, input 9 control information output device 10.

The computing unit (Fig. 2) contains a group of P P-bit input registers 11, a node 12 accumulating adders modulo M, a group of P P-bit dngh output registers 13, information outputs 14, control inputs 15-18.

The node of accumulative adders modulo M (FIG. 3) contains a group of Р Р-bit registers 19 intermediate memory, a group of Р Р-bit d5

0 0 5

0 5

0 5

adders 20, a group of P multipliers 21 for powers of two, information inputs 22, outputs 23, and control inputs 24 and 25.

The multiplication block diagram (FIG. 4) contains the information inputs of the block 26, a group of P P-bit input registers 27, the node 28 of accumulating adders modulo M (performed according to the block scheme of accumulating modulators of M contained in the block 1 PFG), node 29 of connections, a group of P P-bit output registers 30, output 31 of a multiplier, P control inputs-32, control inputs 33 - 37.

The block of connections (FIG. 5) contains P P-bit information inputs 38 and P P-bit outputs 39, and the lower bits of the first, second, ..., P-th inputs 38 are connected to the first, second, respectively. .., Rm bit of the first output 39, second bits of the first, second, ..., P th inputs 38 and connected respectively to the first, second, ..., Pm bit of the second output 39, similarly the senior (P-e) bits of the first, second, ..., P-th inputs 38 are connected respectively to the first, second, ..., P-bit bits of the P-th input 39.

The memory block (Fig. 6) contains a group of P P-bit registers 40, outputs 32, P of control inputs 41,

control input 42.

Block accumulating adders

(Fig. 7) contains informational inputs 43, a group of P 3 P-bit input shift registers 44, a group of P 3 P-bit registers 45 of the intermediate memory, a group of P 3 P-bit of the totalizer 9B 46, outputs 47 control inputs 48–52.

The control unit () contains control inputs 9, mode selection node 53, outputs 54–59, elements HS 60–62, inputs 63–65, calculator synchronizer 66, address memory 67, multiplier synchronizer 68, calculator synchronizer 69, synchronizer 70 accumulating adders., outputs 71-74.

The mode selection node (FIG. 9) contains RS-flip-flops 75, element NOT 76, elements OR 77, element And 78, six-bit shift register 79 (P + +1) -dram shift 80, group (out of six two-input) elements and 81.

The synchronizer of the computational block (FIG. 10) contains (P + 1) -discharge of the shift register 82, RS-trigger 83, element 84, elements 85 and 85.

The multiplier synchronizer (FIG. 11) contains a (P + 1) -discharge shift register 86, RS flip-flops 87, a HE 88 element, AND 89 elements, an OR 90 element,

The address memory node 67 (Fig. 12) contains RS flip-flops 91, HE 92 elements., P-bit shift register 93, AND elements 94, (P + 1)-bit shift register 95, P elements OR 96.

The synchronizer of accumulating summers (FIG. 13) contains RS-flip-flops 97, elements AND 98, element 99 delays and elements OR 100.

The final digital convolution is a numerical procedure defined as follows:

N-1 y (p) Ilh (n-m) x (m), n 0,1,2, ... (1

ifhrO

and is symbolized by y (p) h (n) 4 x (p),

where x (n), h (n) and y (n) are sequences of numbers.

The convolution calculation can be performed using the direct and inverse Fourier – Galois transformations (PPG and OPFG):

f- "

 at (p) OPFG PFG x1, (2)

where PBPG and OPFG are calculated using the formulas

N-1 .1 ppfg X x (k) Their (p) to (p),

 O, N - 1; (3)

 .-х (п) N ElX (k) (n),

n, (

no no

. y , Z,,. ,,,

2 2 2 2 -)

N

-

2 2 2 i

about P-1 (H 2 "" "

54

where x (n) is a digital signal given

on the interval N, i.e. at points 0,1, ..., N - 1 and taking values in the set iO, 1, ..., N - 1; X (k) is the Fourier – Galois spectrum of the signal;

K. (n) is an element of the PFG matrix, which is located at the intersection of the kth row and the nth column of this matrix. The operations in expressions (3) (4) are performed modulo M, where M is an order of the Galus field GF (M), on which PFG are defined. If 2 is chosen as the primitive root of the Nth degree unit / T e GF (M) belonging to the Galois field, then the expression (3) is written in the matrix form (M 2 - 1, where M is a prime number)

2 2 i,

2 ° 2 ° ...

2 ° g,,, ...,

"P-2 P- -L

 - t f)

2 ° 2 2 2,,, ...,

In the case of N P. The inverse transformation is calculated by an expression similar to expression (5), with the only difference that the matrix (n) is replaced by the matrix. (N), the normalization factor and the column vector X are taken. (N) and X (k) are swapped, i.e. OPFG calculation is carried out according to the same algorithm, choo and direct conversion calculation:

(6)

512954156

When calculating the FSGP, after the column x (n), the expression (5) is the record - the multiplication of the matrix X.k, (n) by the vector

a xSO) + 2 ° x (1) + 2 ° x (2; + ... + 2 x (P-1)

2 x (0) (1) + x (2) + ... + 2 x (P-1)

(0) +2 zs (1) + x (2) + ... + (P-1) (7)

2 ° x (0) + 2 x (1) + 24 (2) + ... + 2 x (P-1)

 2 (x (P-1) +2 (x (P-2) +2 (x (P-3) +.. + 2 ° (x (1) +2 (x (0)))) .. .) 2Чх (Р-1) +2 (х (Р-2) + 2 (х (Р-3) + ... + 2 (х (1) + 2 х (0))), ..) 2 (x (P-1) +2 (x (P-2) +2 (x (P-3) + .., + 2 (x (1) +2 x (0))) ...)

2 (x (P-1) (x (P-2) -t-2 (x (P-3)),. + 2 (x (1) + 2 x (0))) ...)

in the column matrix (8) obtained from matrix (7), the terms of each spectral coefficient X (k) are rearranged so that the structure of the expressions for each X (k) is the same, and the multiplication in expressions (8) for each X ( k) is produced by the same factor equal to two in the power corresponding to the number k of the spectral coefficient X (k).

The calculation of X (k) consists in multiplying the first sample of the input sequence x (0) by 2, summing the result with the next (second) sample of the input sequence x (1) and multiplying the sum obtained by summing the result of the last multiplication with the next ( third) by counting the input sequence x (2) and multiplying the sum obtained by 2; ...; summing the result of the last multiplication with the last Pm count of the input sequence x (P-1) and multiplying the sum obtained by 2 (expression (8), O: 6k P-1). Therefore, in al (8:

In the computational order X (k), it is possible to add a cycle consisting in summing the result of the previous cycle with the value of the next sample of the input sequence and multiplying the sum obtained by 2. The cycle for the first count of the input sequence x (0) can be represented by summing nuh (with the first count of the input sequence x (0) and multiplying the sum obtained, i.e. the first count of S 2, Thus the algorithm X (k) consists in sequentially P cycles. When calculating the convolution of two sequences, the operation of the pointwise multiplication of the values of the spectral coefficients of these sequences is performed. The operation of multiplying the two P-bit numbers X H can be written as

 p - and - XH H. (h., 2 + h .. 2 +

+ ... + C2 + 2) X-h.p, -2

p-1

f-a

+ X h. ,, - 2- + ... + X h, - 2 +

h.

2 °

(X h

 -4x

a- -ххp-1

bp.2 + (X-h. h

ip-i

+.

H. & h,

i-0

+ 0)))

2

It is defined as the sum of four convolutions according to the result that one can avoid the occurrence of pseudo-transformation 5 and, consequently, simplify the property, and on the other hand, before reducing the discharge grid, as with this formation.

The resulting expression (9) corresponds to the structure of expression (8) for the JQ calculation of the Pth spectral coefficient, factor X (P-1), in which the input samples represent a sequence of identical numbers X (the first factor), each of which is 15 cuts the value of the first, second h ,, ..,, F th hp, respectively, of the second factor H (when multiplying the input reference (first (n) (x, (n) h (n)) - 2 +

Based on the bp-ud of the hardware implementation of the convolution part, the components of the resulting convolution y (n) x (n) -h (n) are calculated in the following sequence:

factor X) by the value of the logical unit, the input sample remains unchanged; when multiplied by the value of the logical zero, the input sample becomes zero). Therefore, the calculation of the values of the spectral coefficients and the multiplication of two numbers can be produced by the same algorithms.

In order to reduce the length of the discharge grid while preserving the dynamic range of the input data, the splitting of the input words into parts is used.

20

25

2P

+ (x / n) h / n)) - 2 4

+ (x (n) h, (n)) 2

+ (x, (n) h (n)) 2

thirty

In addition, the PFG is performed for the first input sequence x (n), and the value of the spectrum of the coefficients of the second input value H (k), multiplied by the normalizing multiplier N, is carried from the control computer in the device memory. This is due to the fact that when performing a large number of digital processing tasks, only the first sequence changes, and the second sequence when a specific digital signal is executed remains invariably a pulsed one. When the task of processing the memory block of the device is changed, the input 45 .

x (n) x, (n) (n);

Ix (n) k2

h (n) h / n). 2 + h, j (n); | h (n) | (10) The convolution in this case is defined as follows:

y (n) X (n) | (-h (n) (X, (n): h (n)) x

AP 2 + Cx (p) -h (p) +

+ (x; (n) -h, (n)

(eleven

+ x, j (n) h (n)) 2

+ x,., (n)

h, (n).

The device performs a convolution of two numerical sequences (by P samples, each count is an integer not exceeding M 1, i.e., represented in the binary number system 2P-bit binary number). In order to reduce the length of the bit grid, the device uses a partition of the input 2P-bit words into parts consisting of two P-bit words (in accordance with the expression (10)). In this case, the output convolution op54158

It is defined as the sum of four partial convolutions according to equality (11). As a result, the use of Mersenne pseudo-transformation 5 can be avoided and, consequently, the device can be simplified, and on the other hand, the reduction of the discharge grid can be achieved by a factor of 2 as with this transformation.

JQ 15 y (p) (x, (n) h (n)) - 2 +

y (n) (x, (n) h (n)) - 2 +

Taking into account the convenience of the hardware implementation of the hardware, the partial convolutions, which are the components of the resulting convolution y (n) x (n) -x- h (n), are calculated in the following sequence (from left to right):

20

2P

+ (x / n) h / n)) - 2 4

(12)

+ (x (n) h, (n)) 2

25

+ (x, (n) h (n)) 2

thirty

35

40

)

In addition, the PFG is performed only for the first input sequence x (n), and the value of the spectral coefficients of the second input sequence H (k) multiplied by the normalizing factor N-1 N is immediately recorded from the control computer in the memory block of the device. This is due to the fact that in most digital signal processing tasks, only the first input sequence changes, and the second input sequence, when performing a specific digital signal processing task, remains unchanged and represents a pulse response. When the processing task is changed, new values of spectral coefficients are entered into the device’s memory block.

The device works as follows (Fig. 1).

The input data representing 50 is the samples of the first input sequence x (p), where O p P-1, is fed along the input bus 7 to the input of block 1. Moreover, the numerical sequence is fed in two parts x (p) and X2 (p) ( x (n), x, (n) are numerical sequences from the Р Р-bit counts, respectively, Р-senior and Р-low-order bits Р Р input 2Р-bit readings х (п)), 0т55

91

the counts of the numerical sequences x (p) and X (p) enter the input of block 1 sequentially in time, and the feeding of the sequences x, (p) or x (n) begins on the control signal from block 6 of control. The samples of the second input sequence H (k) are fed along the input bus 8 to the input of memory block 5 | Also successively in time. The control computer is connected to the control unit 6 via the bus 9. The control computer provides the supply of the first and second input sequence via the bus 7 and bus 8, as well as the control of the device as a whole. In order to synchronize the operation of all the units of the device and generate control signals, the signals of the initial installation, start-up and the clock frequency are sent to the input of the control unit 6. The process of calculating the convolution is divided into six stages (Figs. 14-17), within each of which one or another unit of the device operates in accordance with the control signals from the control block b.

The device starts to operate after entering the inputs 9 and 9 of the control unit 6 (Fig. 8) of the initial setup pulse and the trigger pulse from the control computer, which sets all the units of the device to the initial state and starts the control unit 6. In this case, at the first stage, block 1 and memory block 5 operate, and the inputs of the first part of the first input sequence X, (n) and the counts of the second input sequence H (k) arrive at buses 7 and 8, respectively. Block 1 produces a PPGF input sequence X (p). After the completion of the first stage of operation, the output of block 1 of the PFG shows the values of the spectral coefficients X, | (k) of the input sequence X; (p). In memory block 5, in the first stage of operation of the device, 2P-times are written the ordinary values of samples of the second input sequence H (k),

At the second stage, the memory block 5 and the multiplication block 2 operate. The input data to the multiplication unit 2 comes from block 1 (X (k)) and from memory block 5. And from the latter, there are counts of the second part) of the second

fO

5415

ten

input sequence H (k), which is a sequence of P P bit bits (P bits of the younger group of 2 P bits of the spectral coefficients H (k)) ,. Multiplication unit 2 produces pointwise multiplication of the values of the spectral coefficients of the two sequences X (k) and H2 (k).

five

0

five

0 5 0 5 0

five

At the third stage, block 1, block 5 of memory, block 2 of multiplication, block 3 and block 4 of accumulating adders work. The input of block 1 receives the samples of the second part of the first input sequence x., J (n). From the output of block 5 of memory, the first input of block 2 multiplication receives the samples of the first part of the second input sequence H (k). To the second input block

The multiplications are calculated in block 1 at the first stage, the counts of the spectral coefficients 1) of the interests X (k), the first part of the first input sequence X (n). To block input

3, samples of the sequence of multiplied spectral coefficients are fed) Hj (k) from the output of multiplication unit 2, Unit 1 produces the PPPG input sequence X ... (n), Multiplication Unit 2 produces pointwise multiplication of the values of the spectral coefficients of two sequences X, (k) and ). Block

3 produces OPFG sequence) H (k) j arriving at its input. At the end of the third stage of work, the calculated values of the spectral coefficients appear at the output of block 1 of the PFG, in block 2 of the multiplication record, the sample values of the sequence of multiplied spectral coefficients X, (k)) appear on the input of block 3, the subtractions (convolution values of X PE) h (p), which are recorded in block 4 accumulating adders, With the help of the latter, the partial values of convolutions are multiplied by factors of 2, 2 and 2 and the results of multiplication are summed up in accordance with expression (12). In the fourth stage, the unit works.

memory, block 2 multiply, block 3

and block 4 accumulating adders. From the output of block 5 of memory, the first input of block 2 multiplies the counts of the second part of the second input

1112

sequences H (k). The counts of spectral coefficients X (k) calculated by the second part of the first input sequence x, j (n) are calculated to the other input of multiplication unit 2 at the third stage. The input of block 3 is supplied with samples of a sequence of multiplied spectral coefficients X (k) Hy (k), calculated at the third stage with the help of block 2 multiplication. The latter produces a pointwise multiplication of the values of the spectral coefficients of the two sequences X k) and H, (k). Unit 3 produces OPFG of the sequence X, (k) H (k), arriving at its input. Block 4 accumulating adders multiplies the convolution values x, (n) h (n) calculated at the third stage by a factor of 2. At the end of the fourth stage of operation in block 2 multiplication, the values of the samples of the sequence of multiplied spectral coefficients X (k) - HgCk are recorded, the output of block 3 is the calculated convolution values x / n) h (n), which are written to the block 4 accumulating; adders.

At the fifth stage, memory block 5, multiplication block 2, block 3 and block A of accumulating adders are operating. From the output of memory block 5, the first input of multiplier 2 receives the samples of the first part of the second input sequence H (k). The inputs of spectral coefficients X (k) calculated by using block 1 in the third stage are fed to another input of multiplication unit 2. the second part of the first input sequence X (p). A sequence of multiplied spectral coefficients X, (k) (H), calculated at the fourth stage in block 2 multiplication, is fed to the input of block 3. The latter produces a pointwise multiplication of the spectral coefficients of two sequences X, j (k) (k). Block 3 produces OPFG sequence X (k) - H, j (k). Block 4 accumulating adders multiplies the convolution values x (n) calculated at the fourth stage. “(N) by a factor of 2 and summing with the previous convolution value, i.e. (x, (n) h, j (n)) - 2 + + (x,; (n) h, (n)) 2). At the end of the p-th phase of work in block 2. multiplying

1512

the readings of the readings of the interconnected spectral coefficients H, (k) Xj (k) are recorded, and the output of block 3 is the calculated values of the convolution x, j (n) (-h (n)), which are written into block 4 accumulating adders. The sixth stage employs block 3 and block 4 accumulating adders. At the input of block 3, counts of a sequence of multiplied spectral coefficients X (k) H (k) Block 4 accumulating adders multiply the convolution values x- (n) calculated at the fifth stage ( factor of 2 ° and summation with previous values of light rtki, ie (x, (n) h (n)) 2 + (x, (n) h, (n)) 2 + (XgCn) l h, 2 (n)) 2 °. At the end of the sixth the stages of work at the output of block 3 appear the computed values of convolution x (n) h (n), which are recorded in block 4 accumulating adders, multiplied by this block by a factor 2 and summed up with the previous convolution values, i.e. The output of the block 4 accumulating jpoB summations of the output convolution counts corresponding to the expression (12) appear. After completing the sixth stage of operation, the device is ready to process the following sequence of input data.

Block 1 works as follows.

Input data representing samples of the numerical sequence x (n) or x, (n) (P samples of P bits each) are fed through bus 7 of the sequential input to the inputs of registers 11, 11p of the group of input registers 11 (Fig. , 15). Input 15 combines the clock inputs of input registers 11-11. (P registers are a group of P-bit data storage registers with a record on the leading edge of the pulse). At the time of the first readout of the input sequence (for example, x. (0)) x (n), the first pulse of the clock frequency arrives at input 15 from control unit 6. With the arrival of this pulse, the first countdown is written to all input registers 11 and, from their outputs, goes to the second inputs (inputs B) of adders 20 of block 12 of modulating M modulators (FIG. 3). Impulse coming

to input 17 (input 25 in FIG. 3) synchronously with the first clock pulse, zeroing of intermediate memory registers 19 of block 12 modulo M accumulators is performed. Input 16 (input 24, FIG. 3 combining clock inputs of registers 19 of the intermediate memory, clock pulses are received, shifted in time by half of the clock pulse period. Until the first pulsing frequency pulse arrives at input 16, the value of the first count Hu (0) of the input sequence, fed to the second inputs of adders 20, total with the data received at the first inputs (inputs A) of the adders 20 from the outputs of the intermediate memory registers 19 (zero values), and the resulting sum goes to the inputs of the multipliers 21 by powers of two. The first multiplier 21, multiplies by powers of two, 2, the second multiplier is 21, - by 2, ..., the Pth multiplier is 21r - by.

The resulting multiplication products:, (0) -2 (where k is the number of the calculated spectral coefficient X (k),) are fed to the inputs of registers 19 of the intermediate memory and with the arrival of the first clock pulse arriving at the input 16 are written to these intermediate memory registers. The summation operation is performed modulo M 2-1, which is accomplished by summing the possible transfer to the (P + 1) -th bit with the least significant bit in each adder 20. For this, the transfer output of the adder 20 is connected to its own transfer input. The multiplication operation by powers of two is realizable by multipliers 21-1-21 p, by powers of two, modulo an integer of M 2 -1, where P is a prime number. Therefore, multiplications by powers of two are DRPS codeword offsets. One can realize multiplication by powers of two modulo M - 1 by simple commutation of wires. Symbolically, the operation of multiplying by a power of two is depicted as P blocks 21 (for the case of P 7, the implementation of these blocks is shown in Fig. 18).

At the moment the second countdown of the input data arrives, the second clock pulse arrives at the input 15 and the second count of the input sequence X (1) is written to all input registers 11 and from their outputs goes to the second inputs of the adders 20. At the outputs of the latter the inputs (inputs B) of the data from the input registers 11 (x (1)) and the data that 0 drank from the outputs of the registers 12 of the intermediate memory recorded in them on the previous cycle (x (0) 2), i.e. the sum x (1) + is formed. 2 The sum of the sum from the outputs of the adders

 20 are fed to blocks of 21 multipliers for powers of two and from their codes the inputs to the registers 19 of the interim memory. The second pulse arriving at input 16 permits writing to the registers 19 of the data supplied to their inputs, i.e. 2 (x (1) + 2 X, CO)).

5 at the moment when the third input data x is received, ((2) the operation cycle of the unit 1 is repeated; the registers 19 record the values accumulated over three cycles in each adder 20

0 partial sums of the corresponding spectral coefficients. This process is repeated P times. On the Р-th cycle, at the moment of post-termination of the P-th reference of the input data, the input 15 enters

5: the clock pulse and the pth count of the input sequence Hz (P-1) are written to all input registers 11 and from their codes come

to the second inputs of the adders 20. At the outputs of the last; the sums of the data entered at the second inputs (inputs B) of the data from the outputs of the input registers 11 s (P-1) and the data received from the outputs of the registers 19 intermediate memory 5 ti recorded in them on the previous cycle are formed: (2 (xy ( P-2) + 2 (x, (P-3) + + ... + 2 (x, (1) +))) ...). Sums x (P-1) 4. 2 (x, (P-2) + - 2 (x, (P-3) + ... + 24x (1) -f 0 - “, (0))). ,.), OSk P-1 from the outputs of adders 20 are fed to blocks of 21 multipliers by powers of two and from the codes of these blocks are fed to the inputs of registers 19 of the intermediate memory. The pth impulse arriving at input 16 permits writing data to the registers 19, which have become discontinuous to. their inputs according to the expression

2Чх / Р-1) + 2Чх (Р-2) +

+ 2 (x / r-3) + ...

+ 2 (x, (1) + 2 x / 0))) ...) ..

This expansion completely coincides with expression (8) for spectral coefficients, in which expression (13) (Oik iP-l) corresponds to each spectral coefficient X (k). The P values of the spectral coefficients X (k) from the outputs of the registers 19 are fed to the inputs of the output registers 13 of the PFG block 1 and when the enable pulse arrives at the input 18 that coincides in time with the (p4-1) -th clock frequency pulse (Fig. 15), the registers 13 are written. Thus, at the end of the (P + 1) -th clock frequency pulse, unit 1 finishes calculating the PFGs, and the P-bit outputs of block 1 show the values of the spectral coefficients X (k) and block 1 is ready to the processing of the following sequence of input data.

Unit 3 device produces OPFG sequence of values of spectral coefficients, for example, X / k) H, (k).

The nominating factor N, which is entered in the calculation of OPFG by equality (4), is studied in the sequence H (k), the samples of which are received from the control computer already multiplied by N. Replacement (5) of matrices of powers of two. ji (p) per matrix (b) X (p), which differs only in the arrangement of rows, is taken into account in block 3 by rearranging multipliers 21 p of power two in accordance with the permutation of rows of matrix X (p). At the same time, the order of output numbers of block 3 is preserved and, in fact, cheng is no different from block 1. Block 3 has the same circuit as block 1 (Figures 2 and 3) with the only difference that the multipliers 21–21 by degrees deuces are built as follows: multiplier 21 multiplies by 2 °, multiplier by 2, multiplier 21 j - by 2 /, multiplier 21 - by, .-, multiplier 21Р - by 2 and 17 (in block 3 for the convenience of

J5

20

25

The description of the control terminal number is given in brackets). (13) Multiplication unit 2 produces pointwise multiplication of the values of the spectral 5 coefficients and works as follows (Figures 4, 3 and 15).

The input data representing the counts of two numerical sequences X (k) or X (k) of the first factors and H (k) or H g (k) of the second factors, for example X (k) and H (k), are input to the inputs 26 input registers 27 and inputs 32 of the logical zero setting of the same input registers. Moreover, the values of the first, second, ..., P-th spectral coefficients of the first factors X (k) or X (k) are received in parallel code, respectively, on P-bit inputs 26 of the first, second, ..., P-th input The P-bit registers are 27, and the values of the first, second, ..., P-th spectral coefficients of the second factors H (k) or H, j (k) are received in a sequential code (bitwise, starting with the least significant Dov) to one-bit inputs 32 of the installation of a logical zero, respectively, of the first 32 ,, second - 32 ,, ..., R-th - 32 p input registers 27. Clock pulses h The signals from the control unit 6 are fed to the input 33 of the multiplication unit 2. Input 33 combines the clock frequency inputs of a group of input registers 27. With the arrival of the first clock frequency pulse, the values of the first factors (for example, X (k)) are written to the input registers 27 and from their outputs go to the second inputs of the adders 20 of the unit 28 of the modulo accumulators modulo M (fig.Z)

45 The first clock pulse arriving at input 35 also clears the intermediate memory registers 19 of block 28 of modulating M accumulators (but 50 measure the control inputs 34 and 35 of block 28 used in multiplier 2, are shown in brackets, FIG .3) This numbering is introduced for ease of description of the control unit 6. Jb

55 THIS time, the inputs 32 of the installation of the logical zero of the input registers 27 receive the values of the first (lower) bits of the second factors (for example, H (k)), which are corrected

35

40

171

output data of the input registers 27 are described as follows; when a 32 pth input register 27 (1) arrives at the input, in which the value of the first factor X (k) is written, the value of the first (lower) bit hj, (k) of the second factor H, j (k) s of the corresponding logical unit The code data of the nth register 27 remains unchanged, and when 32 values at the input correspond to a logical zero, the output data of the nth register 27 become zero, i.e. the multiplication of the k-ro value of the first factor X (k) by the value of the first bit k-ro of the second factor occurs).

The corrected output data X | (k) - h, jfl (k) of the input registers 27 are fed to the second inputs (inputs B) of the adders 20 of block 28 (FIG. 3), where they are summed up with the data received at the first inputs (inputs A) of the same adders from the outputs of the intermediate memory registers 19 (zero values) and the sum (X (k) h, jo (k) + 0) is formed at the output of the adders 20. The output of adders 20 is fed to the inputs of multipliers 21 by powers of two, and in all multipliers 21 of block 28 accumulating adders modulo M, used in block 2, multiplication is performed by 2. The output data from the blocks 21 / is fed to the inputs of the registers 19 of the intermediate memory. Input 34, which combines the clock frequency inputs of the intermediate memory registers 19 of block 28, receives clock frequency pulses that are shifted in time by half of the clock pulse period. The first impulse received at the input 34 permits the recording in the registers 19 of the intermediate memory of the sums received at the outputs of the adders 20 and multiplied by 2 using the multipliers 21, i.e.

(k.h (k).

With the arrival of the third clock pulse at the input 33, the operation cycle of multiplication unit 2 is repeated and partial values of X (k) "H, accumulated over three cycles in adders 20 are recorded in intermediate memory registers 19 (This process repeats P times . On

9541518

,, The Pm cycle of operation of block 2 multiplying, with the arrival of the Pth pulse of the frequency clock at input 33, the values of the first 5 factors X (k) are written to the input registers 27. At the same time, the inputs 32–32p receive the values. The P – x bits of the second factors h ((k), which correct the output data of the input registers 27, Adjusted output data X, (k) h, j (p. ,) (k) input registers 27 arrive at the first inputs of adders 20 of block 28, where they are added to the data that went to the second inputs of adders 20 s; the outputs of register 19 of intermediate memory and the sum of

X (k) -h ,,., J (k) -f

p-1

+ 2 () .h (p. ,,, (k) +

, p-1

+, .. + 2 (x,. (K)) +

+ 2 x, i (k) -h (k).

The output of the adders 20 is fed to the multipliers 21, where they are multiplied by 2 and then to the inputs of the intermediate memory registers 19, the Pth clock frequency pulse, which is fed to the input 34, allows writing to the intermediate memory registers 19 entrances;

2 (X / k) .h, (p. ,, (k) + (X, (k) .h2 () (k) + + ... (x (k) -h (k) + + 2 X , (k) -hj, o (k)) ...)

(14)

Expression (14) completely coincides with extrusion (9) to produce two P-bit numbers X and N. P values of the products of spectral coefficients X., (K) H, j (k), from outputs 23 of registers 19 of the intermediate memory come at the same time on the P P-bit inputs 38 of the block 29 of the connections (FIG. 3). Block 29 of connections and a group of P P-bit output back-up registers 30 serve to implement the sequential output P of the values of the products X / | (k) H. (k) from block 2 multiply to block 3 in this step of calculation when block 3 is working. | With the help of block 29 of connections, the first (lower) bits of the first and second bits are input to the input of the first shift register 30, ..., the P-th product of the spectral coefficients, the second bits of the first second, ..., the P-th spectral coefficients, ..., are input to the input of the second shift register ..., the P-th shift register 30 is received by the P Px bits of the first second, ..., Pth product of spectral coefficients. The data input to the inputs of the shift registers 30 is recorded by applying to the input 36 an enabling pulse that coincides in time with the (P + 1) -th clock frequency pulse. The outputs of the lower bits of each of the P output shift registers 30 are combined into one P-bit bus 31. At the same time, after writing to the shift registers

The 30 bits on the first output of the P-bit bus 31 appear the value of the first bit of the first product.

X (0) - H, (0), at the second output - the value of the second discharge of the product X, (0) - H, j, (0), ..., at the Pth output - the value of the Pth discharge product X (0) E 0). To obtain at the output of bus 31, the value of the second product X (1)), it is necessary to shift the contents of the P shift registers 30 to the left by applying control pulses to inputs 36 and 37. At the outputs of the lower bits, the values of the second product appear XD1) H , (1): on the first pin of the P-bit bus

31 is the value of the first bit X, (1) H (1), on the second. The value of the second bit of the product Hn (1) - X (1), ..., on the P-th pin is the value of P-th bit product Xi (1) H ,, (1). I

To obtain P values of the output of X, (1) N. (1) it is necessary to make (P-1) left shifts of the contents of the shift registers 30. The shift pulses are fed to inputs 36 and 37 during the operation of block 3 (provide a consistent input of values products X (k) Н, (k) in block 3).

The memory unit operates as follows.

The input data is a numeric sequence.

five

0

five

0

five

0

telrst (P counts of 2P bits each,), are fed through bus 8 after the pre-slide input to the inputs of each shift register 40 (Figures 6, 14 and 15). At the moment when the first count of the input sequence H (0) arrives at the input 41 of the clock frequency of the first shift register 40, the first clock pulse arrives from the output of the control-6 unit. With the arrival of this pulse, the first count is written to the first shift register 40. At the moment the second count of the input sequence H (1) arrives, a second clock pulse arrives at the clock frequency input 41 of the second shift register 40 and the second count is written to the second shift register 40. In the same way, the remaining counts of the input sequence H (k) are written in the corresponding shift registers 40. After the last P-th count of the input sequence H (P-1) is written into the P-th shift register 40 process of recording the input sequence H (k) is completed (this corresponds to the memory unit 5 in a first step of calculating, 15). The data recorded in the shift register 40 is fed to the output of memory block 5 from the outputs of the most significant bits of registers 40, starting with the lower bits. With recorded data in pe0

five

32.32,

Young5

The drivers 40 on the inputs of the bits of the registers 40 contain the values of the first (minor) bits P of the input sequence H (k). To obtain at the outputs 32 - 32P of the values of the second bits of the samples H (k), the contents of the registers 40 are shifted to the left by applying control pulses to the inputs 41 and the input 42.

. In this case, the values of the new bits from the outputs 32 are fed to the inputs of the serial input when shifted to the left D, the corresponding 11x registers 40, and are written to the place of the higher bits that are shifted one time to the left. Thus, a cyclic shift of the data recorded in the registers 40 is performed. Repeating the shift of the data in the registers 40 (P-1) times, get at 32 inputs 32 values of the lower digit bits of the 2P - digit number sequence H (k). Minor P bits of the sequence

2112

H (k) correspond to the second part of the numerical sequence H (k), For getting at the outputs 32 P senior. The 2P-bit samples of the H (k) corresponding to the first part of the numerical sequence H (k) must be made of P cyclic shifts of the contents of the registers 40. As the P shifts of the registers 40 follow, the P bits of the second counts in the outputs 32 successively appear parts of the numeric sequence H, j (k). In the same way, the values of the following P bits of counts of the first part of the numerical sequence H f (k) are obtained when P shifts the contents of registers 40. The operation of memory block 5 in the cyclic shift mode corresponds to the work of this block in the second - fifth calculation steps (Fig.14 - 17).

In block 4 accumulating summators (Figs. 7, 14-17), the output convolution is calculated by multiplying the partial values of the convolutions arriving at its inputs 43 by factors and 2 °, and summing the obtained works in accordance with the expression (12 ). Before the operation of block 4, the intermediate memory registers 45 are reset by a pulse that arrives synchronously with a trigger pulse from the control computer to input 52. Input P-bit samples of the calculated partial convolution values are fed to inputs 43 of the SR-bit input shift registers 44 the first (lower) bits of the P input samples are fed to the inputs (P + 1) of the corresponding input registers 44, the second bits of the input samples are fed to the inputs of the (P + 2) bits of the corresponding input registers 44, ..., The P bits of the P input samples are fed to the 2P-X bits of the corresponding input registers 44. When a clock pulse arrives at input 48, which combines the clock inputs of the group of input shift registers 44, the data received on the P input is written - Dov registers 44, starting with the inputs (P + 1) -th bit and ending with the inputs 2P-GO bit and ZR-bit input registers 44, i.e. input data

522

immediately shifted by P bit to the right, which corresponds to multiplication by 2, Therefore, there is no need to multiply by 2 partial values of convolution X; | (n) b (n) and X2. (n) h (n) arriving at inputs 43 of block 4 accumulating adders in the third and sixth stages of calculations.

Partial values of the convolution X (p) t h, j (p) at the end of the third stage of the calculation are fed to the inputs of registers 44. Input 48 combines the inputs of the clock frequency of the group of input registers 44.

With the arrival at the input 48 at the third stage of the calculations (P + 1) th pulse | sa clock frequency delayed by half a clock pulse period (Fig. 16), partial convolution values x; (n) -h (n) are written to input registers 44, From the outputs of the latter, partial convolution values multiplied by 2, t . {x (n) h, j (n). 2, are fed to the second inputs (inputs c) of adders 46. The first inputs (inputs A) of adders 46 receive data from the outputs of registers 45 of the prom: daily memory (zero values). The resulting amount goes to the inputs of the intermediate memory registers 45 and with the arrival of the first clock pulse in the fourth calculation step (Fig. 16) is written to the registers 45. The partial convolution values x (n) h (n) at the end of the fourth calculation step are received at the inputs registers 44 and arriving at input 48 in the fourth stage of the calculation of the (P + 1) -th pulse of a clock frequency delayed by half a clock period of a 1-1 pulse, are written to the input registers 44. Partial convolution values recorded in registers 44 (x (n) W h , (n)) 2, it is necessary to multiply, in accordance with the extrusion (12). To do this, in the fifth calculation step, the contents of the registers 44 are shifted to the right by applying P control pulses to the inputs 48 and 49 (Fig. 17). The partial convolution values obtained at the inputs of registers 44 (x (n) (n)) 2 are fed to the second inputs of adders 46, where they are added to the data stored in the registers of the intermediate memory 45, the resulting sum ((x (n) {ht (n),) + (xi (n) hi (n))) with the arrival

2312

(The P + D-ro pulse of the clock frequency at the fifth stage of the calculations to the input 51 is written to the registers of the intermediate memory.

Partial values of the convolution X, j (n) "hjCn) at the end of the fifth stage of the calculation are fed to the inputs of registers 44 and with the input to input 48 (P + D-ro pulse of a clock frequency delayed by half a clock pulse period, input registers 44. Partial convolution values recorded in registers 44 ((x (n) h,., (n)) f must be multiplied by 2 in accordance with expression (12), i.e. the value defined by ((XdSp) h (n)) 2, is shifted by P bits to the left, which corresponds to multiplying X, j (n) h, j (n) by 2 °. For this, at the sixth stage, (Fig. 17), the contents of registers 44 are shifted to the left by supplying P control pulses to inputs 48 and 50. Obtained at outputs: registers 44 partial convolution values ((x (n) -h,. (n)) 2 served to the second inputs of the adders 46, where they are summed with the data stored in the registers 45 of the intermediate memory. The resulting sum ((x (n) x h (n)) -2 + + (x / n) eh, (n) .24 (x2 (n) (n)) - 2 ° with the arrival of the (P + 1) -th pulse of the clock frequency at the sixth stage of the calculations at the input 51 is recorded in the registers 45 of the intermediate memory. Partial values of the convolution x (n) h, (n) at the end of the sixth stage of the computations arrive at the inputs of registers 44 and with the arrival at the input 48 of the (P + 1) -th pulse of the clock frequency delayed in time for half the clock pulse period. are written to the input registers 44. From the outputs of registers 44, the partial convolution values ((x2 (n) h (n)) 2 are fed to the first inputs of adders 46, where they are added to the data stored in registers 45 of the intermediate memory. Obtained at the outputs of adders 46 sum (x j (n) h - (n)) - 2 + + () (h, (n)) (x ,, (n) h | n)) 2 + (x (n) x h (n)) 2 corresponds. expression (12; for the resultant convolution. The data from the outputs of the adders 46 are fed to the outputs 47 of the block 4 of accumulating adders.

1324

Control block 6 serves to issue control pulses to all units of the device and works as follows (FIG. 8, FIGS. 9-17).

At the input 9 of the control unit 6, a pulse of the initial installation comes from the control computer. Input 9 receives a triggering pulse from the control computer. The input 9 receives the pulses of the clock frequency. The entire operation of the device is divided into six stages with a duration (P + 1) of periods of clock pulses each. At each stage of operation, control unit 6 is supplied with control pulses in various units of the device. Before the control unit starts operation, the initial installation of the mode selection unit 53 is made by a pulse arriving at input 9 (3 nodes 53. With the arrival of the triggering pulse, node 53 starts to work, and at its output 54 a pulse appears that starts synchronizer 66 and node 67 memory addresses that control the operation of the fleet 1 and memory block 5 at the first stage of computation (Fig. 14). Moreover, synchronously with the triggering pulse from the control computer, the control output 52 neither accumulates adders reset register 45 prome the weft memory of the accumulating adders block (Fig. 7). At the end of the first stage of operation of the control unit 6, the output 55 of the node 53 has a pulse that changes the operation mode of the address memory node 67 and starts the multiplier synchronizer 68. These nodes control operation of memory block 5 during the second to fifth stages of the calculations and block 2 of the multiplier at the second stage of the calculations.

At the end of the second stage of operation of the control unit 6, an output appears at the output 56 of the node 53, which starts the synchronizer 66, synchronizes 68 multipliers, the synchronizer 69 and the synchronizer 70 of accumulating adders. These synchronizers control the operation of blocks 1-4 in the third stage of the calculations. At the end of the third stage of operation of the control unit 6, a pulse appears at the output 57 of the node 53, which triggers the synchronizer 68 multipliers 68, synchronizer 69, synchronizer 70 accumulating adders. These synchronizers control the operation of blocks 2, 1 and 4 on. fourth stage calculations. At the end of the fourth stage of operation of the control unit 6, a pulse appears at the output 58 of the node 53, which starts the multiplier synchronizer 68, the synchronizer 69, the synchronizer 70 of accumulating adders. These synchronizers control the operation of blocks 2-4 in the fifth calculation step. At the end of the fifth stage of operation of the control unit 6 at the output 59 of the node 53 a pulse appears that stops the operation of the address maker 67 and starts the synchronizer 68 multipliers, the synchronizer 70 accumulating adders. Synchronizers 69 and 70 control the operation of block 3 and block 4 accumulating adders in the sixth computation stage.

The mode selection unit 53 of the control unit 6 operates as follows (FIGS. 9, 14-17).

At the first input 9 of the node 53 a pulse of the initial installation comes from the control computer, to the second input 9 ,; - a triggering pulse from the control computer, the clock frequency pulses arrive at the third input 9. The initial setup pulse resets the six-bit 79 and (P + 1) - 80-bit shift registers and the first RS-flip-flop 75, With the arrival of the trigger pulse, the level of Log.1 is set at the output of the second RS-flip-flop 75. The same trigger pulse through the NOT element 76 sets the level of the Log.O on the control inputs of the six-bit 79 and (p + 1) -80 digit shift registers, to the first inputs of which the Log.1 level is constantly supplied. When the inputs of the clock frequency of the registers 79 and 80 of level Log.1 from the output of the second RS flip-flop 75 through the elements OR 77 in the first (lower) bits of the registers 79 and VO, the value of Log.1 is entered. Log level the first output of the register 80 is fed to the K input of the second RS flip-flop 75 and to the S input of the first RS flip-flop 75. At the same time, you

During the second CZ-trigger 75 set-gg de register 80 appears level

the level of the Log.O is cast, and on the output of the Log.1, which allows the first CZ-trigger of the first trigger to level through the second element AND 81 levels

 Log.G, which permits passage - Log.G from the second output of register 79,

through the element And 78 pulses i at the output 55 of the node 53 are uro5 O 0

five

0

five

0

clock frequency, which arrive at the second input of this circuit.

The pulses of the clock frequency from the output of the element And 78 through the second element OR 77 are fed to the input of the clock frequency of the register 80. The level Log.1 from the first output of the register 80 also goes to the input of the element 81 of the group of six elements And, to the other input of which comes the level Log .1 from the output of the register 79. At the same time, in the code of the first element AND 81 of the group, the level of Log.1 is found until the value of Log.1 recorded in the first discharge of register 80 is shifted to the second discharge upon receipt of a clock frequency pulse on the clock input of the register 80. Following A clock pulse is used to shift the contents of register 80 by one more bit to the right, and so on, until Log.1 is on the (P + 1) -th output of register 80. In this case, the level of Log.1 goes through the element OR- 77 to the input of the clock frequency of the register 79 and the contents of this register is shifted by one bit to the right, i.e. At the second output of register 79, the level of Log.1 appears, which is fed to the first input of the second element AND 81 of the group. This concludes the first stage of operation of the node 53, which is equal to the duration of the triggering pulse from the control computer plus the duration P of the clock frequency periods.

The triggering pulse is equal in duration to clock pulses and syn- chronized with a clock frequency. Therefore, the first stage of operation of the control unit with relays is the duration of the (P + 1) -periods of the clock frequency. The (P + 1) -th register output of 80 connections with the input of the serial input when the register is shifted to the right and when the next clock frequency arrives. Log.1 value is recorded in the first register bit 80. Thus, with the input (P + D-ro pulse clock frequency or the first clock pulse frequency of the second stage of operation of the node 53 at the first output0

271

Wen Log.1 for one period of the clock frequency. Every next (P + 1) cycle of operation of the node 53, the levels of Log.1 alternately appear at its outputs 56 - 59 during the first period of the clock frequency of each stage of operation of the node 53. At the end of the sixth stage of operation at the (P + 1) th output of the register 80, the level of Log.1 appears, which through the OR 7 element is fed to the input of the clock frequency f of the horn 79 and the contents of this register is shifted by one bit to the right, i.e. all outputs of register 79 are log levels. node 53 finishes its work before the next control pulses arrive at its inputs. As a result, during the operation of the node 53, pulses are generated at its outputs 54-59, which control the operation of the synchronizers 66 - 70 of the control unit 6 (Figures 8 and 14).

The synchronizer 66 (block 69 is similar to block 66) works as follows ((£ 10. 14 - 17).

At the input 63 of the synchronizer 66, triggering pulses are received from node 53. At the clock input 9, clock pulses are received. The control input of the (P + 1) -discharge shift register 82 is continuously supplied with the level Log.1. With the arrival of the trigger pulse at the input of the serial input when shifting to the right (P + 1) -discharge shift register 82, the S-input of the first RS flip-flop 83 and output 17 is set to Log.1. At the same time, the level of Log.1 appears at the output of the first RS flip-flop 83, which allows the passage of clock pulses through the AND 85 element to the output 15. The clock pulses also go to the input of the clock frequency of the register 82 and the input of the HE element 84. With the arrival of the first clock the pulse in the first (lower) digit of de register 82 is recorded the value of Log.1 and on its

The first output appears at the level of Log.1, which is fed to the bJ-input of the second RS-flip-flop 83. At the same time, the output of this RS-flip-flop appears at the level of Log.1, which allows the passage of inverted clock pulses through the second element 60 to the output sixteen.

With the arrival of the second clock pulse, the contents of register 82 are shifted by one bit to the right and

five

A1

g About 5 about

0 35 40 45

0 55

528

The second output of this register is the Log level. G. Each subsequent clock pulse shifts the contents of register 82 by one bit to the right. In this case, the clock pulses pass to the output 15, and the inverted clock pulses pass to the output 16 of the synchronizer 66. With the arrival of the Pth clock pulse, the Logic output of Level 82 appears at the Pm output of the register 82, which arrives at the input of the third RS-flip-flop 83 and at its output sets the level of Log.1. In this case, the inverted P-th pulse frequency is passed through the AND 85 element, which arrives at the R input of the first RS flip-flop 83 and sets the Log.O value at its output, which prohibits the further passage of the clock pulses through the AND element 85 to the output 15. With the arrival of the (P + 1) -th pulse of the clock frequency, a level Log.1 appears at the (P + 1) -th output of the register 82, which enters the R-inputs of the second and third RS-flip-flops 83 and their outputs Log levels are set. At the same time, the inverted clock pulses from the output of the element HE 84 through the elements 60 are prohibited from passing. The level Log.1 of the (P + 1) -th output of the register 82 goes to output 18. With the arrival of the next clock pulse, the contents of register 82 are shifted by one the bit to the right and on all outputs of register 82 are set the levels of Log.O. As a result, during the operation of the synchronizer 66, pulses are generated at its outputs 15-18, which control the operation of unit 1.

The synchronizer multipliers 68 operates as follows (Fig.11,14-17).

The input 64 receives trigger pulses from node 53. At the clock input 9, the clock pulses arrive. At the input 72 of the synchronizer 68 multipliers, the control pulses of the output 72 of the synchronizer 69 are received (Fig. 8). These pulses come to the output 37 and through the element OR 90 also to the output 36 of the synchronizer 68. Otherwise, the operation of the synchronizer 68 multipliers fully corresponds to the operation of the synchronizer 66.

2912

The address memory node 67 operates in a manner (FIGS. 12, 14-17),

At the inputs 54, 55 and 59 of node 67 of. trigger pulses step from node 53. Clock frequency pulses are sent to clock input 9. The input of the mode control of the P-bit shift register 93 and the first input of the (P + 1) -shift shift register 95 continuously provide Log.1 level. With the arrival of a suppressing imgguls at the input 54 of the sequential input when the shift is shifted to the right of the P-bit the shift register 93 appears at the level of Log.1 and with the arrival of the first clock pulse, which is fed to the input of the clock frequency of the register 93, the first (low) bit of the register 93 records the value of Log.1 and at its first output Log level 1 appears, which through the first The OR 96 group element arrives at the output 41 of the node 67. With the arrival of the second clock pulse, the second output of the register 93 appears at the level of Log.1, which through the second element OR 96 of the group enters the output 41 of the node 67, ..., with the arrival The Pth I1Lpulse of the clock frequency at the Pm output of the register 93 appears at the Log level, which through the OR 96 group element enters the 41p output. At this point, the memory node 67 finishes the operation corresponding to the first stage of the operation of the device.

With the arrival of the trigger pulse at the input 55, which is connected to the input of the circuit 92 and the S-input of the first K5-trigger 91, the level of the Log.O and output is set at the input of the mode control (P + 1) -discharge shift register 95. the first RS flip-flop, the level of Log.1, which allows-the passage of clock pulses through element I 94 to the input of the clock frequency of the register 95. The first pulse of the clock frequency, received at the clock frequency input of the register 95, records the level of the Log, 1 in the first (junior) de register register 95 and on the first output of this regis RA is a logic 1 level which is applied to the second RS-Tr ggera 91. At the output of the second RS- trigger level is Log 1 which permits the passage of the inverted clock pulses chasto15 30

You are at the output of an AND 94 element. From the last output, the inverted clock pulses arrive at output 42 and through the P elements OR 96 groups to outputs 41 |, - node 67. After the triggering end, entered at input 55, is entered at the control input of the register 95 Level 1 appears and when the next clock pulse arrives, the contents of register 95 are shifted by one bit to the right.

In this case, the second output of the register 95 appears level Log.1. With the introduction of each next pulsing frequency pulse, the contents of register 95 are shifted by one bit to the right and upon receipt of the (P + 1) -th clock frequency pulse of the second stage of operation of the device, the Log level appears at the (P + 1) -th output of register 95 . 1, which arrives at the R input of the second RS flip-flop and sets a Log level at its output. It prevents the (P + 1) th inverted pulse from passing. clock frequency to the outputs 42 and 41 41. node 67. Level Log.1 s (P + D-ro output register 95 also goes to the input of the serial input when the right register is shifted and when the first clock pulse arrives at the third stage of operation in the first discharge of register 95, the value of Log.1 is recorded. Otherwise, the operation of the node 67 at the stage of operation of the control unit 6 fully coincides with the operation of this block at the second stage of operation. In the next fourth and fifth stages of the operation of the node 67, the cycle repeats. at the beginning of the sixth stage of operation of the node 67 zap The output of the first RS flip-flop appears at the output of a gatse pulse at the input 59. The level that prevents the clock pulses from being transmitted through the AND 94 element. The same triggering pulse clears the contents of the register 95. As a result, during the operation of the node 67, at its outputs 42 and 41, pulses are generated that control the operation of the device memory unit 5. The synchronizer 70 of the accumulator szmmmators operates as follows (FIGS. 13-17),

311

The inputs 57–59 post trigger pulses from node 53. The first and second inputs of block 70 receive control pulses from the fourth 74 and second 72 outputs of the synchronizer 69, respectively. Control pulses fed to input 74 through element 99 delays and the element OR 100 arrive at output 48 with a delay of half the period of the clock frequency. From the output of the delay circuit, the same pulses are fed to the R inputs of the first and second RS flip-flops 97 and the outputs of these RS flip-flops set the level of Log.O. The start pulse from input 57 through element OR 100 passes to output 51. The triggering pulse, which is fed to input 58 synchronously with the first clock pulse, is passed to the fifth stage of the calculation at the S input of the first RS flip-flop 97 and its Logout level appears. 1 which allows the passage of pulses from input 72 through element AND 98 to output 49 and then through element OR 100 to code 48, as well as pulse from input 74 through element And 98 and element OR 100 to exit 51 in the fifth calculation step. A triggering pulse arriving at input 59 synchronously with the first clock pulse, at the sixth stage of the calculation, is fed to the S input of the second RS flip-flop 97 and its output is Log.1, which allows the passage of pulses from input 72 through the element E 98 to exit 50 and further through the element OR 100 to exit 48, as well as the pulse from input 74 through element E 98, the element OR 100 to exit 51 in the sixth calculation step. A pulse delayed by a half period of the clock frequency from the input 74 sets the first and second RS-flip-flops 97 to zero. As a result, during the operation of the synchronizer 70 accumulating adders, pulses are generated at its outputs 48-51 which control the operation of the block 4 accumulating adders.

Claims (1)

Invention Formula A device for calculating a Fourier-Galois transform and convolution comprising a multiplier and a memory block whose output is connected to the transducer 41 5 0 5 0 five five 532 The first input of the multiplication unit, characterized in that, in order to increase the speed, the first and second computing blocks, a block accumulating adders and a control block, the information input of the first computing block are the first information input of the device, the output of the first computing block is connected to the second input of the multiplication unit, the output of which is connected to the information input of the second computational unit, whose output is connected to the information input of the block accumulating adders, output which is the information output of the device, the first, second, third, fourth and fifth outputs of the control unit are connected respectively to the control input of the first computational unit, the address input of the memory unit, to the synchronous input of the multiplication unit, to the control input of the second computing unit and to the synchronous input block accumulating adders, and the information input of the memory block is the second information input of the device, while the control unit contains a node of the mode, the two synchronizers calculate blocks, an address memory node, a multiplier of 1-1 bodies, a accumulator of accumulators and three OR elements, the first, second and third inputs of the mode selector node being the initial setup input, the start input and the device clock input, the first and third the outputs of the mode selector node are connected respectively to the first and second inputs of the first OR element, the output of which is connected to the input of the first synchronizer of the computing unit, the first, second and sixth outputs of the mode selector node are connected from respectively to the first, second and third address inputs of the address memory node, the second, third, fourth and fifth outputs of the mode selector node are connected respectively to the first, second, third and fourth inputs of the second OR element, whose output is connected to the trigger input of the multiplier synchronizer, the third, fourth, and fifth outputs of the mode selector node are connected to the first, second, third, and fourth inputs respectively I will give the third element OR exit. which is connected to the start input of the second synchronizer of the computing unit, the quarter, five and sixth outputs of the mode selector node are connected respectively to the installation input, the start input and the stop input of the synchronizer accumulating adders, the second output of the second synchronizer of the subcomputers computation block and the start of the synchronizer accumulating adders, the fourth output of the second synchronizer of the computing unit is connected to the setup input synchronized ora accumulating accumulators, clock input of the node of choice of Renshma is combined with the installation inputs of the first and second synchronizers of computing blocks, the control input of the address memory node and the installation inputs of the multiplier synchronizer, the first, second, third and quarter outputs of the first synchronizer of the computing block are combined The first output of the control unit, the first and second outputs of the address storage unit are combined and are the second output of the control unit NIN, the first, second, third, fourth and fifth outputs with The multiplier synchronizer is interconnected and is the third output of the control unit jnep, second, third and quarter outputs of the second synchronizer of the computing unit and the fourth output of the control unit, the first, second, third and quarter outputs of the synchronizer accumulating adders and the second input of the selector unit, p € 1 clamp, is combined and is the fifth output of the control unit, with the mode selector node containing two short-circuits, an element NOT, two SOZh elements, an element And, two shift registers and a group of elements And, than zero setting inputs of the first and second shift registers and the R-input of the first RS-trigger and is combined with the first input yut- mode selecting part. the third input of which is the first input of the element AND, the input of the element NOT and the S input of the second RS flip-flop five 5 0 5 0 are interrupted and are the second input of the mode selector node, the output of the first RS flip-flop is connected to the second input of the AND element, the output of which is connected to the first input of the second element OR, the output of the element is NOT connected to the inputs, shift control of the first and second shift registers, the output of the second RS -trigger connected to the second inputs of the first and second elements OR, the output of the second element SH-connected to the clock input of the second shift register, the output of the lower order of which is connected to the S-input of the first RS-flip-flop, R-BXO- to the second RS-flip a and the first inputs of the AND elements of the group, the output of the higher bit of the second shift register is connected to the input of the sequential-recording of the information of the second shift register and the first inputs of the first element OR whose output is connected to the clock input of the first shift register, the inputs of the lower bits the first and second shift registers are connected and are the input of the logical unit of the mode selection node, the bits of the first shift register are connected to the second inputs of the corresponding AND elements of the group, the outputs of which The first are the outputs from the first to the sixth mode selection node, while the computing unit contains a group of P input registers, a node of accumulating modulo M adders (M 2 - 1) and a group of P output registers, and the information inputs of the unification input registers are not and are the information input of the computing unit, the output i-ro (i 1, P) of the input register is connected to the 1st information input of the node accumulating adders modulo M5 whose 1st output is connected to the information input i-ro of the output register output outputs reg The lines are combined and are the output of the computational unit, the clock inputs of the input registers, the node of accumulating modulo M adders and the output registers are combined and controlled by the control input of the computational unit. "Y " "/ f .p fPus. vA; . ft Qius.B "--Yes .J Fa 10 FIG. eleven 91 uP7 "oh toL-J 59 3f IpMit Ipu / D i- i lJIbjIJI-Ji,  I P / (I RF I I four 1 F f g .n Vut.fS Haz 26 Haz Haz Haz Fig 18 Compiled by A. Baranov Editor N. Bobkova Tehred I., Popovich Proofreader G. Reshetnik Order 619/56 Circulation 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4