SU1328925A1 - Digital recursive filter - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to increase the filtration accuracy. Digital recursive filter contains operative ff 7 th storage unit (OZB) 1, two multi-pass switches 2 and 3, two adders 4 and 5, N + M adders-calculators (CB) 6, N + M registers 7, N + + M the switches 8, the memory block 9 of the switching codes and the control unit (CU) 10. The filter is implemented in canonical form, in which the current intermediate data and output samples are calculated by f-logs. To form coefficients, we use the property of codes in redundant number systems, which allow the sequential processing of data words, beginning with the highest digit. The goal is achieved by introducing CB 6, registers 7 and switches 8, with which, together with OZB 1 and switch 3, the intermediate results are multiplied by coefficients. The filter according to PP.2, 3 and 4 differs in the computation of OZB 1, BU 10 and CB 6, and their sludge is given. 3 hp ff, 7 ill. (C cl at.f

Description

11328925

The invention relates to radio engineering and can be used in digital signal processing devices with serial information processing,.

The purpose of the invention is to improve the accuracy of filtration.

Figure 1 shows an electrical structural diagram of a digital recursive filter; Fig. 2 is a diagram of the operative storage unit; Fig. 3 is a diagram of the control unit; FIG. 4 is a diagram of an adder-subtractor; FIG. 5 is a multiplier circuit; figure 6 is a diagram of a multi-input switch; Fig. 7 shows timing diagrams explaining the operation of the 1-FRF recursive filter.

Digital recursive filter (Fig. 1) contains operative memory - block 1, first and second multiple-input switches 2 and 3, first and second adders 4 and 5, N + M subtractors 6-1 - 6- (N + M ), N + M registers 7-1 - 7- (N + M), N + M switches 8-1 - 8- (N + M), block 9 of memory of switching codes, block 10 of control, first and second outputs 11 and 12 operational storage unit 1, information input 13 of a digital recursive filter, information output 14 of a digital recursive filter, input 15 of a control of the coefficients of a digital recursive filter, clock in 16 digital recursive filter, marker input 17 of the common recursive filter, marker output 18 of the common recursive filter, is the first output of block 10

20

25

thirty

35

control, second and third syncroni-40 side of the lower-order result

signaling outputs 19 and 20 of the control unit 10.

Operational storage unit 1. (Figure 2) contains the first, second and third groups of registers 21-1 - 21- (N-1), 22-1 - 22-N, 23-1 - 23-M.

The control unit 10 (Fig. 3) contains a counter 24 and a decalphator 25.

The adder-subtractor (figure 4) contains a sequential adder 26 and the multiplier 27 by +1.

The multiplier 27 by +1 (fig.Z) contains the first and second switches 28 and 29.

The MiGow Switch (FIG. 6) contains the switches 30-1 to 30-L (L N for the first multiple input switch 2, for the second multiple input switch),

North-West But if the transfer to the lower bits is almost infinite, then to the high bits, the transfer spreads to a limited number of result bits (usually two to four bits). Therefore, the result of successive summation is neither in redundant OTJ number systems

gQ is from the input operands / s for several calculation cycles P, the number of which is determined by the number of bits to which the transfer signal can propagate towards the higher bits. Therefore, if the sequential summation of a number in the redundant number system begins with the higher bits and is performed with the number obtained as a result of

55

Digital recursive filter works as follows.

The digital recursive filter is implemented according to the canonical form, in which the current intermediate data (s) is calculated by the formula

j (n) X (n) - T b. Lo (n-i)

where X (n) is the value of the current input reference;

W (p-1) are intermediate values of the calculation process. Output counts are calculated using the formula

YES

Y (n) Z a.w (n-i),

11 o

Y (n)

M, N

the value of the current output count,

the number of samples (coefficients) of the non-recursive and recursive parts of the digital recursive filter. ,

0

five

To form coefficients a. and b, the following property of codes in redundant number systems is used, which allow the sequential processing of data words, starting with the highest bit, for example, the digit code.

In redundant numeration systems, which perform the operation of the incremental addition of two operands, starting with the higher bits, the transfer signal propagates, as a rule, both towards the higher bits and

North-West But if in the direction of the lower bits the transfer spreads almost infinitely, then in the direction of the higher bits the transfer spreads to a limited number of bits of the result (usually two to four bits). Therefore, the result of sequential summation in redundant OTJ number systems:

Q is from the input operands / s for several calculation cycles P, the number of which is determined by the number of bits to which the transfer signal can propagate towards the higher bits. Therefore, if the sequential summation of the number in the redundant number system begins with the higher bits and is performed with the number obtained as a result of

five

summing up is equivalent to multiplying the number by the coefficient

K1 1.1 1 0 .. .0 1 .. 1 ... R.. Р Р

If the result of summation is delayed before summation with the initial number by C cycles, then this will be equivalent to multiplying the number by the coefficient

, p .. 0 1 0 ... 0 1 0 .. 1 ... P + C Pt-C P + C

If the initial number is preliminarily delayed by H clocks, then this is equivalent to multiplying the coefficient K2 by R, where R is the base of the redundant number system, i.e. multiplying the original number by a factor

.o 1, o .. 1 0 .. .0. one...

Н Р + С Р + С

The operation of the digital recursive filter in each cycle of forming the output sample is initialized by a pulse from the marker input 17 (Fig. 76), which comes from the marker output 18 of the previous digital recursive filter operating in the cascade, or from the control output of the device - the source of the digitized signal ( for example, an analog-to-digital converter operating in codes of a redundant number system). The clock signal is fed to the clock input 16 (Fig.7a)

The pulse at the marker input 17 should immediately precede the arrival at the information input 13 of the sequence of words of the input data X (n) (Fig. 7c). It enters the installation input of the counter 24 of the control unit 10. This leads to zeroing of the counter 24 and the formation of a pulse at the second output 19 (fig. 7d) of the control unit 10. This pulse is fed to the installation inputs of the second group of registers 22-1 - 22-N, the sum of matrices-subtractors 6-1 - 6-Ы (fig.7i m), registers 7-1 - 7-N and the first adder 4, which leads to reset them. Following this, data words X (n) begin to arrive at the information input 13 in a sequential form.

28925

presented in the codes of the redundant number system and coming from the information output 14 of the previous digital recursive filter or from the information output of the device - the source of the digital signal. From the outputs of the first group of registers 21-1 - 21- (N-1) operational storage

0 block 1 to the information inputs of the second group of registers 22-1 - 22- (M-1) begin to arrive consecutive, the words of intermediate results w (n-i). By means of the second group of registers 5-1-1 22-N, the first multiple-input switch 2, the combiner-readers 6-1-6-N, the registers 7-1 -7-N and the switches 8-1 -8- (N + M) multiply the intermediate

2Q results q) (p-1) on coefficients

one

Formation of the mark of works

It is carried out by subtractors 6-1 to 6- (N + M), where the sign of the coefficient comes from the sign output of the block 9 of the memory of the switch codes5

five

tion, and the sign of the intermediate value of the word u) (n-1) - on the information input. The sign of the products is formed by 0 at the output of multiplier 27, which multiplies by f1. For a digit code, multiplying by a negative coefficient will cause the positive and negative busses of the operands of the first and second switches 28 and 29 of the multiplier to change places. The first adder 4 forms the current value of w (n). At the same time, the input data X (p) is multiplied by the factor b to normalize the gain of the digital recursive filter.

As mentioned, the data word bits at the output of totalizers 6-1 to 6- (N + M) lag behind the data bits of the same name at their inputs by several cycles P. This leads to the fact that the bits of the formed word the values of w (p) at the output of the first adder 4 (fig. 7k) are delayed with respect to the same-named bits of the words w (ni) at the outputs of the first group of registers 21-1 to 21- (p-1) at P + K cycles (fig. 7g), where 5 K is the number of cycles j for which the data in the first adder 4 is delayed. If the latter is made in the form of a tree of two-input adders in excess oh number system then

0

the delay K will be equal to K Pjlog N clocks, where the expression denotes the smallest integer greater than or equal to logjN.

Since this delay is constant for the recursive part of the digital recursive filter, the timing of the arrival of single-word bits of the intermediate results of the co (ni) calculations to the inputs of the totalizers 6- (N + 1) - 6- (N + M) carried out It is by delaying the words of intermediate results of 1 calculations w (ni) when, at the inputs of registers of the third group of registers 23-1 - 23- (M-1) by P + K cycles when they are off-shift. along the chain of the second group of registers 22-1 - 22 - (N-1) (fig.7z), and this leads to the fact that the same-named bits of all words are interleaved computing W (p-1) (, N) simultaneously arrive at the inputs of the third group of registers 23-1 - 23-M (fig.7l).

Through P + K-1 cycles from the beginning of processing the next input sample, i.e. per pulse before the first value of the word bit of the intermediate computation u (n) of the third output 20 (fig.7e) of the control unit 10 arrives at the input of the register 23-M, an impulse is generated (fig.7a) arriving at the installation inputs of the third group registers 23-1 - 23rd and registers 7- (N + +1) - 7- (N + M), which leads to their zeroing. The same pulse arrives at the installation inputs of adders-subtractors 6- (N + 1) - 6- (N + M) and the second adder 5, which leads to their zeroing. Through the third group of registers 23-1 -23-M, the second multi-input switch 3, accumulator adders 6- (N + 1) - 6- (N + M), registers 7- (N + 1) - 7- ( N + M) and the switchboard of the current output value Y (n) is accompanied by the generation of an output marker impulse at the output 18 of the control unit 10, which enters the next stage of the digital recursive filter or the output device (Fig. 7d).

Total processing time of a single data word in a digital recursive

The W filter is 2P + K + K + B cycles, where B is the number of bits in the data words. The same-name words of intermediate results of the calculations of ω (p-1) from the outputs of registers of the second

15 groups of registers 22-1 (N-2) are fed to the corresponding inputs of the first group of registers 21-2 - 21- (N-1) with numbers one more. This allows for re-indexing.

20 intermediate results of calculations in accordance with the digital filtering algorithm.

Block 9 of the memory of the switching codes can be executed as a constant

25 storage device (ROM) or as random access memory (RAM). In the case of running it as RAM on the input 15 of the coefficient control, a record of the control

There are 30 codes that determine the amount of data word shift in the first and second multi-pass switches 2 and 3 and switches 8-1 - 8- (N + M) and the signs of the coefficients. When executing a block

The J5 9 memory in the form of a ROM at the input 15 of the coefficient control is used to control the selection of a specific set of filtering coefficients, which allows the various transfer functions of the digital recursive filter to be realized.

Claims (4)

Formula 1. Digital recursive filter. The 8- (NH) -8- (N + M) torques are produced by 45 ™ control, the first adder and the operational storage unit are connected in series, the second input of which is the information input of a digital recursive filter, the second adder whose output is an output. Digital recursive filter, first and second multi-input switches, memory block of switching codes, first in-multiplication of intermediate results u) (ni) by coefficients a. . The second adder 5 generates the current output value Y (n) (fig.7n). The first significant bit of the current output value Y (n) is generated at the output of the second adder 5 through 2P + + K + K clock cycles (K is the number of clock cycles. 50 first connected sum and a random access memory block, the input of which is the information input of a digital recursive filter, the second adder, the output of which is an output. The digital recursive filter, the first and second multiple-input switches, the switching code memories, the first inna which delays the data in 55 whose output is connected by the second adder 5, defined by the expression K P3 log, M) from the beginning of the processing of the next input data word X (n). The appearance of the first is significant with the control inputs of the first and second multi-input switches, and the input is the input controlling the coefficients of the digital recursive bit of the current output value Y (n) accompanied by the generation of a pulse of the output marker at the output 18 of the control unit 10 that enters the next stage of the digital recursive filter in the output device (Fig.7g). Total processing time of a single data word in a digital recursive The filter is 2P + K + K + B cycles, where B is the number of bits in the data words. The same-name words of intermediate results of the calculations of ω (p-1) from the outputs of registers of the second groups of registers 22-1 (N-2) are fed to the corresponding inputs of the first group of registers 21-2 - 21- (N-1) with numbers one more. This allows for re-indexing. intermediate results of calculations in accordance with the digital filtering algorithm. Block 9 of the memory of the switching codes can be executed as a constant storage device (ROM) or as random access memory (RAM). In the case of running it as RAM on the coefficient control input 15, control codes are written that determine the amount of data word shifting in the first and second multi-pass switches 2 and 3 and switches 8-1 to 8 (N + M) and the signs of the coefficients. When executing a block 9, a memory in the form of a ROM at the input 15 of the coefficient control is used to control the sampling of a specific set of filtering coefficients, which makes it possible to implement various transfer functions of a digital recursive filter. Formula 1. Digital recursive filter. 45 ™ to control, then 50 the first adder and a random access memory unit, the second input of which is the information input of a digital recursive filter, the second adder, the output of which is an output. The digital recursive filter, the first and second multi-input switches, the memory block of the switching codes, the first output which is connected to the control inputs of the first and second multi-pass switches, and the input is the input control of the coefficients of the digital recursive filter, characterized in that, in order to increase filtering, entered N + M subtractors, N + M switches and N + M registers, with the clock and marker inputs of the control unit being the clock and marker inputs of the digital filter, the marker output being the marker output of the digital recursive filter , the first synchronization output of the control unit is connected to the first control input of the operational storage unit, with the control input of the first adder and with the control inputs of N registers and N adders-subtractors, the second synchronization output of the control unit It is connected to the second control input of the operational storage unit, to the control input of the second adder and to the installation inputs of the M registers and M totalizers of the subtractors, the first output of the operational storage unit is connected to the information input of the first multi-input switch, N outputs of which are connected with the first information inputs of N adders-subtractors, the control inputs of which are connected to the sign output of the memory block of the switching codes, and the outputs are connected to the inputs of the first totalizer Pa and through the corresponding serially connected register and switch are connected to their second information inputs, the second output of the operational storage unit is connected to the information input of the second multi-input switch, the M outputs of which are connected respectively to the first information inputs M of adders, the control inputs of which are connected to the sign the output of the memory block of switching codes, and the outputs are connected to the inputs of the second adder and through the corresponding series These registers and switches are connected to their second information inputs, and the second information output; the switching code memory block is connected to the control inputs of the N + M switches. 2, The filter according to claim 1, wherein the random access memory unit contains the first, second and third groups of registers from the NN and M (M) registers, respectively, while the installation inputs of the registers of the second group are combined and are the first controllers. The operational input of the operational storage unit, the installation inputs of the registers of the third group are combined and are the second control input of the operational storage unit, the information inputs of the first register of the first group and the M-th the third group of registers are combined and are the first input of the operational storage unit, the information input of the N-ro register of the second group is the second input of the operational storage unit, the outputs of the registers of the first group are connected to the information inputs of the same registers of the second group, the second outputs of which, except N-ro connected to the information inputs of the same name registers of the third group; information inputs of the registers of the first group, except the first, are connected to the second WELHOD's of the previous registers of the second group ppy first register the outputs of the second group are output first RAM unit, and the outputs of the third group of registers are the second output of the operational memory block. 3. The filter according to claim 1, wherein the control unit comprises a serially connected counter and a decoder, wherein the counter clock input is the clock input of the control unit, the counter installation input is the marker input of the control unit, and the first, second and third decoder outputs are the first and second synchronization outputs of the control unit and the marker output of the control unit, respectively. 4. The filter according to claim 1, characterized by the fact that the adder-subtractor contains a series-connected multiplier of ± 1 and a serial adder, the output of which is the output of the adder-subtractor, the setup input is the setup input of the subtractor, the information input of the multiplier by ± 1 is the first information input of the adder, subtractor the input is the control input of the adder-subtractor, and the second input of the serial adder is the second information input of the adder-subtractor. h h h Have Wu Vryyush, yi UstanVochiiya L. .. By / Southern / to {1 Input Bus ABOUT / Y / ytrchidgulma tread wheel 28 Fist oh shd okg Is positive bymdna tire o Otriyat / gna Bypass Tire-o Editor V.Danko Compiled by E. Borisov Tehred M. Morgenthal Order 3496/56 Circulation 901 Subscription VNIIGSh of the USSR State Committee for Inventions and Discoveries 4/5, Moscow, Zh-35, Raushsk nab. 113035 Production and printing company, Uzhgorod, Projecto st., 4 Proofreader V. Girn to