SU1027732A1 - Digital function generator - Google Patents

Abstract

DIGITAL FUNCTIONAL TRANSMITTER, containing two input registers, three memory blocks, seven intermediate registers, two adders, a synchronization unit and an output register, the output & d of the synchronization unit connected to the control inputs of all registers, the output of the first input register connected to the information input of the first intermediate register and through the first memory block with the information input of the second intermediate register, the output of the second memory block is connected to the information input of the third intermediate register An isstra, the output of which is connected to the first input of the first adder, the output of which is connected, to the information input of the output register, characterized in that, in order to improve speed, a switch, a trigger and two memory blocks are entered into it, the output of the second input register being through the third the memory unit is connected to the information input of the fourth intermediate register, the output of which is connected to the first input of the second adder, the second input and output of which are connected respectively to the output of the second intermediate register and an information input of the 5th intermediate register, the output of which through the fourth memory block is connected to the information input of the sixth intermediate register, the forward and inverse outputs of which are connected respectively to the first and second information inputs of the switch, the output of which is connected to the second input of the first adder , the output of the first intermediate register is connected to the information input of the seventh intermediate register, the output of which is connected to the inputs of the second and fifth memory blocks, 1C output n n The second memory block is connected to the trigger information input, the synchronous input and output of which are connected respectively to the output of the block, the synchronization OO tC and the control input of the switch. .

Description

The invention relates to computer technology ti and can be used as a specialized high-performance computer system processor for computing functions of one variable. A device for calculating elementary functions is known, which contains seven adders, three number registers, an argument register, a remainder register, two rounding blocks, thirteen element-AND, two multiplication blocks, seven OR elements, eight comparison blocks, and four counters. as a sequence of iterations, with several iterations of TI 1 being performed at each iteration. The disadvantage of the device is its low speed. The closest to the proposed technical solution is a conveyor device for calculating elementary functions, containing five registers, three ROM blocks, two multipliers, two adders, and a control block. This device operates on a pipelined basis. Its speed in processing arrays of numbers is determined by the multiplication time of two numbers per multiplication block}. However, in the tasks of digital processing of seismic data, radio navigation, results of physical experiments and so on, where multiple computations of functions of one variable, in particular elementary functions, are required, there is a need to further improve processing performance. This is due to both the increase in the volume of data being processed and the appearance of new processing algorithms, the implementation of which is impossible on slow digital devices. Thus, the speed of a known device is no longer satisfactory. The purpose of the invention is to increase the speed of interaction. The goal is achieved by the fact that a digital functional converter containing two input registers, three unit blocks, seven intermediate registers, two adders, a synchronization unit and an output register, the output of the synchronization unit connected to the control inputs of all 1,322 registers the input register is connected to the information input of the first intermediate register and through the first memory block to the information input of the second intermediate register, the output of the second memory block is connected to the information input The third intermediate register, the output of which is connected to the first input of the first adder, whose output is connected to the information input of the output register, is additionally introduced a switch, a trigger and two memory blocks, the output of the second input register being connected to the information input through the third memory block the fourth intermediate register, the output of which is connected to the first input of the second adder, the second input and the output of which are connected respectively to the output of the second intermediate register (information the input of the fifth intermediate register, the output of which through the fourth memory block is connected to the information input of the sixth intermediate register, the forward and inverse outputs of which are connected respectively to the first and second information inputs of the switch; the output of which is connected to the second input of the first adder, the output of the first intermediate register is connected to the information input of the seventh intermediate register, the output of which is connected to the inputs of the second and fifth memory blocks, the output of the fifth memory block is connected to nformatsionnym trigger input, and the clock output of which is connected respectively to the output synchronizing unit and the control input of the switch. The drawing shows a block diagram of the convertible, the converter contains registers 1-10, memory blocks 11-15, adders 16 and 17, trigger 18, switch 19, synchronization unit 20. The converter calculates an arbitrary function F (x) O using the Taylor formula using two terms: FCx)% F (Xj -4xF (Xo), where XQ 0, X; ,,,, x, P, ,, 0 is the number formed by the higher bits of the argument; Dx 0,0,., 0hc., X J, is the number formed by the lower digits of the argument.

The error of this formula can be made to go beyond the limits of the discharge grid by an appropriate choice of the parameter K.

The increment Dx F {x is calculated by the formula

AxF4Xo) (F () (o))

; () /

where is the function

R

if X P,

Sicgn | 0,

if x oh

if X o. To perform transformations. o- F (XO). (XQ), lx -, 2 L, where Z + locjj / F xoH (p / F (x)) / memory blocks ll-1i are used. The case of FCXp and lx O is taken into account by the fact that the corresponding values of locg- / RFC (5) / and in the tables are taken so large in absolute value negative numbers that the result is beyond the limits of the discharge grid.

The device works as follows.

In the first clock cycle, the number Xd is written to register 1, and the number lho to register 2 According to the numbers from memory blocks 11 and 12, the 1oQr2 / F (XQ) /

and

In the second cycle, these values are written to the registers, respectively, and 5 and the contents of register 1 are rewritten to register 3. At the adder 16, the contents of registers 4 and 5 are added together.

In the third cycle, the number from the adder 16 is written to register 7, and the register 6 is copied to register 6. The contents of this register from memory blocks 13 and 14 read F values accordingly (xp; and /F (xo )/.no register contents 7, the value 2 is read from the memory block 15, i.e., at its output a number equal to the product 4 x / P (CW) / is obtained.

In the fourth cycle, the values read from blocks 13–15 are written to register 8, trigger 18, and register 9, respectively. Adder 17 adds the contents of registers 8 and 9, i.e., the value of F (x) is formed. Moreover, the contents of register 9 comes in the second

the input of the adder 17 in the forward or reverse code, depending on the sign of F {XJJ; stored in the trigger 18, which allows the operation of the subtraction.

In the fifth clock cycle, the value obtained is written to register 10, and from it goes to the output of the device.

Separating a device into registers allows its steps to operate independently. Therefore, as soon as the result of processing one element of the array from one step is transmitted to the next, the results of processing the second element 5 of the array already arrive at this step. Managing the operation of this device is reduced to the generation of clock pulses, moving intermediate results from registers of one stage to registers of the next stage. Clock pulses are generated by synchronization block 20, which contains a clock pulse generator and start and stop circuits, which allow or prohibit the passage of clock pulses to device registers.

The device operates according to the conveyor principle; therefore, its speed is determined by the tact duration equal to the delay in the slowest stage, i.e.

°

where is the summation time on the adder;

t, is the information delay by the switch.

The speed of the prototype is equal to t. As is known, the multiplication operation is much slower than the addition operation, in particular when using the fastest multilayer multiplier and the adder with the accelerated transfer, tt. Thus, the proposed device significantly exceeds the performance of the prototype.

The total amount of device memory blocks is different for different functions, in particular, when the number of processed numbers is 16 for the sin function, Gl 15 kbps, for the function ° 1, Q is 22 kbps.

On the given structure, it is possible to implement any functions of a single variable, if these functions belong to a class that is twice uninterrupted but differentiable. In this case, in the ROM it is necessary to have coefficients for all functions, or to replace the ROM blocks if separate functions are realized.

Claims (1)

A DIGITAL FUNCTIONAL CONVERTER containing two input registers, three memory blocks, seven intermediate registers, two adders, a synchronization block and an output register, the output of the synchronization block being connected to the control inputs of all registers, the output of the first input register connected to the information input of the first intermediate register and through the first memory block with the information input of the second intermediate register, the output of the second memory block is connected to the information input of the third intermediate register, exit for which it is connected to the first input of the first adder, the output of which is connected to the information input of the output register, characterized in that, in order to improve performance, a switch, a trigger and two memory blocks are introduced into it, and the output of the second input register through the third memory block is connected with the information input of the fourth intermediate register, the output of which is connected to the first input of the second adder, the second input and output of which are connected respectively to the output of the second intermediate register and information the input of the fifth intermediate register, the output of which through the fourth memory block is connected to the information input of the sixth intermediate register, the direct and inverse outputs of which are connected respectively to the first and second information inputs of the switch, the output of which is connected to the second input of the first adder, the output of the first intermediate register is connected to the information the input of the seventh intermediate register · whose output is connected to the inputs of the second and fifth memory blocks, the output of the fifth memory block is connected to inf rmatsionnym trigger input, and the clock output of which is connected respectively to the output unit, the synchronization and the control input of the switch. SU, .., 1027732 1 '