SU1125746A1 - Digital filter - Google Patents

Abstract

A DIGITAL FILTER containing a shift register, the bit outputs of which are connected to the inputs of a multi-input adder, as well as the first two-input adder, the output of which is connected, to the input of a delay register, the output of which is connected to the first input of the first two-input adder, characterized in that extending the functionality by providing consistent filtering of pseudo-random sequences, the second and third two-input adders and the multiplier are inserted into it, the first input of the second the second two-input adder is connected to the code of the first bit of the shift register, the second input is connected to the output of the last bit of the shift register, and the output to the first input of the third two-input adder, the second input of which is connected via a multiplier to two with the output of a multi-input adder, and the output to the second the input of the first two-input adder, the third input of which is the input of the signal of the logical unit, while the inputs of the multi-input adder are connected to the outputs of the register bits with a shift according to K + C, where K is weight marketing coefficient. iNd SL

Description

The invention relates to a technique for optimal reception of signals and can be used in digital signal processing devices, as well as in radio links, as a matched filter for the separation of code words in the form of pseudo-random sequences (PRS),

A digital filter is known that contains a shift register and a multi-input adder consisting of matching blocks connected to the outputs of the shift register bits, the second inputs of the matching blocks are connected to the outputs of the storage elements of the weight code, and the outputs to the inputs of the multi-input adder 1 J.

The disadvantage of this digital filter is its low speed, which is explained by the need to perform per cycle (shift cycle) of the summation of a large number (N) of codes, which reduces the frequency range of the processed signals. Also digital. The filter has low reliability due to the large number of links caused by the need to have taps from each bit of the shift register. The noted drawbacks of the device are the greater, the greater the length of the processed memory bandwidth.

The closest to the invention to the technical nature is a digital filter containing serially connected shift register and a multi-pass adder, the additional input of which is connected to the output of the first sign selector, the second sign selector whose input is connected to the outputs of the bits of the shift register, and the code to the first the input of the two-input adder, the second input of which is connected to the output of the delay register, the input of which is connected to the output of the two-input adder C2.

However, a known digital filter cannot provide consistent filtering of the memory bandwidth, which limits its functionality.

The purpose of the invention is to expand the functionality of the device by providing consistent filtering of pseudo-random sequences.

The goal is achieved in that a digital filter containing a shift register, the bit outputs of which are connected to the inputs of a multi-input adder, as well as the first Two-input adder, the output of which is connected to the input of the delay register, the output of which is connected to the first input of the first two-input adder, is entered and the third two-input adders and a multiplier by two, while the first input of the second two-input adder is connected to the output of the first digit of the shift register, the second input - to the output of the last bit reg shifter, fi output to the first input of the third two-input adder, the second input of which is connected via a multiplier to two with the output of the multi-input adder, and output to the second input of the first two-input adder whose third input is the input of the signal of the logical unit, while the inputs of the multi-input adder connected to the outputs of the register bits in accordance with,.,

howl ratio.

The drawing shows a structural electrical circuit of a digital filter.

The digital filter contains a register 1 / shift, a second two-input adder 2, a multi-input adder 3, a multiplier 4 for two, a third 5 and a first 6 two-input adders, a register of 7 delays and an input 8 of a logical unit signal.

The device works as follows.

When negotiating the filtering of binary signals, a weighted sum is calculated

(one)

(I

where x is the input samples,

+1 values

and -1i K.gl) .- weights,

+1 values

and -1;

 the value of the expected memory bandwidth. Completing filtering directly by expression (1) when processing the memory bandwidth requires an excessive number of operations. For the output signal of the matched digital filter in and. (1-1) th bars: ..Kj MN-2 | N n- (N-1) (2) (. X -. N-CN-Zl NS n-1 0 n-2 1 n- (Nl) N-2 ft-N Nf After summing up the impressions (2) and ( 30 and bringing similar terms, we get (, (n4N-1) Nl N-2n-N N-1 Lérenés U. to the left, using the summation sign and taking out the coefficient 2 from the sum sign, we get the difference equation of the digital filter: ... nn -% -NVl 2 Lie- (In expression (4), in contrast to expression (1), to get the next} start) 1 and the output signal Hf, not only the present and previous values of the input signal h are used. but the value of the output signal Vn obtained in the previous cycle is The coefficients are implications (4 recipients can take one of three values +1, -1.0. A known property of the bandwidth is that they have a total number of pairs of neighboring positions (Ki, K take values (+ 1, -1), ( -1, +1), (+ 1, + 1), (-1, -Ч) is almost the same, so about half of the coefficients V ii-i - 2 are equal to zero in expression (4), which is significant (almost twice) reduces the number of operations required for filtering. Before starting operation, the shift register 1 and the delay register 7 are reset. The filtering signal x is fed to the input of the shift register 1. In each operation cycle, the signals from the outputs of the first and last () th bits of the shift register 1 are summed by the second two-input adder 2, and the signals from the intermediate outputs of the shift register 1 - by the multi-input adder 3. The number formed at the output of the multi-input adder 3 is multiplied by two in the multiplier 4 and is added in the third two-way adder 5 with the result obtained at the second two-input adder 2. The signal is in the form of a direct parallel code from the output. the third two-input adder 5 enters the second input of the first two-input adder 6, the first input of which receives the output delayed by one clock cycle generated in the previous filter cycle (Vf,), the output signal delayed by clock from the inverse outputs of the delay register 7 and is therefore represented in the reverse code. At the transfer input of the mpa discharge of the two-input adder 6, the unit potential applied from the input 8 of the signal of the logical unit acts permanently, forming an additional number code along with the incoming feedback code. As a result, the first two-input adder 6 performs the operation. subtracting the number v. i, so that at the output of the first two-input adder 6, the output filtered signal Vf ,, is formed, which is written into the delay register 7 for use in the next operation cycle. Thus, the proposed digital filter provides consistent filtering of pseudo-random sequences.

Claims (1)

(57.) A DIGITAL FILTER containing a shift register, the discharge outputs of which are connected to the inputs of a multi-input adder, as well as the first two-input adder, the output of which is · connected, to the input of the delay register, the output of which is connected to the first input of the first two-input adder, characterized in that , in order to expand functionality by providing consistent filtering of pseudo-random sequences, the second and third two-input adders and a multiplier by two are introduced into it, while the first input of the second the two-input adder is connected to the output of the first bit of the shift register, the second input is to the output of the last bit of the shift register, and the output is to the first input of the third two-input adder, the second input of which is connected through the multiplier by two to the output of the multi-input adder, and the output to the second input of the first a two-input adder, the third input of which is an input of a signal of a logical unit, while the inputs of a multi-input adder are connected to the outputs of the register bits with a shift in accordance with where K is the weight coefficient . , „SU.l 125746> (About t5