SU1159013A1 - Device for adding n numbers together - Google Patents

Abstract

A DEVICE FOR ADDITION n NUMBERS containing k multi-single-bit adders (k is the number of groups of digits of summed numbers) and delay elements and n-1 inputs of each multi-input adder are connected to the inputs of the corresponding bit of the n-1 group of summable numbers of the device, differing from that that, in order to simplify the device and increase its speed, the device contains k multi-digit adders, the first inputs of bits, each multi-digit adder are connected to the outputs of the corresponding bits In the case of a multi-input single-digit adder, the output of the first discharge of each multi-discharge adder is the output of the corresponding bit of the device, the output of each discharge, starting from the second, each multi-discharge adder, except for the k-ro, is connected to the second input of the previous discharge Yes, the subsequent multi-bit is a summator, and the transfer output of the high bit of each multi-bit adder, except for the k-ro, is connected to the second input of the high bit of the next multi-bit adder, BIJhons of bits, starting from V and the high-order carry-out output (L k-ro multi-digit adder is connected to the inputs of the corresponding delay elements, the outputs of which are connected to the second inputs of the corresponding bits of the first multi-bit adder, the inputs of the n-th summable group of numbers are connected to the transport inputs of the lower order bits of the SP of the corresponding multi-bit sum maters.

Description

. one . I The invention relates to computing and is intended for use in a digital computer. The purpose of the invention is to simplify the device and increase its speed. The drawing shows a block diagram of the proposed device for adding n numbers. The device contains k myogvodovyh one-digit adders 1 (k is the number of groups of bits of summable numbers), the number of inputs of which is equal to ps, k of multi-category summator 2, the number of bits of which is m + 1, and m + 1 delay elements 3. n - 1 the inputs of each multi-input adder 1 are connected to the inputs of the corresponding bits of the n-1 group of summable device numbers. The first inputs of the bits of each multi-bit adder 2 are connected to the outputs of the corresponding bits of the corresponding multi-input single-bit adder 1. The output of the first bit of each multi-bit adder 2 is the output of the corresponding -discharge device. The output of the KSL discharge, starting with the second of each multi-digit adder 2, except for the k-ro, is connected to the second input of the previous discharge of the next lot. bit adder 2. The high-order carry output of each multi-bit 82-th regular adder 2, except for k-ro, is connected to the second high-order input of the next multi-bit adder 2. The bits output, starting from the second, and the high-order carry output k The -ro multi-bit adder 2 is connected to the inputs of the corresponding ,, delay 3 elements, whose outputs are connected to the second inputs of the corresponding bits of the first multi-bit adder 2. The bits of the n-th summed group of bits are connected to the transfer ports lower x bit-dov. respective multibit adders 2. The device operates as follows. During the first cycle of operation, the inputs of the same n bits of all n numbers are supplied to the inputs. At the outputs of the first bits of multi-bit adders 2, signals of the respective bits of the bits and odds are formed. At the inputs of each bit, starting from the second, and the transfer code of the highest bit of each multi-bit adder 2, transfer signals to the high bits are formed. During the second cycle of operation, the next k bits of all n numbers and hyphens formed in the preceding clock cycle are similarly summed up. Thus, with the termination of all the digits of all n numbers, the device generates their sum.

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Claims (1)

DEVICE FOR ADDING η NUMBERS containing k multi-input single-digit adders (k is the number of groups of digits of summed numbers) and delay elements, moreover, p-1 inputs of each multi-input adder are connected to the inputs of the corresponding bit of the group p-1 summed numbers of the device, characterized in that, in order to simplify the device and increase its speed, the device contains k multi-bit ί adders, the first inputs of the bits of each multi-bit adder are connected to the outputs of the corresponding bits accordingly of the multi-input single-bit adder, the output of the first bit of each multi-bit adder is the output of the corresponding bit of the device, the output of each bit, starting from the second, of each multi-bit adder, except for the kth, is connected to the second input of the previous bit of the subsequent multi-bit adder, and the transfer output is older the discharge of each multi-bit adder, except for the k-th, is connected to the second input of the senior bit of the subsequent multi-bit adder, the outputs of the bits, starting from the second, and the output transfer MSB k-th multi-bit adder are connected to inputs of the respective delay elements, whose outputs are connected to second inputs of the respective stages of the first multi-bit adder, the inputs discharges group η-th summiruemogo- connected to the inputs of transfer LSBs corresponding multi-bit adders. ... SU 1159013