SU1381541A1 - Device for digital filtration - Google Patents

Abstract

The invention relates to computing and can be used in digital processing systems for seismic, hydroacoustic and other signals. The purpose of the invention is to simplify the device. The device contains an operation unit, a memory unit, an addressing unit, a clock pulse generator; the operational unit contains the source data register, multiplexer, output register, result register, accumulation multiplier, adder, fixed memory node, data register, NOT element, addressing block contains impulse response length counter, decoder, memory node, multiplexer, OR element , key, registers, NOT elements, filter counter, shifter, octave counters, counters, priority encoder, adder. The device performs active filtering of input signals from M sources. 4 il. S (l

Description

00 SP

The invention relates to computing and can be used in digital processing systems for seismic, hydroacoustic and other signals.

The purpose of the invention is to simplify the device by simplifying the block for the formation of the address-record.

Figure 1 is a block diagram of a device for digital filtering; figure 2 - matrix elementary filters (EF); on fig.Z - impulse response of the filter; in fig. - the format of the block 2 memory address.

The digital filtering device contains an operation unit 1, a memory unit 2, an addressing unit 3, a clock pulse generator 4. Operational unit 1 includes a source data register 5, a multiplexer 6, an output register 7, an output 8 of results, an accumulator multiplier 9, an adder 10, constant memory node 11 (coefficients), input 12, data register 13, input 1i, control input 15, NOT element 16, control input 17, control input 18, address outputs 19 and 20 of addressing unit 3. The addressing unit 3 contains a counter 21 of the impulse response length} 1ki, input 22, a decoder 23, a fixed memory node 2c with an output 25 of block 3, control outputs 26 and 27, a multiplexer 28, element I.PI 29, a key 30, a control output 31, register 32, element NO 33, control output 34, register 35, filter counter 36, register 37, address 38 output, element NOT 39, controller 40, register 41, counters 42 and 43 octaves, counters 44 c 45, register 46, priority encoder 47 and adder 48.

The device performs octave filtering of input signals coming from M sources. This is ensured by the sequential implementation of a matrix of elementary filters (IMF) of KxM size, which is shown in Fig.2. When cascading the ESP in each octave, the data are halved, i.e. Each of the ESP forms an output sample only upon receipt of two input samples. Therefore, the ESP of each subsequent octave is processed twice as rarely as the filters of the previous octave. This allows the use of a single operating unit for the repositioning of the entire MEF.

The implementation of any EF is reduced to performing an acyclic convolution operation according to the formula

N-

(one)

-

yu 15

20 25 30 40

d,

five

where h - the coefficients of the impulse response;

 countdown of the input signal;

Y is the output. To illustrate the operation of the device, FIG. 3 shows the impulse response, the total number of N coefficients of which is 17, all coefficients with even numbers, except the central one (bg), are zero, and the number of nonzero coefficients is (N-1) / 2 - f 1 i.e. 9. Due to the symmetry of the impulse response about the ordinate, the number of different zero coefficients is 5 (4 side and 1 central). Symmetry of impulse response. allows to reduce the number of multiplications, if the input samples, which should be multiplied by symmetric coefficients, are pre-summed and then multiplied by the corresponding coefficient. From formula (1), it follows that before calculating the final result of the ESP, the sequence of input samples shifts relative to the sequence of coefficients of the impulse response by two positions. In the proposed device, this shift is carried out by forming at each step of the calculation a specific sequence of read addresses. This sequence depends on the number of occurrences in this octave (in this ESP) and does not depend on the number of the processed octave. The most recent count is added to the oldest count, i.e. by counting, which will not be used on the next calculation stage, then the counting that precedes the last time, and the counting, which comes after the oldest, and so on, are added up. All these operations are performed only on the odd count except for the count, which must be multiplied by the central coefficient. Since in this case (Fig. 3) the impulse response contains 8 nonzero odd coefficients, there are 8 variants of such sequences.

Let At be the time interval between two neighboring readings arriving at the device input. Then 2Mit AT is the accumulation time of two samples for all ESPs of the first octave, where M is the number of ESPs in an octave. The filtering device works in real time, if during the time L T, Y is calculated for the M filters of the first and M filters of any other octave and the realization time of one ESP is At.

For the sequential implementation (processing) of the ESP, a volume of memory is required; V Y lW words, where K is the number of octaves; M - the number of filters in the octave; N-length of impulse response (number of samples).

When forming the sequence of addresses of memory block 2, you use the method of connecting addressing. The address format is shown in FIG. The first field of the address contains the address of the octave being processed, or the address of the next octave, or the address of the first octave. The number of bits of the first floor is k 1 1orgK. The second field of the address contains the address of the filter to be processed (the number of bits of the third field is the address of the reference number of the impulse response when reading the X data, writing the result Y and writing the source data to the EF of the first octave (the number of bits

 About log N O.

It should be noted that the term Vre occurrence in the i-th octave means the calculation of the output sample Y for M filters of the i-th octave in accordance with the expression (1) and the record Y ,,

as source data

vn

for

i + 1st octaves, entry into each i-th octave is performed twice as often as in i-i-1; With V-M occurrence in any octave, the values of the X. data read addresses are () and the records of the output A differ only in the value in the first after the address.

To illustrate the operation of the device, consider the case of K 3, M 3, N 17.

In this case, the impulse response length counter 21 has a conversion factor N

1.4 12

Jq 15

and 20

n 25 Oh

Q

dd Q

55

and implementation requires n 4 bits, filter counter 36 has a conversion factor of M 3 and m. f 2 bits is required for its implementation, 42 octaves counter has a conversion factor of N 17 and requires n 31or2 5 bits, the counter 44 has a conversion factor of 44 is equal to 8 and for its implementation K 3 bits are required, counter 45 has a coefficient of recalculation N and requires n lopgN 5 bits, counter 43 has a coefficient

recalculation of K- (.2 + 1) 136. -o

To form the first field, adR an, 0, c (initial data record addresses for the first octave) use the sum switch 48, key 30 and priority encoder 47. Priority encoder 47 determines the number of the octave ready for occurrence, which is obtained by the K-bit converter in The K-bit code corresponding to the bit number with the low zero in this word. For example, ХХХО - 000, ХХХ01 - 001, ХХ011 - 010, XI11 - 111, etc. (the extreme first bit is the youngest bit of counter 43, X is an indifferent state).

In addition, a shifter 40 is used, which performs a shift to the right of the current value B of counter 43 by a number of bits equal to K + 1. As a result of this conversion, we obtain the higher n bits of the address of the node 24 of the permanent memory. The low order bits of this address are formed on the counter 21. The sequences read from the fixed memory node 24 form the third field of the address Azmp {4 The state of the counter 42 determines the value of the third field of the address A. The value of the second field of the address Ajan. ;;,, A, corresponds to the state of the filter counter 36.

In order to simplify the description of the operation of the device, we assume that the reception of information in all registers and a multiplier, the switching of counters is carried out by a positive differential clock, the selected output of the decoder 23 corresponds to a zero value, the write mode in memory block 2 is a zero value at control input 34, the read mode is single, the mode of receiving information in the shifter corresponds to the presence of a negative differential at the input of the reception control, and to the mode of issuing information - the state O at the input of the receive control The moment and state 1 at the output of the output control, the mode without accumulation in the multiplier 9, corresponds to the zero value at the control input terminal 18.

The operation step of the device is

 N-1

N cycles of operation of the counter 21 of the length of the pulse characteristic From the N cycles of M --- -1-1 9

tiki,

N-1 -2 cycles are used for reading the X data, ||, one cycle for writing the original data, and two more cycles for receiving and writing the result of calculations v in b: 1 2 memory.

To implement the i-ro entry into the octave, w 3 steps are required. Let the 1st occurrence in an octave constitute the cycle of operation of the device, and the period of its operation constitutes the number of cycles necessary to compute the counts of the last (third) octave,

one . tL, t - 1) 17-8 136

t-O CYCLES.

In the initial state, which let the first tread of the first step and the psov cycle of the device, let the register 46, into which the values for the third address field are received, be recorded code 00001, code 00001 is set in the counter 21 of length n and the characteristic 21 41 - code 00000, which corresponds to the entry number in the octave, from the constant memory node 24 reads the value of the address 01111, which is present at the input of the multiplexer 28, on the control inputs f of the liqabel 28, the code 1 1, which allows the information to pass from the output of the nodes and 24 is permanently stored at the input of register 46, in register 37 — code 00, and in filter counter 36 — number 01, in register 32 — code 01, in register 35 — number 00, at the input of the third state control Z register 35 there is a zero value that permits the passage of the contents of a register to the address input of 2 memories. Thus, at the address input of block 2

the memory is present i ifc (1) 000000001. On the register 34 read control management of memory block 2 there is a single value, the output of memory block 2 is given X, we assume that in memory block 2 there are counts for filters 1- octave, the address input of the node 11 of the permanent memory contains the address 000, at which an arbitrary value is selected from the node 11 of the memory 11, Operand X is recorded in the source data register 5.

In the second cycle of the first step, a clock pulse is sent to the nhol 22, which changes the state of the counter 21 and 00010, the same pulse performs the reception of the code 01111 into the register 46. the state of the registers 41, 37, 32 and 35, uplash the inputs of the adders 48, 10 and the multiplexers 28 and 6 are unchanged. Register 13 accepts lanny X | (signal 17). At address A, (2) 000001 G 1, the operand X is read from memory block 2 (on control Bxo; i.e. 34-1), which goes to} the output of adder 10 (on control input (.- 15 adder 10 - level 1) 3 g; mmator 10 calculates the sum

GU

{

- X ,,)

iia arrives at the first input of the multiplier of its multiplier 9, at the second input I accumulate a multiplier of 9

five

0

five

0

five

which is read from

value n

considered; 1 i of the permanent memory at address 0001. From the node 24 of the current memory of A. 00 0010, the value 0001 1 is read. .

G) -pc: in the clock cycle the state of the counter 21 - 00011, the count 46 receives the count 00011, from the node 24 of the permanent memory at address 0000011 the code 01101 is read, the state prr isters 37, 32, 41 and 35 and the control signals are mull1 The multiplexers and adders cannot be measured. On the address IO / TP of the memory block 2 there is (3) 0 (10000011, by which Xj is read.) The positive difference of the signal 17 is the sum (.) and in the multiplier 9, on the control, In the hoops 18 multiplier 9, the code O is present, in the multiplier the product (X, + is summed with zero.

 On the fourth step of the first step, the state of the counter is 21-00100, the code OP01 is received in register 46, and from the memory 24 memory is taken at address 00 (10100

N. h ,,

which is calculated

read code 00101. The state of the registers 37, 32, 35 and 41, the control inputs of the adders 10 and 48, the multiplexers 28 and 6 does not change. Operand (signal 17) is received in register 13, from memory block 2 at address Aj.,. (D) 000001101 is read out X ,, and is fed to the input of the adder 10 b, the adder 10 is calculated (Xj X,.,) And is fed to the first input of the multiplier 9, the second input of the multiplier 9 contains the value h ,, derived from node 11 constant the memory at address 0010, in the multiplier 9, a positive differential (signal 17) fixes the value (X, + X, 5) h, at the output of the multiplier 9.

In the fifth clock cycle of the first step, the state of the counter 21 is 00101, code 00101 is received in register 46, code 01011 is read from the fixed memory node 24 at address 0000101. As in the previous clock cycles, the state of registers, adders, multiplexers (element you 41, 37, 32, 30, 10, 40, 6, 28) is not measurable.

On the address entry of memory block 2, the address is (5) 000000101, on which operand X is read. Signal i 7 performs reception (Xs +) and hj to multiplier 9 (code 1 at control input 18) and calculates (x, j) bz.

In the sixth cycle (counter status 21-00110), the operation of the device is similar to that described for the second and fourth cycles, except that the value at control input 18 corresponds to 1 and the sum (X, - + X, s) is calculated in multiplier 9 (Xs + X, 5) hj.

The register 13 is written to the operand Xj, from the memory block 2 X is read, in the adder 10 it is calculated (Xj + X ,,) and is fed to the first input of the multiplier 9, to the second input of the multiplier 9 receives the value hj-, read from the node 11 of the permanent memory at address 0011, code 00111 is read from the node 2A of the permanent memory.

The output of the multiplier 9 is fixed () h, + (Xs + X, j) bz.

In the seventh cycle, the state of the counter is 21-00111, the operation of the device is similar to that described for the third and fifth cycles. From the memory node 24, code 01001 is read, code 00111 is received into register 46, to address

five

0 5

ABOUT

five

0

five

the input of memory block 2, address A, (7) 000000111, by which the operand X- is read. Signals. 17, (Xj + X,) and bj are multiplied, -9 (on the control zhol, 18 - number 1), (X + x ,,) -h5 is calculated.

The eighth cycle (counter status 21–01000) is similar to the sixth. In the multiplier 9, the sum of the signal (X, -n X | j) -h, + -f (X;, + X ") -hy - (X 4. x ,,). Is recorded by the control signal 17, and the register 13 is written operand X, from memory block 2 is read Xd, in adder 10 is calculated (Xd) and fed to the first input of multiplier 9, to the second input of multiplier 9 receives the value h read from fixed memory node 11 at address 0100, from node 24 constant 1 amti reads code 01000.

In the ninth cycle, the state of the counter is 21–01001, code 4600 is in register 46, address A is on address Boho of memory block 2 (9)

S-C U T

 000001000, by which the operand Xg is read, multiplied by the central coefficient 1g of the pulse characteristic hg. Signal 17 receives (X -, + Xj) and h to multiplier 9 (at control input 18 is code 1), calculates (Xs) L-,.

At multiplexer 28, the control code is changed to 01, which allows the passage of information from the output of counter 42.

At the tenth cycle, the state of the counter 21 - OtOlO, operand Xj is written to register 13, on control input 15 of adder 10 - code O, which corresponds to the Operand Skip mode, and Xd is fed to the first input of multiplier 9, at the second input of multiplier 9 is present the value of hg, read from the node 11 of the permanent memory at address 0101, in the multiplier 9 is fixed the sum of (X, y) h + + (Xs + X,.,) -bh + (Xj + X ,,) -hj + + ( Xg) h, the register 46 takes the value 00000, the address inputs of the memory block 2 contain the address A (./ 000000000). At the control input 34 of the memory block 2 there is a zero This ensures that X is written to the address. "pOOOOOOOO." In the same cycle, code 00001 is read from the permanent memory node 24 at address 00000.

In the eleventh cocTonmie clock (: h of the clock 21–0101, by the signal 17, the operands Xj and hg are taken into the multiplier 9j, the product is calculated, the control input 34 is set to a single value, and a positive Xfi is received on the control input 15 .

In the twelfth cycle, the state

counter 21-00000, in the register 13, a random operand is written on the ovMMaTope 10, an arbitrary sunma is calculated at the inputs of the push button, 9 is passed through the state, the total Y is fixed at the multiplier 9,

/ V

  X, - which

 . n

,) h, П Х i- X pass cheoez

i Xi + X, l) bz

fXghj

a) bv multiplexer 2 memory

fij is fed to the input of the block and the record (it is located at the address A-j, 010000000. At the control input is a cop about: control pe ifcHi i;: oc g ;: w, -m register 32-1., block 30 repeat

Oh lei

35 -

- M V

B; fcvci ui-ir pafto iT.i device on h a p h ;; is-l

Г) ou ую ую ций ou ou T T T ч н on on oniis, ;;; ;,one. h) that

1-g olderinda gn

 . Phil F with a

; OIC) rw VstrojsTV-; with M7 I am excluded Chengp BbinonHHKjTCF

 a n i a n nymi dd s.k- with video

Denoting the processing of the Kn octaves of the ghrim V-M is 1 and in liy (K), Let the real) algorithm i i., I.K) compose the device operation cycle, a); ; en ;; p I: counts for l.O. Led MI OhTiifibi his period.

lieuC. designations consider pa6oTv devices.

The period of operation of the unit

A P, w (. 2 -.- t) cycles 17 (1 + J + 4i

- one /. eight

(36

cycles

(note tzk / xe, in the peak of the year and O1rntsionalnym difference (inversion of the older bit of the counter 36 filters) you are with the contents of the counter 43 in s / 1Rigatel 40, with the previous value of the previous digit and the negative value of the older digit ss. The counter 43 is set equal to the number of bits equal to the number of 6 bits (oy 1st octave plus unity in; even at the output (motor 40,

)

 j

0

i

IN 1 / . 9

cycle 1 1st state of the counters - 4 and 43 is changed to i + 1-e, K bits of the counter 44 are fed to the input of the priority encoder 47, where they are converted into the code g to the octave of processing K, and the input to the register 35. Using the adder 48, the code READY1 to the processing of the octave, increased by one (K 4 1), is present at the control input of the shift 40 and at the input of the register 32, in the shift 40, the contents of the counter 43 are shifted by K + .1 bit to the right and by the end of the i-ro cycle, the result of the shift is present at the input of the register 4 1, On this i-th cycle of operation of devices It ends with Z,

In the i + lM cycle, the transfer signal, iiof the output of the counter 36, you / ju 32 cad K + 1 is written, in register 35 - K. The state of the counters 42 and 43 is changed to i -t 2 and t, d.

Ph o m l l i

/ forsignal for digital phytra- /, g;, 1 supporting operap / ion block, b 101 memory, addressing block and gen., tact x impediments, the output of which is connected to the input of the address block c.rLiuin, first and second address the outputs of which are connected to the first and second address blocks of the memory block, respectively, the information goho of which is connected to the output of the re-:. L1.t-tgov operational unit, first, vtszroy, third and fourth control; pop; and its inputs are connected respectively to the first, second, third and fourth control n, 1ho ;; am addressing unit, fifth control output which is connected to the write control input by reading a memory block whose output is connected to the first information input of the operation unit, the second g (whose information input is under Kjrt04; ui to the third address output of the addressing block, the fourth address output of which is connected to the third address input memory block, the operation block contains the node of the permanent memory, the source data register; the output register accumulating

a multiplier, a data register, a NOT element, an adder and a multiplexer; the information input of the input data register is the information input of the filter, and the output of the data register is connected to the first information input of the multiplexer, the output of which is connected to the information input of the decoder register and the output of the results of the operation unit, and the output of the output register is the information output of the device, the second information input, the multiplexer is connected to the output of the accumulator multiplier, the first and second information inputs of which are connected to the outputs of the fixed memory node and adder, respectively, the first input of which is connected to the information input of the data register and is the first information input of the operation unit, the second information input of which is the address input of the fixed memory node, the output of the data register is connected to the second input of the adder, the synchronous input of data reception of the accumulating multiplier is connected to the input of the NOT element and is the first control input of the operation unit, the second control input of which is the data accumulation synchronization accumulative multiplier, the data output synchronization input of which is connected to the synchronous input of the data register and connected to the output of the NOT element, the control input of the multiplexer is connected to the synchronization inputs of the adder and the input data register and is the third control the operational input of the operation unit, the fourth control input of which is the synchronous input of the output register, the addressing unit containing the impulse response length counter, decoder, node a fixed memory, an OR element, a key, four registers, two octave counters, a priority encoder, a multiplexer, a NOT element and an adder, and in the addressing unit the counting input of the impulse response length counter is connected to the synchronous input of the fourth register and is the input of the addressing unit, and the information output of the impulse response length counter is connected to the input of the decoder and the first address input of the fixed memory node,

0

five

0

five

0

five

0

five

0

five

the outputs of the bits, in addition to the low-order, impulse response length counter, are the third address output of the addressing unit, the first control-; The output of which is a low-end output counter of the impulse response length; The key input is the third control output of the addressing unit, the fourth output of the decoder is connected to the second fy control input of the multiplexer, the fifth output of the decoder is connected to the second input element 1, the state control input of the outputs of the first register and is the fourth control output of the addressing unit, the output of the element OR is connected to the input of the element NOT and is the fifth control output of the addressing unit the second register, the information output of the first octave counter is connected to the first information input of the multiplexer, the second information input of which is connected to the output of the node permanently), the output of the third register is connected to one third the multiplexer information input and the second address of the fixed memory node, the multiplex output is connected to the information input of the fourth register, the output of which is the first address output of the addressing unit; the information input of the second register and the first input of the adder, the second input of which is the input of the device constant setting, the output of the adder is connected to the information input The first register, the information input of the key is the input of the device code setting zero, the outputs of the first and second registers are connected to the output of the key and are the second address output of the addressing unit, which, in order to simplify the device, the addressing unit contains a filter counter , the fifth register and the shifter, the transfer output of the counter of the impulse response length is connected to the counting input of the filter counter, the transfer output of which is connected to the counting inputs of the first and second octave counters, synchronous inputs The second and third registers, the information output of the filter counter is connected to the information input of the fifth register, the output of which is the fourth address output of the addressing unit; information of the shifter is connected to the output of the element NOT, the input of which is connected to the output of the M-th bit of the filter counter (M is the bit of the filter counter), the output of the (M-1) th The view of which is connected to the shifter output control input, whose information output is connected to the third register information input,

s

h N -d

13815D1

H

Claims (1)

Formula of invention / construction for digital filter <. ' something containing an operating unit, a bit of memory, an addressing unit and a gene. 1T., ·· clock pulses, the output of which is · connected to the input of the addressing unit, the first and second address outputs of which are connected respectively to the first and second address inputs of the memory unit , information gathering is connected to the output of D-jv.ni.tagov operation unit, the first second, third and fourth control inputs which are connected respectively to the first ^7, second, third and fourth control outputs of the addressing unit, fifth control output to the other is connected to the third address output of the addressing block, the fourth address output of which is connected to the third address input of the memory block, the operation block containing a constant node memory, register of source data, output register, accumulating 1 1 multiplier, data register, element NOT, adder and multiplexer, while the information input of the source data register is the information input of the filter, and the output of the source data register is connected to the first information input of the multiplexer, the output of which is connected to the information input of the output register and is the output of the results of the operating unit, and the output of the output register is the information output of the device, the second information input of the multiplexer is connected to the output of the accumulating multiplier, ne the first and second information inputs of which are connected to the outputs of the permanent memory node and the adder, the first input of which is connected to the information input of the data register and is the first information input of the operating unit, the second information input of which is the address input of the permanent memory node, the output of the data register is connected to the second the adder input, the data input clock of the accumulating multiplier is connected to the input of the element NOT and is the first control input of the operating unit, second the control input of which is the data storage sync input of the accumulating multiplier, the data output clock of which is connected to the data register clock input and connected to the output of the element NOT, the control input of the multiplexer is connected to the clock inputs of the adder and the source data register and is the third control input of the operation unit, the fourth control input of which is sync input of the output register, and the addressing unit contains a pulse length counter, a decoder, a constant node memory, OR element, key, four registers, two octave counters, priority encoder, multiplexer, NOT element and adder; moreover, in the addressing unit, the counting input of the impulse response length counter is connected to the fourth input clock input and is the addressing unit input, and the length counter information output impulse response is connected to the input of the decoder and the first address input of the permanent memory node, the outputs of the digits, except for the youngest, the length counter of the impulse response are the third address output of the block addressing, the first control output of which is the low-order output of the impulse response indicator, the first output of the decoder is the second control output of the addressing unit, the second output of the decoder is connected to the first control input of the multiplexer, the third output of the decoder is connected to the first input of the OR element, the control input of the key is the third control output of the addressing unit, the fourth output of the decoder is connected to the second control input of the multiplexer, the fifth output of the decoder dklyuchen to the second input of the OR gate, the input control condition of the outputs of the first register and a fourth control output of the addressing unit, an output of the OR gate is connected to the input ⁷ of the element HE and the fifth control output of the addressing unit, an output of NOT is connected to the input of the control state of the second register output, the information output of the first octave counter is connected to the first information input of the multiplexer, the second information input of which is connected to the output of the permanent memory node, the output of the third reg The country is connected to the third information input of the multiplexer and the second address input of the permanent memory node, the output of the multiplexer is connected to the information input of the fourth register, the output of which is the first address output of the addressing unit, the information output of the second octave counter is connected to the input of the priority encoder, the output of which is connected to the information input the second register and the first input of the adder, the second input of which is the input of setting the device constant, the output of the adder is connected to to the input of the first register, the information input of the key is the input of setting the zero code of the device, the outputs of the first and second registers are connected to the output of the key and are the second address output of the addressing unit, characterized in that, in order to simplify the device, the addressing unit contains a filter counter the first register and shifter, the transfer output of the impulse response length counter is connected to the counting input of the filter counter, the transfer output of which is connected to the counting inputs of the first and second octave counters, sync odes of the first, second and third registers, the information output of the filter counter is connected to the information input of the fifth register, the output of which is the fourth Address output of the addressing unit, the information output of the second octave counter is connected to the information input of the shifter, the shift control input of which is connected to the output 5 of the adder, the input control input information of the shifter is connected to the output of the element NOT, the input of which is connected to the output of the Mth discharge of the filter counter (M is the digit capacity of the filter counter 10), the output of the (M-1) th discharge of which is connected to the input of the output of the shifter whose information output is connected to the information input of the third register n 4 Ef \ • 1 Ef \ • < F • * ...} • • • • • • • • • Ef g 1 Ef 2 Ef I ... Ef 1 Ef t ef s · · · - to • / field 2 pale 3 pale The address of the i-th address on the i-th surface is /, or the address t + / -and ond / /, or the address of the / -th omtada (I ‘Adrada address of the filter (pt) The account / daengag address of this Ku-n _t or the address of the record of the result is Y and, or the address of the record is the claim. data (21. FigF