SU842799A1 - Multiplying device - Google Patents

Description

(54) DEVICE FOR MULTIPLICATION

one

Isoretation refers to computing and can be used in arithmetic devices of digital computers.

A device for multiplying numbers is known, based on memorizing transfer numbers and performed by shifting the partial plays to the right by one bit, with multiplier analysis, starting with the lower bits, and storing the younger part of the product in the multiplier register. The device also contains a memory trigger, an adder - two additional low-order bits. The multiplication is accelerated by analyzing the two digits of the multiplier 1.

The disadvantage is that if both figures are equal, then there will be no acceleration of multiplication, besides - the device is characterized by a large amount of equipment.

The closest to the proposed device is the device, which contains the multiplier registers, the multiplicand, two registers of partial products, two adders, the control circuit and the switch. The operation of this device is that simultaneously

multiplication of the multiplicand by the upper and lower half of the multipliers is carried out. Adding a multiplicand to the contents of the first

the register of partial products, successively higher multipliers, the addition of the multiplicand to the contents of the second register of partial products is controlled by sequentially younger bits. The processes run simultaneously, therefore, in general, the multiplication time is reduced. For the summation of two partial products, one of them is shifted PP / 4 times, where the number is the number of bits of the multiply and through the switch goes to summation with each other partial product 2.

The disadvantage of the device is low

0, determined by the fact that before adding two pieces of work, additional time is required for 1p / 1 shifts.

Multiplication time of this device

5 is

 (-iVfc --tt / addl, 1, 1 c.f, t ,. ° e.

where one shift time em. ... the time of one sum; Vavi;

0

mn - the number of bits

multiplier;

. (j-l) is the shift time of the multiplier registers;

t 5 is the shift time of the partial products, the results of the parallel I multiplication; . Bc -c - time: summation

two partial works.

The purpose of the invention is to increase speed.

The goal is achieved by having a multiplying device comprising first and second shift registers of partial products coupled with accumulators, switch, multiplicative register, multiplier storage unit, control unit, the first output of which is connected to the shift control inputs of the first and second partial product registers and with the shift control input of the multiplier storage unit, the second output of the control unit is connected to the write inputs of the first and second registers of partial products, the third output The control unit is connected to the gate input of the multiplicable register and the installation inputs of the partial work registers; the fourth output of the control unit is connected to the control input of the switch, contains a multiplier distribution unit containing the AND elements, the multiplier storage unit contains two shift registers of even and odd multipliers, respectively the outputs of the even elements AND the multiplier distribution block are connected to the corresponding inputs of the register of the odd bits of the multiplier, the first inputs of the AND elements of the block the multiplier distributions are connected to the inputs of the device multiplier, and the second inputs are connected to the third output of the control unit, the outputs of the multiplicable register are connected to the first input of the AND elements of the first and second groups, the output of each AND element of the first group is connected to the first input of the corresponding bit of the first adder, the outputs of elements AND of the second group are connected to the inputs of the switch of the first group, the second inputs of each element AND of the first group are connected to the output of the register of even bits, the second input of each element AND the second group nN register connected to the output of odd bits MSB outputs of the first shift register partial products are connected to second inputs of bits of the first adder shifted by one bit towards LSBs, yields low bits of the first shift register partial products

connected to the inputs of the same register with a shift by one bit towards the lower bits, the outputs of the bits of the second register of partial

works connected to the first inputs of the bits of the second adder with a shift of one bit in the direction of the younger bits, the second inputs of the bits of the BTCfporo adder are connected

With the outputs of the switch, the inputs of the second group of which are connected to the outputs of the gaps of the first register of partial products.

The essence of the invention is as follows.

Multiplication is carried out separately for even and odd multipliers. In this case, to obtain the complete product, it is not necessary to shift the t / 2 times the partial products relative to each other. In Prototype, the need for shifts is due to the fact that multiplication occurs separately by the older and younger half of the multiplier bits.

FIG. 1 shows a block diagram of a device for multiplying; in fig. 2 is a multiplication scheme; Fig. The design of the control unit.

A device for multiplying a block G of the multiplier distribution, consisting of AND 2 elements, shifting the register of 3 even bits and shifting the register of 4 odd bits, constituting the multiplier storing block 5, multiplier B register, AND 6 - 8 element group, block 9 control, co1 switch 10, adders 11 and 12, which shift registers 13 and 14 of partial products, outputs 15 18 of control block 9. The outputs of all odd elements AND 2, block 1 of the multiplier distribution are connected to the information inputs of the register 3 even bits, the outputs of all even elements AND 2 of the block 1 of the multiplier distribution are connected to information inputs of the register 4 odd bits.

The gate inputs of the elements AND 2 of block 1 and the register of multiplicable b, and the inputs of the installation in registers 13 and 14 are connected to the output 17 of the control junction 9. The signal at output 17 records the multiplicand multiplication in regis b in registers 3 and 4, and in register 3 a record of the four is provided. bits, in register 4, odd, in registers 13 and 14, zeros are written in all bits. The outputs of the multiplier register B are connected bitwise with the first inputs of the adder 11 through the elements 7 and the first inputs of the adder 12 through the elements 8 and the switch 10, the gate inputs of the elements 7 and 8 connected to the outputs of the lower bits of registers 3 and 4, respectively. In the process of multiplying, the first inputs of the adders 11 and 12 receive the values of the multiplicand or logical zeros, depending on the value in the analyzed even and odd bits of the multiplier, which output the registers 3 and 4 from the registers 3 and 4 respectively. The second inputs of the bits of the summator 12 and 11 are connected to the outputs of the register 14 partial products and the output terminal of the register 13 of the partial products, respectively, the connection of the bits is performed with an offset at which the output of the K-th register register 14 or 13 is connected to the input (Kl) -ro bit yes adder 12 or 11, where K is the number p yes. The second half of the outputs of the register of 13-piece works is connected to the second half of the inputs, adjacent to the bits of this register. Each output of the second half of the register bits of the 13 partial outputs is connected to the (i-l) input of this register, where i is the number of the discharge. The first half of the first group of inputs of the switch 10 is connected to the outputs of the elements And 8, the second half of the first group of inputs of the switch 10 is connected to the logical bus O Such connection of the inputs of adders 11 and 12 provides a shift of the result of the summation in registers 13 and 14 by one bit in the direction of the younger bits on each clock cycle, which additionally increases the speed without increasing the amount of equipment. The registers 3,4, 13, and 14 are shifters. The shift control inputs are connected to the output 15 of the control unit 9, on which the shift control pulses are generated. Register control inputs 13 and. 14 are connected to the output 16 of the control unit 9 on which they are formed. write pulses. The control input of the switch 10 is connected to the output 18 of the control unit 9. Depending on the signal at output 18 (logical 0 or 1), switch 10 connects its outputs bitwise with the first group of inputs or the second. The first group of inputs is connected to the outputs of the elements .And 8 and to the logical bus. Oh, the second group of inputs is connected to the outputs of the shift register of 13 partial products. The device works as follows. Before multiplication, the multiplier is recorded in the register b of the multiplier in registers 3 and 4 and zeros in registers 13 and 14 by a control block 9, which generates a pulse at the output, -. Multiplication occurs in two to obtain two partial products and to add them together . During the first stage, block 9 generates at the output 18 siggsh, whose presence at the control input, switch 10 provides for the connection of a part of the inputs of the switch 10 with the outputs of the elements And 8 and a part of the inputs with a bus. ABOUT . As a result, the multiplicand from the outputs of register 6 through the elements of AND 8 and the switch 10 is fed to the inputs of half of the bits of the adder 12, the inputs of the second half of the bits of which are logic O. Obtaining partial products is carried out simultaneously in two registers 13 and 14 in a pact way by adding and shear. In each clock cycle, the control unit 9 generates alternately the write and shift pulses at the outputs 16 and 15. When the write pulse of registers 13 and 14 arrives at the write inputs, the summation results in adders 11 and 12 are written to these registers. A shift pulse is formed at the output 15 of block 9 and eliminates the content shift in registers 3.4 13 and 14. Thus, a shift is provided each summation result in registers 13 and 14 relative to the previous result by two bits. Control unit 9 generates (-1) write pulses ipch shift pulses to the control inputs of registers 3, 4,13,14. The second stage (obtaining the complete product) is implemented as follows. Block 9 changes the value of the signals at output 18 to the opposite. At this, switch 10 switches the first partial product from the outputs of register 13 to the inputs of adder 12 with a shift by one bit. Block 9 directlea forms. at the input 16, a write pulse, which is provided for writing to the work register 14. In this way, the addition of two partial operations and obtaining the complete product is ensured. The control block 9 contains delay elements 19 and 20, trigger-21, AND elements 22.23, generator 24, NOT element 25, counter 26, element OR 27. When a signal multiplication is received at the Start device, it sets to output 17 and through element 19 Support for RSrigger 21 installation input; The delay time of element 19 must; More time is required to write to registers 3, 4, and 6, and settings in O registers 13 and 14.

The trigger 21 provides at the output 18 of the control unit 9 a logic level at which the switch Yu connects the outputs of the AND 8 elements to the inputs of the adder 12. At the same time, the output signal; trigger 21 opens, elements 22 and 23. The second inputs of elements K 22 23 from the generator 24 receive pulses of direct and inverse polarity, respectively, the inversion of polarity provides an element NOT 25. Pulses from the output of element And 22 arrive at output 15 of block 9 control and meter input 26.

After passing through the counter

26 the number of pulses necessary to obtain partial products, at the output of the counter. 26, a pulse is generated that sets the trigger 21 to its initial state. In this case, the elemental switches 22 and 23 are closed, and the output of the control unit 15 stops the output of the shift pulses, the signal at the output 18 is inverted and the switch 10 connects the outputs of the register 13 to the input of the adder 12.

The formation of recording pulses at the output 16 of the control block 9 is provided from the output of the element OR 27 At the stage of obtaining partial products at the first input of the element OR

27 pulses come from the output of the element 23 at the stage of obtaining a complete product to the second input of the element OR 27 from the output of the counter 26 through the delay 21 the pulse arrives, the delay time of which must be longer than the switching time of the switch 10.

Increased speed due to reduced time

multiply by

and

s.d.

combining the addition with a one-shift shift in the production of partial products.

The multiplication time of the device is

(2

- -roi

Comparison of formulas (1) and (2) shows that in formula (2) there is no. D W, i.e. the time of multiplication of this device is less than the time of multiplying the known device by this value. Most often, C x t,. In this case, as can be seen from a comparison of (1) and (2), the multiplication time decreases by a factor of 1.5.

The proposed principle of speed increase allows the device to be implemented for multiplying with a large speed increase. For this, the storage unit of the multiplier should be executed not in the form of two registers (even and odd bits), but in the form of n - registers. In this case, the first register p is written - first, (n + 1), and (2n + 1) -th, ... bits of a multiplicand, in the second register - the second, (n + 2) -th, ( 2n + 2), i ,. bits of the multiplicand, etc., to the n-th register, in which the nth 2nth is written, ... bits of the multiplier. Such a device contains n registers of partial products and n adders. The outputs of the bits of the registers of partial products are not connected with adjacent inputs of the adders, but with the inputs of the p-1 bits.

Claims (2)

1. Authors certificate of the USSR 357561, cl. G 06 F 7/39, 1970. 2.Kartsev M.A. Arithmetic 0 devices of electronic digital machines, M Fizmatgiz, 1958, p. 133, fig. 35 (prototype). I Chl „“ V Xi iXiXo VYVVY Well, .. yUHYY y, l ... X tXsXtXM / ifJf / tA s fJffW, .YT9 y 9 7 77777 Z /.,.,; .., “; r2 # rVjfir / C multiply Of eaiHtie bits multiplyAvl pvrvov part npOUtMeftUt z ,; z, z; zizsZl, z, ziz, Zo z /. ,, z, z, z, „„ .. 5 "SgSaSrSeSsSiSjSiSiSfSo occurrence fn ....; j -r /;". ,, ... multiplier yi (Xn ...) YjfXn ... Х ХХГХ Х,) У (Х „...) (1Хо) - -1. .:. The second partial 2 „2gZ Z Z Zl, the product.