SU1205152A1 - Digital filter - Google Patents

Description

1205

the stroke of the second element I is the third output of the block and is connected to the counting input of the cycle counter, the output of which is connected to the first input of the third AND element whose output is the fourth output of the block and connected to the input of the element. The invention relates to specialized means of supervisory technology and can be used for digital signal processing, in particular, for digital filtering in various digital complexes in radio communications, radio location systems, radio navigation, information-measuring systems and.

The purpose of the invention is to increase the speed of filter rebuilding.

FIG. 1 shows the functions. Nonal non-recursive digital filter circuit; in fig. 2 - functional. On the diagram of the synchronization unit / in FIG. 3 - temporary AHarpaNH ibi digital filter operation.

The digital filter (Fig. 1) contains: iKHT To shift registers, ii. M, register 2 slice encoder 3, register 4 addresses, memory block 5, adder b, output register 7, OR element 9 register code, deprafrater 10, block 11 synchronization, bits 12 of the register 2 slice, information inputs 13 and outputs 14 of the digital filter, respectively, and clock input 15 of the filter.

Block P (Fig. 2 contains clock 15 and informational 16 inputs, first 17, second 18, third 19 and quarter 20 output, R5 trigger 21. HE element 22, first 23, second 24 and third 25 elements I. counter 26 cycles and delay element 27.

The operation of a digital filter is described with an algorithm

MnbZIa; ;;,. ()

where Y (n) is the output sample of a fichstra at the nth instant of time;

N is the number of conclusions from the register's biasBbiX l: “the number of operands involved

52

whose output output is connected to the installation input of the cycle counter, the inverse output of the RS flip-flop is connected to the first input of the second element AND, the second inputs of the nerve, the second and third elements AND are combined and are the second input of the block

one

In the formation of the transfer function

and the coefficients that provide the desired impulse response or transfer function of the filter; Z - - samples of input signal X represented in binary digital code; (for a non-recursive filter, 2, .. ,, N for recursive 1, ..., V) and delayed output signals Yp., (, 2 ,,., R) for a recursive filter,.

The samples of the input signal, and for the recursive filter and the delayed samples of the output signal, are represented by the bit (including the sign bit) number in the additional code with a fixed comma:

“:

0

five

U

S, -Z, - +. 2-% (2)

where Z, 3j-Oj1, ..., B-1 are binary variables that can take the values O or II j II

v °

 - the value of the sign bit.

Substituting (2) in (i), a digital filtering algorithm is obtained in the form: N ВН; ; N 6-1; N;

Y (n) r.a., Z: K 2- -i: a, E ° 2: 2 2: a; S. - jH; m -, 1 1

W S-1 i

-5th - - --.- р (n:,: „..,;) dz)

 . . N.

F (,,, „Х) (з),. Ои, .. ,, вч .: (4)

The digital filter works as follows.

3

Before starting the calculation of the next 11th output countdown in the first BbDf shift register 1.1 under the control of the write pulses shown in FIG. Ze, a regular sampling of the input signal X is input. A pulse of recording new operands (Fig. Ze) is formed at the fourth output 20 of control unit 11 by passing a pulse from clock input 15 through the third element 25 at the counter 26 cycles counting B cycles , generates a signal to open the third element AND 25. The pulse from the fourth output 20 of the control unit is fed to the control inputs of the parallel recording of the first shift register 1.1. The same impulse with a delay of 1) (T / 2bo T), where T, the period of clock pulses (Fig. 3a), carried out on delay element 27, flushes the counter of 26 cycles, preparing it for counting cycles when calculating the next n- th day off counting. Now in the N shift registers 1.1-1.N there are operands Z ,, Z2, ..., Zf, which for the considered non-recursive digital filter are the N last counts of the input signal Xn, Xn ,, ,,. .., X,. „.,.

The calculation period of one output sample Y (p) according to the algorithms (3) and (4) in the proposed digital filter consists of B cycles, the boundaries of which are shown in FIG. Ze dashed vertical lines.

At the beginning of each of the B cycles, the RS-trigger 21 is in the zero state (timing diagram in Fig. 36. The end of the next cycle occurs when there is a zero potential at all inputs, and therefore at the output of the OR 8 element, which zeroes RS-trigger 21. In this case, the clock pulses (Fig. Za) from input 15 pass through the second element I 24 to the third output 19 of block II (time diagram in Fig. Ze). On the leading edge of these pulses in each successive j- m (, 1, ... ,, In-1) the cycle is shifted to the right by one bit of content in output register 7. Thus, in accordance with formula (3), multiplication by 2 of the sum accumulated as a result of processing the previous ones (with

05152Л

numbers less than j) bits of the operands. The pulses from the third output 19 of the control unit are also fed to the counting input of the counter of 26 cycles, 5 which generates a signal for the end of processing the next sample after counting the cycles B, opening the third element I 25. These same (Fig. Ze) pulses shift

to one bit to the right of the operands stored in the shift registers 1.1-1. N and fixing the next (j-ro) slice of the operands z | , z ,. .., Z}, in the N-bit register of the second slice. The slice fixed in register 2 is analyzed by the N input element OR 8. In this case, two situations are possible.

1. All bits in the cp20 register for 2 have zero values. Then, at the output of the SHSh 8 element, there is a zero level, R5-trigger 21 remains in the zero state, the first And 23 element is closed, the second

25 element and 24 is open. In this case, the clock pulse (sync pulse) does not pass through the first element And 23. to the second output 18 of block 11, therefore the information from the encoder 3 in the registers of address 4 and code 9 is not recorded. Memory block 5 and adder-subtractor 6 are not activated, since the first output 17 of block 11 (direct output of the RS flip-flop) is zero. No arithmetic

- the digital filter does not perform operations in this situation. The next clock pulse passes through the second element 24 again to the third output 19 of block 11 and, as described above, the next (j + 1) -th cycle of fixation and analysis of the slice is performed.

Ii. If during the jth cycle at least one of the triggers 1.1. - 1.N of the register 2 slice is in

 state, then a single level appears at the output of the input element OR 8 and the RS flip-flop is set to one, prohibiting the passage of clock

50 pulses through the second element And 24 and passes them through the first element And 23 (timing diagrams in fig.Zd).

At the same time, during each next P period of clock pulses, 55 pulses, the code from the output of register 2 of the cutoff enters the encoder 3, at the output of which the L-bit code () of the highest number is generated (in

full cycle) a significant bit of the slice of the operands 7: (i is the sequence number of the bit, its priority) having a nonzero value. The bits in the slice register are numbered, for example, from bottom to top and take the value, 2, .... . N

The code of the highest non-zero bit on the leading edge of the clock pulses, coming from the output of the first element And 23, is recorded in registers - 9 codes and 4 addresses. In this case, the signal from the direct output of the RS flip-flop 21 (timing diagram in Fig. 3B) activates memory block 5 and subtractor-subtractor 6. From the cell of memory block 5, the address of which corresponds to the high-order single-bit code of slice Z. The weighting factor a is calculated, which in the adder-calculator 6 is added to the previously accumulated amount stored in the output register 7 (the shift in the output register after the arithmetic operation is not performed). Thus, the operation of calculating Φ (j) by the formula (4) and its simultaneous addition with the partial sum obtained in the previous cycles (3) by adding (without shifting) the value of a, read from the memory, with the output register 7

During the same clock cycle, the priority code of the bit Z recorded in the register of code 9 is decoded in the decoder 10, the activated output of which zeroed i -and trigger 12.1 in the register 2 of the slice. Now the N-input element OR 8 and the encoder 3 analyze the new code at the output of the register 2 slice and again two situations are possible: 1 the output of the element OR 8 is zero and the slice processing cycle ends; 2) at least one trigger (from among those with priority less than i in register 2, the slice is in a single state. In the latter case, the described processing of the new higher nonzero bit repeats. This happens until all bits of register 2 are slice

ten

15

20

25

12051526

will not accept a zero value. At this, the slice processing cycle ends, the zero level appears at the output of the N-input element 1 OR 8, the short-switch trigger 21 switches to the zero state, the next shift in the output register 7 and the shift registers 1.1-1.N and the new one (j + 1) -th slice is fixed in register 2 of the slice - a new (+1) -th cycle begins. After execution In the slice processing cycles, new readings and processing of new samples are entered and extracted from the digital filter.

the samples are repeated. I

A recursive filter differs from a non-recursive filter only in that for recursive filters, the N shift codes 1,1-l.N are divided into two groups of V and R () serially connected registers. The parallel (t-bit) input of the first register from the second group of R.1 is connected to the second m-bit group of the outputs of the output register 7, which is the output of the filter 14. The control inputs of the parallel recording of the first registers of the first and second groups VI and R.1 are combined and connected to the fourth output 20 of the control unit.

Before starting the calculation of the next output sample under the control of pulses (Fig. Ze) in the first shift register of the first group V. 1 by a parallel code entry — the next input sample is X, and in the first shift register of the second group R. 1 - the previous output count Y, coming from the output of the digital filter. In the N shift registers there are operands, ..., Z which represent the V last samples of the input signal Xn, X,,. . . , X, y , stored in the registers of the first group, and R of the last samples of the output signal Y, Y ,. .. jY.gv. stored in registers of the second group. Next, the processing of operands Z, Z2, ..., Z | performed as described above.

thirty

35

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45

50

20

Editor L. Pchelinska

Compiled by V.Zinin

Tehred O. Vashchishin Proofreader G. Reshetnik

Order 8536/51 Circulation 709Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d, 4/5

Branch GPP1 Patent, Uzhgorod, st. Project, 4

Claims (2)

1. A DIGITAL FILTER containing N shift registers, a memory block, an adder, a synchronization block and an output register, wherein the information input of the first shift register is a filter input, the output is го-th (i = I, 2, ..., N-1) the shift register is connected to the information input of the (: +1) th shift register, the output of the memory block is connected to the first information input of the adder, the output of which is connected to the information input of the output register, the output of which is connected to the second information input of the adder and is the filter output, characterizedthe fact that, in order to improve performance in the filter tuning mode, it additionally contains a slice register, an encoder, an address register, a code register, a decoder, an OR element, and the output of the jth shift register (j = 1,2, ..., N) is connected to the information input of the jth digit of the slice register, the installation input of the jth bit of which is connected to the jth output of the decoder, the input of which is connected to the output of the code register, the information input of which is connected to the output of the encoder and to the information input of the slice register, whose output is connected to the address by the Glock input of memory, the output of the jth discharge of the slice register is connected to the jth input of the encoder and to the jth input of the OR element, the output of which is connected to the first input of the synchronization block, the first output of which is connected to the read input of the memory block and the clock input the adder, the second output of the synchronization unit is connected to the clock input of the address register and the clock input of the code register, the third output of the synchronization block is connected to the clock input j. -th shift register, the clock input of the slice register, the clock input of the output register, the fourth output of the synchronization block is connected to the input of the parallel recording of the first shift register, the second input of the synchronization block is the clock input of the filter. 2. Filter by π. 1, characterized in that the synchronization unit contains a 45 trigger, an element NOT, a first, second, third AND element, a cycle counter and an elec. the delay moment, and the 5-input of the RS trigger is combined with the input of the element NOT and is the first input of the block, the output of the element is NOT connected to the R-input of the R5 trigger, the direct output of which is the first output of the block and connected to the first input of the first element And, the output of which is the second output of the block, the output of the second element And is the third output of the block and is connected to the counting input of the cycle counter, the output of which is connected to the first input of the third element And, the output of which is the fourth output of the block and connected to the input of the element and whose output is connected to the input of the installation cycle counter, inverse output RS-flip-flop connected to the first input of the second AND gate, the second inputs of the first, second and third AND elements are combined and the second input unit.