SU1307587A1 - Frequency divider with variable countdown - Google Patents

Description

The invention relates to a pulse technique and can be used in automation and computing devices.

The purpose of the invention is to increase speed.

The drawing shows an electrical block diagram of a frequency divider with a variable division factor.

The device contains a pulse counter 1, the counting input of which is connected to the input bus 2, a reset input with the output of the first element 3 coincidence and the left shift input of the shift register 4, whose information inputs are connected to the bus 5 of the division factor code, the shift input right with. the output of the second coincidence element 6, the first input of which is connected to the first output of the trigger 7, the second output of which is connected to the first input of the first coincidence element 3, the second input of which is connected to the second input of the second coincidence element 6, in trigger one 7 and the output of the third element 8 match the first (inverse) input of which is connected to the output bus 9, the output of the decoder 10 and the input of the delay element 11, the output of which is connected to the second input of the third element 8 of the match; the first and second groups of inputs of the decoder 10 are connected bitwise with the outputs respectively

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the pulse counter 1 and the shift register 35 ger 7 transitions from the zero state to the horn 4. The pulse counter 1 contains successively connected triggers 12, 13, the first count of which 12 is connected to the counting input of the pulse counter 1, the reset input of which is connected to the reset inputs the second and subsequent triggers 13, the outputs of all triggers are connected to the corresponding outputs of the counter 1 pulses.

The device operates as follows.

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not once, as a result of which element 3 opens and element 6 closes.

With the arrival of the 2K-TH input pulse, the output of the decoder 10 again n is the signal of the unit level, which, like the first case, goes to bus 9 and to the inputs of elements 8 and 11,

With the arrival of the (2K + 1) th input pulse, the signal at the output of the decoder 10 becomes zero and, in the initial state, the counter 1 and the trigger 7 are set to the zero state. The signals from the outputs of the trigger 7, the element 3 is closed, and the element 6 is open. The control factor for the division factor K is recorded from 1Yin 5 in the n lower memory cells of register 4, and the (n + 1) -discharge code of the specified division factor enters the second group of inputs of the decoder.

five

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five

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When the input pulses arrive on the bus 2, the counter 1 is filled up and codes of numbers corresponding to the number of incoming input pulses are generated at its outputs,

with the arrival of the K-th input pulse, a single level signal appears at the output of the decoder 10. This signal goes to bus 9, to the first input of element B and to the input of element 11. At the output of element 8, in this case there is a zero level. With the arrival of the (K + 1) th input pulse, the code of the number K + 1 is set at the outputs of counter 1 whereby the signal at the output of the decoder 10 becomes zero. This ends the output impulse on bus 9 and prevents the passage of signals through element 8. A single level signal appears at the output of this element, which exists for a short period of time determined by the delay time in element 11. The signal of single level from the element output 8 enters the counting input of the trigger 7, and through the open element b - to the input of the shift to the right of register 4. As a result, the contents of register 4 are shifted by one bit to the right and the code of the number 2K is set at its outputs. At the time of the disappearance of a single level at the output of the element 8 trig

Ger 7 goes from zero -

not once, as a result of which element 3 opens and element 6 closes.

With the arrival of the 2K-TH input pulse, a single level signal appears again at the output of the decoder 10, which, like in the first case, goes to bus 9 and to the inputs of elements 8 and 11,

With the arrival of the (2K + 1) th input pulse, the signal at the output of the decoder 10 becomes equal to zero and, therefore, the pulse ends at the bus 9. At the output of the element 8 a short single pulse is formed, which through the open element 3 enters the left shift input register 4 and to the reset input of counter 1. There is a shift of the contents of register 4 by one bit to the left and the trigger triggers 13 are set to the zero state.

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Thus, bringing the device to the initial state after counting the first 2K input pulses occurs in several steps: trigger 12 is set to zero state immediately after the arrival of the 2Kth input pulse (as every even pulse brings it to zero) Then with the arrival of the (2K + 1) th input pulse, the triggers 13 of the counter 1 and the register 4 are reset, and finally, after the reset pulse ends, the trigger 7 is set to the zero state.

Further, the operation of the device is repeated, with the result that pulses are generated on its output bus, the frequency of which is followed directly

proportional to the input frequency, with the output of the third pulse element and inversely proportional to the specified division factor, and the duration of the output pulses is determined by the follow-up period of the input pulses.

Claims (2)

1. A variable division divider frequency divider containing a pulse counter, the counting input of which is connected to the input bus, the reset input — with the output of the first match element and the shift shift register left, shift information, and trigger input — and the output bus is connected to the input the delay element and the output of the descrambler. 25 2. The divider according to claim 1, characterized in that the pulse counter contains successively connected triggers, the counting input of the first of which is connected to the counting 30 by the input of the pulse counter, the reset input of which is connected to the reset inputs of the second and subsequent triggers, and the outputs of all the triggers are connected to the corresponding outputs of the counter 35 pulses. Compiled by A. Sokolov Editor I. Rybchenko Tehred M. Khodanych Order 1641/55 Circulation 902 VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab, 4/5 Production and printing company, Uzhgorod, st. Project, 4 the input inputs of which are connected to the dividing ratio code bus, the right shift input is with the output of the second coincidence element, the first input of which is connected to the first trigger output, the decoder, the first and second groups of inputs of which are connected to the outputs of the pulse counter and shift register, respectively - with the first input of the third coincidence element, the second input of which is connected to the output of the delay element, and the output bus, about t., which means that the trigger is countable to increase the speed m, his second you the stroke is connected to the first input of the first matching element, the second input to the second input of the second matching element, to the output of the third element coincidence with the trigger input, the output bus being connected to the input of the delay element and to the output of the decoder. 2. The divider according to claim, 1, characterized in that the pulse counter contains triggers connected in series, the counting input of the first of which is connected to the counting the input of the pulse counter, the reset input of which is connected to the reset inputs of the second and subsequent triggers, and the outputs of all the triggers are connected to the corresponding outputs of the counter pulses. Proofreader L. Pilipenko  - - - -.- .- centuries .., ™. Subscription