JPS5910584Y2 - Field brightness detection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device capable of detecting the highest and lowest luminances distributed in a field.

If there are highlights and shadows in the subject, in order to take a photo that satisfies the entire subject without sacrificing either of them, the brightness value of the highlights and shadows must be approximately halfway between the brightness values of the highlights and shadows. A method is adopted in which the value is detected as a field brightness value.

However, with conventional field brightness detection devices that measure the average brightness of the field, the photometric value deviates from the intermediate value depending on the proportion of the highlight and shadow parts. , it was difficult to obtain good photographs.

Therefore, if the maximum and minimum partial brightness of the object scene can be detected, the intermediate value can be easily determined.

Also, if we consider the blackening degree curve (density curve) of a film, for example, the degree of blackening is proportional to the light intensity when the light intensity is within a certain range. In order to obtain a photograph, it is desirable that the luminance of each part of the field falls within the above range.

Even in such a case, it is desired to detect the maximum and minimum brightness of the field.

The purpose of the present invention is to digitally detect the maximum and minimum brightness of each part of the object.

Therefore, the present invention includes a pulse generator that generates a plurality of pulse trains with a pulse frequency that is proportional or inversely proportional to the brightness of each part of the object, and a pulse generator that separately counts two pulse trains selected from the plurality of pulse trains. two counters, a comparison circuit that compares the counts of these two counters,
The output of this comparison circuit opens a circuit that resets the one of the force counters with the smaller number of counts and a gate that receives the output, and one pulse train newly selected from the plurality of pulse trains is sent to the reset counter. a gate circuit that inputs the pulse train, a sequence circuit that repeatedly selects a pulse train, counts the counter, compares the number of pulses, resets one counter, and opens the gate circuit, and and a digital display device installed on each of the above two counters to display the scene. The feature is that it is designed to digitally detect the maximum or minimum of each partial brightness.

Examples of the present invention will be described below.

Note that in each figure, the same circuits are indicated by the same symbols.

FIG. 1 shows an embodiment circuit in which each pulse train is sent out with a time lag and a comparison operation is performed each time a pulse train is input to one of two counters.

In the figure, reference numeral 1 denotes a clock pulse oscillator, and a self-running multi-vibrator or the like is used.

2 is a ring counter for sequence control;
Each time a clock pulse is input from the pulse oscillator 1, the output "1" moves from 2a to the right in the figure.

3, 4. Reference numeral 5 denotes a pulse oscillator whose frequency is determined according to the brightness of each part of the field. For example, it is a pulse oscillator whose frequency is determined according to the brightness of each part of the field. The oscillation frequency is determined for each.

Therefore, although not shown, the number of pulse oscillators is usually the same as the number of photoelectric conversion elements 6.

7, 8. 9 is an AND gate, AND gate 7
The stage 2b of the ring counter 2 is configured to pass the pulse from the pulse oscillator 3 only while the output is "1".

Similarly, in the AND gate 18, the 2e stage outputs 4i 1 1*
During this period, the AND gate 9 passes the pulse from the corresponding pulse oscillator only while the 2h stage has an output of "1".

Therefore, the number of pulses in the pulse trains sent out from each AND game 7, 8, and 9 corresponds to the luminance of each part of the object field, and each pulse train is sent out sequentially with a predetermined time interval. become.

The lth pulse train sent out from the AND gate 7 is configured to be input to the counter 14 via the OR gate IQ and the AND gate 12.

The second pulse train sent out from the AND gate 8 is arranged to be input to a counter 14 or 15 via an OR gate 10 and an AND gate 12 or an OR gate 11 and an AND gate 13.

The third pulse train sent out from the AND gate 9 is similarly input to the counter 14 or 15.

Counters 14 and 15 each have an AND gate 12. 13
A counter that counts the number of pulses of each pulse train inputted through the counter, and may be a binary counter or a decimal counter.

16 and 17 are digital display devices added to each counter 14 and 15, and a well-known seven segment type display device or the like is used.

18 and 19 are force counters 14. The count value of 15 is shifted into the shift register 20. This is a circuit for writing to 21, and as is well known, it is an AND of a number equal to the number of bits of the counter.
Confidential at the gate.

The write circuits 18 and 19 are two of the ring counters 2.
Writing is performed when the output of the C stage, 2f stage, etc. is "1".

The shift registers 20 and 21 are AND gates 3, which will be described later.
3, the written signal is shifted to the right in the figure, and the outputs of the 2d stage, 2g stage, etc. of the ring counter 2 are changed from "1" to "0".
It is arranged so that it is reset when the value changes to 91.

22 is a comparison circuit, which includes two shift registers 20.
21, and if the value in shift register 20 is equal to or larger than that in shift register 21, a signal "1" is sent from the Y terminal to shift register 2.
When the value of 0 is smaller, a signal "1" is output from the X terminal.

Although the configuration of such a comparison circuit 22 is well known, for example, the one shown in FIG. 3 is used.

In the figure, the comparison circuit 22 is a NOT game} 23, 2
5, AND gates 24 and 26, an OR gate 27, and a matching circuit 28.

This matching circuit 28 includes shift register 20. When no numerical value is written in the shift register 21, that is, when each stage of the shift registers 20 and 21 are all "0", no output is made.

In FIG. 3, the numbers shown in the diagram are in the shift register 2
．． Assume that it is written in 21.

In this state, the shift register 20. The outputs of the rightmost stage 21 are both "O I+", and the outputs of the AND gates 24 and 26 are "0".

On the other hand, since the output of the coincidence circuit 28 is also "0", X, Y
Both terminal outputs are "0".

Shift register 20. When l shift pulses are input to 21, the signal moves one stage to the right, and the rightmost stage outputs both become "1".
It becomes ゛.

Even in this case, the outputs of the X and Y terminals are "0".

Furthermore, one shift pulse is sent to each shift register 20.
21, its rightmost stage output becomes "1" in the shift register 20 and "0" in the shift register 21.

Therefore, the output of the AND gate 26 becomes "1" and the output is output from the Y terminal.

In this way, the shift register 20. Depending on the magnitude of the numerical value of 21, a signal "1" is output from either the X or Y terminal.

When the numerical values are equal, the coincidence circuit 28 outputs "1", and this output is outputted from the Y terminal via the OR gate 27.

The X terminal output of the comparison circuit 22 is used as a reset signal for the counter 14 and is connected to the S input of the RS flip-flop 29, while the Y terminal output is used as a reset signal for the counter 15 and is connected to the S input of the RS flip-flop 29. It is connected so that it becomes the R input of.

The Q output of the RS processor 29 is applied to the AND gate 113 via the AND gate 12 and NOT gate 30.

Therefore, depending on the output state of the flip-flop 29, the AND
Either gate 12 or 13 is opened.

31 is O which receives the X and Y terminal outputs of the comparator circuit 22;
R gate, the output of the OR gate 31 is the NOT gate 3
After being inverted by 2, it is input to an AND gate 33.

The AND gate 33 is for passing the pulse from the shift pulse oscillator 34, and is for passing the pulse from the shift pulse oscillator 34.
It is designed to also receive outputs from the d stage, 2g stage, and so on.

The operation of this embodiment circuit will be explained.

When one pulse is input from the clock pulse oscillator 1 to the ring counter 2, its 2b stage outputs "1", the AND gate 7 is opened, and the first pulse train from the pulse oscillator 3 is OR'ed to the gate 10, The signal is input to the counter 14 via the AND gate 12.

When the second pulse from the clock pulse oscillator 1 is input to the ring counter, its 2C stage outputs "1", and this output is sent to the write circuit 18. 19 and the count values of counters 14 and 15 are transferred to shift register 2.
Moved to 0, 21.

Since the number of pulses that passed through the AND gate 7 while the stage 2b of the ring counter 2 outputs "1" is the count number of the counter 14, this number is transferred to the shift register 20.
On the other hand, since the count number of the counter 15 is 0, the shift register 21 also remains 0.

When input to the third pano wrestling counter 2,
The 2d stage outputs "1".

Therefore, the pulses sent from the shift pulse oscillator 34 are passed through the AND gate 33 to the shift registers 20 and 21.
The input and written signals are shifted.

The shift register 20 has numerical values, and the shift register 21
Since is O, the Y terminal of the comparison circuit 28 becomes an output ゜“1゛.

Due to this output, the RS flip-flop 29 is reversed from the state shown in the figure, and the AND gate 12 is closed and the AND gate 13 is opened.

On the other hand, this Y terminal output is OR gate 31, NOT gate 3
2 to the AND gate 33, and closes the AND gate 33.

When the fourth pulse is input to ring counter 2,
The 2e stage becomes the output "1".

At the moment the output of the 2d stage changes from ゜"1" to ゜゜0゛, the shift registers 20 and 21 are reset, and the Y terminal output of the comparison circuit 22 also returns to ゜"091.

At this time, the state of the RS flip-flop 29 does not change,
On the other hand, the output of the NOT gate 32 returns to "1".

Since the output of the stage 2e becomes "1", the AND gate 8 is opened and the second pulse train from the pulse oscillator 4 is sent to the counter 1 via the OR gate 111 and the AND gate 13.
5 is input.

When the fifth pulse is input to the ring counter 2, its 2f stage outputs "1", and the count numbers of the counters 14 and 15 are transferred to the shift register 20. Moved to 21.

Since the counter 14 was not reset, the same pulse value of the first pulse train as before is written into the shift register 20, while the value of the counter 15, that is, the value of the second pulse train, is written into the shift register 21.

When the 6th pano reply is input to the ring counter 2, the 2g stage becomes an output "1", the AND gate 33 is opened, and the shift pulse is sent to the shift register 20.21.
is input to.

A comparison operation is then performed by the comparison circuit 22, and a signal "1" is output from either the X or Y terminal.

This signal causes the counter with the smaller number of counts among the counters 14 and 15 to be reset, while the AND gate corresponding to the reset counter among the AND gates 12 and 13 is opened.

When the seventh pulse is input to the ring counter 2, the pulse oscillator 5 is sent to the reset counter.
The third pulse train from is input.

Thereafter, the writing operation, comparison operation, and counting operation are repeated in the same way, and finally the one with the largest number of pulses among each pulse train remains on one of the counters 14 or 15, and the count value is displayed on the display device 16 or 17. Is displayed.

As described above, according to this embodiment, each pulse oscillator 3,
Among the pulse trains sent out from 4, 5, . . . , the one with the maximum number of pulses can be detected.

Therefore, if the oscillation frequency of each pulse oscillator is proportional to the light intensity incident on each charge conversion element, the maximum brightness of each part of the object can be detected, and vice versa. If you do this, you will be able to detect the lowest point.

FIG. 4 shows a configuration in which the first comparison operation of the comparator circuit is performed at the time when the second pulse train is input when the first pulse train and the second pulse train are sent out with a time lag as in the previous embodiment. An example circuit is shown.

In this circuit, the input of the AND gate 8 is taken from the 2C stage of the ring counter 2, and the second pulse train outputted from the AND gate 8 is inputted to the counter 15 via the OR gate 35. This is different from the example.

The counters 14, 15, write circuits 18, 19, etc. are the same as the circuits of the previous embodiment, and the entire circuit is shown in one block to avoid complexity.

In this embodiment circuit, when the first pulse is input to the ring counter 2, its 2b stage outputs "1", and the first pulse train from the pulse oscillator 3 is input to the counter 14.

When the second pulse is input to the ring counter 2, its 2C stage outputs "1", and the second pulse from the pulse oscillator 4 becomes "1".
A pulse train is input to counter 15.

When the third pulse is input to the ring counter 2, its 2d stage outputs "1" and writing is performed, and the fourth
At the th pulse, the output of stage 2e becomes "1" and a comparison operation is performed.

Then, the third pulse train is input to the reset counter, and the writing operation, comparison operation, and counting operation are repeated in the same manner.

In this embodiment, although the first pulse train and the second pulse train are sent out with a time lag, the first comparison operation is performed when the second pulse train is input to one of the two counters. Of each pulse train, it is possible to leave the one with the largest number of pulses or the one with the smallest number of pulses.

In order to retain the one with the minimum number of pulses, the X and Y terminals of the comparator circuit 22 may be interchanged.

In this way, the counter with the larger number of counts among the counters 14 and 15 is reset, and finally the one with the smallest number of pulses among each pulse train can be left.

In order to simultaneously send out the first pulse train and the second pulse train, in the embodiment circuit shown in FIG. Circuit 1 writes the output of stage...
8. 19, the outputs of stages 2d, 2g, . . . are connected to the AND gate 33, and the outputs of stages 2e, 2h, . . . are connected to the AND gate 9, .

With this configuration, the first pulse train is input into one counter and the second pulse train is input into the other counter at the same time, so it is possible to leave out the one with the maximum number of pulses or the one with the minimum number of pulses among each pulse train. .

In the above embodiment, either the highest or lowest luminance of each part of the object can be detected.If you want to detect both at the same time, for example, in FIG. It is sufficient that the pulse train with the maximum number of pulses is detected on the one hand, and the pulse train with the minimum number of pulses on the other hand is detected.

Although the embodiments of the present invention have been described above, there is no problem in making various changes as long as they do not make the implementation impossible.

For example, instead of using a ring counter for sequence control, multiple timers may be used, or one pulse oscillator 3, 4, 5, etc. may be used instead of multiple ones, and each photoelectric conversion element 6 and 1 The configuration may be such that the pulse oscillators are switched by a multiplexer or the like.

Also, other circuits can be used as comparison circuits.

Furthermore, each pulse oscillator 3, 4. The oscillation frequency of No. 5 may be determined corresponding to the logarithm of the light intensity incident on each charge conversion element.

This invention digitally detects the maximum and minimum of each partial brightness by providing a pulse generator that generates a plurality of pulse trains corresponding to the brightness of each part of the object, two counters, and a comparison circuit. is possible.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a field brightness detection device according to an embodiment of the present invention, FIG. 2 is a diagram showing photoelectric conversion elements arranged to receive light from each part of the field, and FIG. The figure shows an example of a comparison circuit, and FIG. 4 is a circuit diagram of another embodiment of the present invention. 1... Clock pulse oscillator, 2... Ring counter, 3, 4. 5... pulse oscillator, 14,
15...Counter, 22...Comparison circuit.

Claims (1)

[Scope of utility model registration request] a pulse generator that generates a plurality of pulse trains with a pulse frequency that is proportional or inversely proportional to the luminance of each part of the object field; and two counters that separately count two pulse trains selected from the plurality of pulse trains; A comparison circuit that compares the counts of these two counters, a circuit that resets the counter with the smaller number of counts using the output of this comparison circuit, and a gate that opens in response to the output thereof;
A gate circuit that inputs one pulse train newly selected from the plurality of pulse trains into the reset counter, sequentially selecting pulse trains, counting the counter, comparing the number of pulses, resetting one counter, and gate circuit. A sequence circuit to repeatedly open the circuit, and the above 2 to display according to the count number of the counter.
and a digital display device provided for each of the two counters, and the display device displays the maximum brightness of each part of the scene according to the count finally stored in either of the two counters. Or a field brightness detection device configured to digitally detect the lowest brightness.