JPH05122198A - Error rate alarm circuit with hysteresis - Google Patents

Abstract

PURPOSE:To apply a hysteresis without fail even when a time taken for deteriorating an error is short in the error rate alarm circuit with hysteresis. CONSTITUTION:Each output of clocks A6 and B7 is inputted to a selector 3, and a clock to be outputted to an error rate alarm circuit 2 by a selector 3 is changed according to the output of an alarm circuit (set/reset flipflop 4), thereby changing the alarm starting point of the error rate alarm circuit 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error rate alarm circuit with hysteresis, and more particularly to an error rate alarm circuit with hysteresis for digital data transmission.

[0002]

2. Description of the Related Art An example of a conventional error rate alarm circuit will be described with reference to FIGS. This FIG. 2 shows a basic error rate alarm circuit. In FIG. 2, 11 is an error rate alarm circuit, 12 is an error pulse, 13 is each input of a clock, 14 is an alarm output, and 15 is an inverted alarm output. The error rate alarm circuit 11 shown in FIG. 2 inputs one set of error pulses 12 and clocks 13, counts how many error pulses are input for each clock cycle, and sets the counting result to a preset setting. When the value is equal to or more than the value, a logic "1" is output to the alarm output 14, and a logic "0" is output to the reverse alarm output 15. Conversely, if it is smaller than the set value, alarm output 1
The logic "0" is output to 4 and the logic "1" is output to the reverse alarm output 15. For example, in the case where the setting value is 1 and the clock input is a clock with a power of 10 bit cycle of a signal sequence for monitoring an error, if one or more error pulses are input within the clock with a power of 10 6 bit cycle, that is, Is 10 −6 or more, the alarm output 14 becomes the logic “1” and the inverted alarm output 15 becomes the logic “0”.

FIG. 3 shows an example of an error rate warning circuit with hysteresis using two sets of error rate warning circuits and one set-reset flip-flop. In FIG. 3, 21,2
Reference numeral 2 is an error rate warning circuit, and 23 is a set / reset flip-flop which is set by the output of the error rate warning circuit 21 and reset by the output of the error rate warning circuit 22. Reference numeral 24 indicates an error pulse, 25 indicates a clock A, 26 indicates a clock B input, and 27 indicates an alarm output.

Next, the operation will be described. First, the error rate alarm circuit 21 inputs the error pulse 24 and the clock A25, counts the number of error pulses in the cycle of the clock A25, and sets the logic "1" when the number is equal to or more than a preset set value. It outputs to the set terminal (S) of the reset flip-flop 23. The error rate warning circuit 22 inputs the error pulse 24 and the clock B26 and inputs this clock B2.
When the number of error pulses in the period of 6 is counted and the number is smaller than a preset value, a logic "1" is output to the reset terminal (R) of the set / reset flip-flop 23. Then, the set / reset flip-flop 23 is
When the set input is "1" and the reset input is "0", a logic "1" is output to the alarm output 27, and when the set input is "0" and the reset input is "1", the alarm output 27 is output.
The logic "0" is output to, and when both the set input and the reset input are "1" or "0", the previous output is held.

Next, assuming that the set values of the error rate warning circuits 21 and 22 are 1, and the clock A25 has a 10 6 bit period and the clock B 26 has a 10 7 bit period,
The error rate alarm circuit 21 outputs a logic "1" when the error rate is 10 -6 or more, and outputs a logic "0" when the error rate is less than 10 -6. Similarly, the error rate alarm circuit 22 outputs a logic "0" when the error rate becomes 10 -7 or higher, and 1
If it is less than 0 -7, a logic "1" is output.

The set-reset flip-flop 23 is "0" when the error rate is less than 10 -7 to the set terminal (S) and the reset terminal (R), respectively.
Since "1" is input, "0" and "0" are input when the value is 10 -7 or more and less than 10 -6, and "1" and "0" are input when 10 -6 or more. If it is less than 10 −7, the alarm output 27 is set to logic “0”, and if it is 10 −6 or more, it is set to logic “1”. Also, 10 −7 or more 1
If the error rate changes from 10 −8 to 10 −5, the alarm output 27 is logically output when the error rate changes from 10 −8 to 10 −5. "0"
Then, if it is 10 −6 or more, it is set to logic “1”. vice versa,
When changing from 10 −5 to 10 −8, 1
At 0-7 or more, the alarm output 27 is set to logic "1", and 1
A logic "0" can be obtained when the power is less than 0 to the power of -7, and a hysteresis corresponding to an error rate of one digit can be provided.

[0007]

In this conventional error rate warning circuit with hysteresis, the output of the error rate warning circuit 21 is the clock because the cycle of each input of the clock A25 and the clock B26 is changed in order to have hysteresis. A
Although it changes in the cycle of 25, the output of the error rate warning circuit 22 changes only in the cycle of the clock B26. Therefore,
If the error rate in the previous example is 10 −8 or less, it becomes 10 −5 only during one cycle of the clock A25, and this time becomes 5 × (10 −7), then 10 −. When the power is 8 or less, the output of the error rate warning circuits 21 and 22 is "0",
When it is "1", the alarm output 27 is logic "0", and -10 of 10
When the power is raised, the output of the error rate warning circuit 21 is "1", and the output of the error rate warning circuit 22 does not change immediately, so it is "1".
And the alarm output 27 is logic “0”, and 5 ×
Since the output of the error rate warning circuit 21 becomes "0" when it becomes (10 -7), the warning output 27 remains the logic "0", and there is a problem that hysteresis is not applied.

[0008]

An error rate alarm circuit with hysteresis according to the present invention is an error rate alarm circuit for digital transmission, in which an error pulse and a first clock are input,
A first error rate warning circuit that compares the number of error pulses in the period of the first clock with a preset value and changes the output according to the comparison result, the first clock, and the first clock. A second clock different from the above-mentioned clock and an alarm output, and a selector for selecting and outputting either the first clock or the second clock in response to the alarm output; Input the same error pulse and the output clock of the above selector, compare the number of error pulses during synchronization of this output clock with a preset value,
The alarm output is set by the output of the second error rate alarm circuit that changes the output according to the comparison result and the output of the first error rate alarm circuit, and this alarm output is output by the output of the second error rate alarm circuit. And an alarm output means for resetting.

[0009]

In the present invention, means for selecting the cycle of the input clock of the second error rate warning circuit is provided, and the level at which the second error rate warning circuit outputs a warning is changed.

[0010]

1 is a block diagram showing an embodiment of an error rate alarm circuit with hysteresis according to the present invention. This Figure 1
In 1, an error rate alarm circuit for inputting the error pulse 5 and the clock A6, comparing the number of error pulses in the cycle of the clock A6 with a preset value, and changing the output according to the comparison result, 3 inputs a clock A6, a clock B7 different from the clock A6 and an alarm output,
The selector 2 which selects and outputs either the clock A6 or the clock B7 in response to this alarm output, 2 inputs the same error pulse as the error pulse 5 and the output clock of the selector 3, and synchronizes this output clock. The error rate warning circuit 4 that compares the number of error pulses in the circuit with a preset value and changes the output according to the comparison result is set by the output of the error rate warning circuit 1, and the output of the error rate warning circuit 2 An alarm output means for resetting the alarm output 8 by the output of the error rate alarm circuit 1 and resetting the alarm output 8 by the output of the error rate alarm circuit 1. Is composed of.

Next, the operation of the embodiment shown in FIG. 1 will be described. First, the error rate alarm circuit 1 inputs the error pulse 5 and the clock A6, respectively, counts the error pulses in the cycle of the clock A6, and when the number is equal to or more than a preset set value, sets the logic "1". When it becomes smaller than the set value, a logic "0" is outputted to the set terminal (S) of the set / reset flip-flop 4. The selector 3 inputs the clock A6, the clock B7, and the alarm output 8, and outputs the clock A6 when the alarm output 8 is logic "0" and outputs the clock B7 when the logic output is "1".

Next, the error rate warning circuit 2 inputs the error pulse 5 and the output clock of the selector 3 and counts the number of error pulses in the cycle of this output clock and if the value is smaller than a preset value, the logic "1" is given. Is output to the reset terminal (R) of the set / reset flip-flop 4.

Now, the set value of the error rate warning circuits 1 and 2 is set to 1
And clock A6 is 10 6 bit period, clock B
Assuming that 7 is a 10 7 bit period, the error rate warning circuit 1
Outputs a logic "1" when the error rate is 10 -6 or more, and outputs a logic "0" when the error rate is less than 10 -6. Then, the selector 3 outputs the clock A6 having a cycle of 10 6 bits.
While selecting, the error rate warning circuit 2 has an error rate of 10
When it is more than the −6th power of, a logical “1” is output and 10−6
If it is less than the power of two, a logic "0" is output. This selector 3 is 1
While selecting the clock B7 having a bit cycle of 0 to the 7th power, the error rate warning circuit 2 outputs a logic "1" when the error rate is 10 -7 or more, and a logic "1" when the error rate is less than 10 -7. 0 ”
Is output.

Next, if the error rate is 10 −5 power or less from a state of 10 −8 power or less to one cycle of the clock A6, and this time becomes 5 × (10 −7 power), it becomes 10 power. −
Set reset flip-flop 4 when the power is 8 or less
The set and reset inputs become logic "0" and "1",
The alarm output 8 becomes logic "0". When the alarm output 8 has a logic "0", the selector 3 selects the clock A6 and outputs it to the error rate alarm circuit 2.

Next, 1 is set only during one cycle of the clock A6.
When it becomes 5 × (10 −7 power) after becoming 0 −5 power, the outputs of the error rate warning circuits 1 and 2 are logic “1”, “0”.
Becomes Therefore, the alarm output 8 becomes logic "1",
The selector 3 selects the clock B7 to select the error rate warning circuit 2
The output of the error rate warning circuit 1 becomes a logic “0” when it becomes 5 × (10 −7), but the output of the error rate warning circuit 2 remains a logic “0”. The alarm output 8 holds logic "1". And the error rate is 10 again.
When the power falls below the 7th power, the outputs of the error rate warning circuits 1 and 2 become logic "0" and "1", and the warning output 8 becomes logic "0".

As described above, when the error rate changes, the alarm output 8 is output in the order of "0" → "1" → "1" → "0", so that hysteresis can be provided.

[0017]

As described above, according to the present invention, the level at which the second error rate warning circuit outputs an alarm is changed by providing means for selecting the cycle of the input clock of the second error rate warning circuit. By doing so, there is an effect that the hysteresis operation can be performed even when the time for which the error rate changes is short.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an error rate warning circuit with hysteresis according to the present invention.

FIG. 2 is a block diagram showing a basic error rate warning circuit.

FIG. 3 is a block diagram showing an example of a conventional error rate warning circuit with hysteresis.

[Explanation of symbols]

 1, 2 Error rate alarm circuit 3 Selector 4 Set reset flip-flop 5 Error pulse 6 Clock A 7 Clock B 8 Alarm output

Claims (1)

[Claims] 1. An error rate warning circuit for digital transmission, wherein an error pulse and a first clock are input, the number of error pulses in the period of the first clock is compared with a preset value, and the comparison result is obtained. A first error rate warning circuit for changing the output in response to the first clock, the first clock and the first clock
A second clock different from the above clock and an alarm output, and a selector which selects and outputs one of the first clock and the second clock corresponding to the alarm output,
An error pulse that is the same as the error pulse and the output clock of the selector are input, the number of error pulses during synchronization of this output clock is compared with a preset value, and the output is changed according to the comparison result. A second error rate warning circuit and a warning output means for setting a warning output with the output of the first error rate warning circuit and resetting the warning output with the output of the second error rate warning circuit. Characteristic error rate alarm circuit with hysteresis.