JPH0540645A - Parity counter circuit - Google Patents

Abstract

PURPOSE:To reduce the scale of a parity counter circuit by simplifying the constitution of this circuit. CONSTITUTION:When an initial setting signal 105 is kept at logic '0' in a single cycle of a clock 101, the output of a buffer 2 is set at a high impedance. As a result, a signal 106 supplied to one of both input terminals of an exclusive OR circuit 3 is always equal to logic '0' by the function of a resistance 4. Therefore the output signal. 102 of the circuit 3 is decided by a data signal. 107 only and never receives the influence of the counting result obtained in 8 parity counting section preceding by a stage. In other words, a counter 1 is initialized when the signal 105 is set at logic '0'. At the same time, a parity counting operation is started again. As a result, the counter 1 can be initialized without using a conventional complicated circuit that produces a signal to reset a flip-flop 1 even though the parity counting sections are continuous.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parity counting circuit used for digital communication.

[0002]

2. Description of the Related Art An example of a conventional parity counting circuit is shown in FIG. This parity counting circuit functions as a counter D
It is composed of a flip-flop 11 of a type, an exclusive OR circuit 3 functioning as a comparator, and an initial setting signal conversion circuit 12. The data signal 107 (see FIG. 4) is input to one input terminal of the OR circuit 3, and the OR circuit 3 compares the data signal 107 and the inverted output signal 104 of the flip-flop 11, and they are coincident with each other. In that case, a logic "0" signal is output, and if they do not match, a logic "1" signal is output. Then, the flip-flop 11 takes in the output signal 102 of the OR circuit in synchronization with the rising edge of the clock 101. As a result, the number of signals whose value included in the data signal 107 is logic “1” or logic “0”, that is, the parity count result is
The signal 103 is output from the flip-flop 11. The clock 101 is a clock with which the data signal 107 is synchronized, and the value of the data signal 107 changes in synchronization with the falling edge of this clock.

Since such parity counting is performed for each predetermined number of signals (that is, the number of bits), the initial setting signal 105 which becomes logical "0" is input every predetermined number of clocks. The initial setting signal conversion circuit 12 generates and outputs the initial setting signal 201 by this signal, and resets the flip-flop 11. That is, the flip-flop 11 is reset every time the initial setting signal 105 becomes logic "0", and the parity counting circuit newly starts the parity counting.

[0004]

However, in such a conventional parity counting circuit, when the initial setting signal 105 becomes low level in the case where the counting period is continuous, the flip-flop is activated by the next rising edge of the clock 101. Since 11 must be reset, the initial setting signal conversion circuit 12 generates a narrow pulse as the initial setting signal 201 at a very limited timing, as shown in FIG.
It must be given to the flip-flop 11. As a result, the initial setting signal conversion circuit 12 has to perform complicated control, and has a complicated structure and a large scale.

An object of the present invention is to eliminate such drawbacks and provide a parity counting circuit having a simple circuit configuration and a small scale.

[0006]

According to the present invention, the number of signals having a value of logic "1" or signals having a value of logic "0" contained in the first data signal sequence is counted at regular intervals. In the parity counting circuit, a second data signal sequence and a clock with which the data signal sequence is synchronized are input, and the value contained in the second data signal sequence is logical "1" or "0". A counter that counts the number of signals and outputs a signal indicating the counting result and an inverted signal thereof, and a signal having a predetermined logical value or the inverted signal output by the counter is based on the initial setting signal. A selector that selects and outputs the selected signal and the output signal of the selector and the first data signal sequence, and outputs a signal representing the comparison result to the counter as the second data signal sequence. And a comparator.

[0007]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 shows an example of a parity counting circuit according to the present invention. This parity counting circuit includes a D-type flip-flop 1 that functions as a counter, an exclusive OR circuit 3 that functions as a comparator, a tristate buffer 2 and a resistor 4 that function as a selector. Then, the data signal 107 (see FIG. 2)
Is input to one input terminal of the OR circuit 3, and the OR circuit 3
The output terminal of is connected to the data input terminal D of the flip-flop 1. The clock input terminal C of the flip-flop 1 has a clock 10 to which the data signal 107 is synchronized.
1 is input and the non-inverting output terminal Q of the flip-flop 1
Outputs a signal 103 representing the parity counting result.
The inverting output terminal Q (bar) is connected to the input terminal of the buffer 2. The output terminal of the buffer 2 is an OR circuit 3
Is connected to the other input terminal, and a resistor 4 is connected between the output terminal of the buffer 2 and the ground. The initial setting signal 105 is input to the output control terminal of the buffer 2.

Next, the operation will be described. Initial setting signal 105
, The output of the buffer 2 is active, and the signal 104 from the inverting output terminal of the flip-flop 1 is supplied to one input terminal of the exclusive OR circuit 3 through the buffer 2. Therefore, in this case, the circuit configuration is equivalent to that of the conventional parity counting circuit shown in FIG. 3, and the parity counting is performed by the conventional operation.

Next, when the initial setting signal 105 becomes logic "0" for one cycle of the clock 101 as shown in FIG. 2, the output of the buffer 2 becomes high impedance. As a result, the signal 106 supplied to one input terminal of the exclusive OR circuit 3 by the action of the resistor 4 is always logic "0". Therefore, in this case, the output signal 102 of the OR circuit 3 is determined only by the data signal 107,
It is not affected by the counting result in the preceding parity counting section. That is, when the initial setting signal 105 becomes a logic "0" for one clock cycle, the counter 1 is initialized and a new parity counting is started at the same time.

As described above, the parity counting circuit of this embodiment does not require the initial setting signal conversion circuit 12, and the initial setting can be performed with a simple circuit configuration. Since the initial setting signal 105 is a signal that becomes a logical “0” for one cycle of the clock 101 for each predetermined number of clocks 101, it can be easily generated by a simple circuit.

[0011]

As described above, in the parity counting circuit according to the present invention, the selector selects either the inverted output of the counter or the signal of the predetermined logical value based on the initial setting signal and outputs it to the comparator. Therefore, when the initial setting signal is input, the comparison result by the comparator can be made independent of the previous parity counting result, and as a result, a new parity counting is started at the same time as the initial setting. It becomes possible. Therefore, in the parity counting circuit of the present invention, even when the counting section is continuous, the conventional initialization conversion circuit is not necessary, and the circuit is simple and small.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a parity counting circuit according to the present invention.

FIG. 2 is a waveform diagram showing waveforms of respective parts of the parity counting circuit of FIG.

FIG. 3 is a block diagram showing an example of a conventional parity counting circuit.

FIG. 4 is a waveform diagram showing waveforms of respective parts of the parity counting circuit of FIG.

[Explanation of symbols]

 1 D-type flip-flop 2 Tri-state buffer 3 Exclusive OR circuit 4 Resistor

Claims (1)

[Claims] 1. A parity counting circuit for counting the number of signals having a logic "1" or a signal having a logic "0" included in a first data signal sequence at regular intervals, A data signal sequence and a clock with which the data signal sequence is synchronized are input, and the number of signals having a value of logic "1" or "0" contained in the second data signal sequence is counted and counted. A counter that outputs a signal indicating the result and its inverted signal, and select either a signal of a predetermined logical value or the inverted signal output by the counter based on the initial setting signal,
A selector for outputting and a comparator for comparing the output signal of the selector with the first data signal sequence and outputting a signal representing the comparison result as the second data signal sequence to the counter. A parity counting circuit characterized by being provided.