JPH05175829A - Method and device for data input/output - Google Patents

Abstract

PURPOSE:To provide the method and the device for input and output which can read and write data at a high speed. CONSTITUTION:The high-speed operation is possible if a counter 1 is used where D flip flops are inserted to the series carry line of AND gates of synchronous counters at intervals of m bits, but a value which cannot be unequivocally determined is generated in the counter 1, therefore, arbitrary one of values larger than n-1 belonging to an OK set is set as the initial value of the counter 1 when the value collected for every m bits is denoted as (n), thereby using all addresses of a memory 2 corresponding to all bits and performing the high- speed operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data input / output method and device for reading / writing data from / to a memory, and more particularly to a technique enabling high-speed reading / writing.

[0002]

2. Description of the Related Art Generally, when reading or writing data to or from a memory, a clock signal is counted by a counter (counter), and an address corresponding to the counted value is designated in the memory to read or write the data. To do. The counter used in the above input / output device will be described below.

FIG. 8 is an example of a conventional general asynchronous counter, showing a 4-bit binary counter using a JK flip-flop. In FIG. 8, FF _{0 to} F
F ₃ is a JK flip-flop, CLK is an input pulse signal (clock pulse) to be counted, and b _{0 to} b ₃ are outputs of respective bits.

FIG. 10 is an example of a conventional general synchronous counter, showing a 4-bit binary counter using a JK flip-flop and an AND gate. Figure 10
In FIG. 8, A _{0 to} A ₃ respectively represent AND gates, and other parts have the same reference numerals as those in FIG. In the circuit of FIG. 10, the J _i and K _i inputs of each bit are determined as follows by the output from the preceding JK flip-flop and the input of the least significant bit. J ₀ = K ₀ = 1 J ₁ = K ₁ = b ₀ J ₂ = K ₂ = b ₁ b ₀ J ₃ = K ₃ = b ₂ b ₁ b ₀

[0005]

However, in the conventional counter as described above, the general terms J _n and K _{n of the} input for determining the value of the nth bit are J _n = K _n = b _n-1. Since b _n-2 ...... b ₂ b ₁ b ₀ , there is a problem that if the number of digits of the counter increases, it takes time for the intermediate result to propagate and the operating frequency cannot be increased. It was Hereinafter, the above-mentioned problems regarding the asynchronous type and the synchronous type will be described in detail.

Problems in Asynchronous Counter In the circuit of FIG. 8, the J input and the K input of each JK flip-flop are both set to 1, and the input to be counted to the clock input terminal of the lowest JK flip-flop FF _0. (C
LK), and thereafter, the outputs of the respective JK flip-flops are input to the clock input terminals of the JK flip-flops one stage higher. In the above configuration, each J
Since the K flip-flop has a delay until the operation is completed, when the frequency of the input signal to be counted becomes relatively high with respect to the above delay, the count value is delayed and the output binary number is delayed. There is a problem that the value becomes smaller than the actual count value. For example, FIG. 9 is a timing chart of the asynchronous counter. FIG. 9 illustrates the case where the delay τ of each JK flip-flop is equal to the half wavelength of the clock pulse CLK. In this case, (A) a point is a point that contains the fifth pulse, therefore the count value _{"b 3 b 2 b 1 b} 0" must be "0100" (decimal 4). However, as can be seen from the figure, the actual delay is "0010" (2 in decimal) or "0000" (0 in decimal). Therefore, when using the asynchronous counter, the frequency of the clock pulse must be sufficiently low with respect to the delay of the continuous JK flip-flops.

A second problem is that the delay τ of each JK flip-flop is not all equal, which causes a problem of non-synchronization. That is, when operating the entire system including this counter in synchronization with a specific clock, the asynchronous counter has delays of all flip-flops that have non-uniform delays when the value is determined. Since the value is defined by the sum, if the value is referred to synchronously, the value becomes uncertain. For example, at the point (A) in FIG. 9, the value is “001
0 "or become" 0000 becomes "of differences from occurring is due to the second JK flip-flop or the operating speed of the FF ₁ is slightly faster or slower. Similar to the above phenomenon, illustrated As described above, it also occurs at the time when the 8th and 9th pulses are input.

Problems with Synchronous Counter In the circuit of FIG. 10, the output of each JK flip-flop is connected to the input of the JK flip-flop of the next bit through one AND gate, and each AN is connected.
The output of the D gate is connected to one input of the AND gate of the next bit to form a serial carry line of the AND gate. FIG. 11 is a timing chart of the synchronous counter. In FIG. 11, the input clock pulse has a pulse width nsec of 2 and a period of 6 nsec, each AND gate has a delay of 1 nsec, and each JK flip-flop has a delay of 3 nsec. That is, the delay of 1 nsec at the point (A) is caused by the operation delay in the AND gate A ₀ of FIG. Similarly, the delay at point (B) is AN
The transition delayed by the D gate A ₀ is further delayed by ₁ nsec by the AND gate A ₁ , and the input signal of the JK flip-flop FF ₂ is delayed by a total of 2 nsec. After the transition from "0" to "1" at the point (B), the JK flip-flop FF ₂ operates corresponding to the falling edge of the clock pulse 1 nsec later, and the JK flip-flop is operated as shown at the point (C). The output of the JK flip-flop FF ₂ transits from “0” to “1” after the delay of 3 nsec which the loop has. A series of operations similar to the above series of operations is shown in (D), (E), and (F) of FIG. The delay at point (F) is AN in the circuit of FIG.
Corresponding to the delay of the D gate A _2, the total delay of the input of the JK flip-flop FF ₃ is increased by 1 nsec to 3 nsec.
It has become. Therefore, the input signal to the JK flip-flop FF ₃ transits from “0” to “1” at the time when the clock pulse falls, and when the clock pulse falls, it is stable “1”. Don't
Therefore, the normal transition of the JK flip-flop FF ₃ cannot be expected, and as shown by the dotted line in (G), the fall of the clock happens to be delayed, or the AND gates A ₀ , A ₁ and A ₂ happen to be slightly delayed. JK flip-flop F becomes smaller or
The output of F ₃ will be or remain "1" or a, or "0". The above-mentioned unstable phenomenon occurs because the sum of delays in the AND gates A ₀ , A ₁ , and A ₂ becomes relatively large with respect to the cycle of the clock pulse. In the example, each A
The sum of the delays of the ND gates is 1 / the cycle of the clock pulse.
When it reaches 2, accurate counting becomes impossible. Therefore, from the relationship between the delay characteristic and the clock pulse period as shown in the time chart of FIG. 11, it can be understood that only a counter having up to 3 bits can be configured. As described above, in the conventional counter, when the number of digits becomes large, it is difficult to realize a high-speed counter in which the frequency of the clock pulse is increased, and therefore it is difficult to read and write data from the memory at high speed. There was a problem that there was.

The present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide an input / output method and apparatus capable of high-speed reading / writing of data.

[0010]

In order to achieve the above object, the present invention is constructed as described in the claims. That is, in the data input / output method according to the first aspect, as a counter for designating the address of the memory, there are provided flip-flops of a number corresponding to the number of bits and AND gates of the same number, and each flip-flop is The output of each AND gate is connected to the input of the flip-flop of the next bit through one AND gate, and the output of each AND gate is connected to one input of the AND gate of the next bit to connect the serial carry line of the AND gate. In the serial carry line of the AND gate in the synchronous counter being formed, D (m is a positive integer) every D bits
Uses a synchronous counter that has a configuration in which flip-flops are inserted in series and that outputs a normal count value at a plurality of predetermined values, and compensates for the part of the counter that does not output a normal value. Therefore, the address of the memory is specified by the procedure as described in (1) to (5) of claim 1. In addition, "↑ (m + n)" in "2 ↑ (m + n) -1" described in claim 1 indicates 2 to the power of (m + n). That is, 2 ↑ (m + n) −1 has the content shown in the following (Equation 1). Similarly, in the same manner, the sign of ↑ () indicates a power in parentheses. However, when used as a subscript, 2 ↑ (m + n)
-1 is displayed as X.

[0011]

[Equation 1]

Further, in the input / output device of claim 2,
A structure for realizing the method according to claim 1, that is, a memory, the above-mentioned special synchronous counter, an initial value setting means, and a control means are provided. The initial value setting means and the control means described above can be configured by, for example, the functions of a computer (for example, the central processing unit 3 in FIG. 1 described later).

[0013]

As described above, in the present invention, the special high-speed counter as described above is used as the counter for designating the address of the memory. In the above-mentioned synchronous counter, by inserting the D flip-flop every m bits in the serial carry line of the AND gate, the propagation distance of the intermediate result can be shortened, so that the high-speed counter with a high operating frequency is provided. Can be realized. In other words, if the above-mentioned part for each m bits is named a stage, and a D flip-flop is inserted for each stage,
The carry length of the AND gate existing between the D flip-flops is at most m gates. That is, D for each stage
Since a flip-flop is inserted so that the delay in each AND gate becomes 0 at that point, even if the total number of AND gates on the serial carry line is large, the delay that affects the operation is different. Only the delay within the stage can be suppressed. Therefore, when the number of bits in the stage is m, no matter how large the total number of bits is, the delay affecting the operation is the delay of m AND gates, so that the cycle of the clock pulse is made faster. You can

However, with the above configuration, the D flip-flop may be inserted on the serial carry line to cause a count value different from the true value. For example, in the case of m = 2 and n = 2, that is, in the case of a 4-bit counter consisting of two stages that are grouped every 2 bits,
0, 1, 2, 3, 5, 6, 7, 9, 10, 11, 13,
It is possible to accurately count 14 and 15, but
The count values of 4, 8, and 12 are different from the normal values. Therefore, when the counter as described above is used in the data input / output device, it is necessary to use a special address designating method. That is, when a predetermined value that is a normal count value is an OK value and the number of stages divided by the D flip-flop is n, a memory numbered from 0 to a maximum _X is used and written in the memory. Alternatively, when the series of data to be read is D ₀ , D ₁ , D ₂ , ..., D _i , ..., D _X , first, an arbitrary OK value of n−1 or more (in the above example, 2, 3 5, 6, 7, 9, 10, 11, 13,
14, 15) and sets or resets each flip-flop of the synchronous counter to set the initial value of the synchronous counter to the selected OK value. Further, all the D flip-flops of the synchronous counter are reset. The above-mentioned OK value may be selected in advance and the value may be initialized. Next, the first data D ₀ is written in the value of the synchronous counter, that is, the address indicated by the initial value.

Next, when the synchronous counter counts the input pulse signal and transitions from the current state to the next state, the next data is written in the address indicated by the count value of the synchronous counter. Then, the above operation is repeated until writing of all data, that is, up to D _X is completed. Also, in the case of data reading, the address of the memory is specified and the data of the address is read by the same procedure as above. For example, as in the synchronous counter shown in FIG. 2 described later, m = 2, n
In = 3 in case where the 5-bit counter, if you select 2 as the initial value of the above relation of the address to be written and the data D ₀ to D ₃₁ are as shown in FIG. As can be seen from FIG. 3, the third data D is at address 0.
₂ , the 16th data D ₁₅ is written in the 1st address and the 1st data D ₀ is written in the 2nd address, so that the order of the addresses and the data number written therein are different. If the same address is specified for writing and reading, no problem will occur.

In the present invention, as described above, a special high-speed counter whose count value is a value different from the normal value is used in part, and all the numbers that can be counted by the counter (for example, 16 bits for 4 bits) are used. ) To specify all the addresses corresponding to
Although the special address designation method as described above is used, if the address corresponding to a value different from the normal value is to be omitted,
The same address designation method as usual can be used. For example, in the case of the above 4-bit counter with m = 2 and n = 2, 0, 1, 2, 3, 5, 6, 7, 9, 10, 11, 1
Use only 13 addresses of 3, 14, 15 and 4, 8,
If the memory is not used for the three addresses 12 and the memory is not used, the first data D ₀ , 1 is assigned to the address 0 as usual.
The address may be designated as the second data D ₁ .

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Before explaining the data input / output device of the present invention, first, a special synchronous counter used in the present invention will be explained. FIG. 5 is a block diagram of an example of a synchronous counter invented by the present inventors.

In FIG. 5, FF _{0 to} FF ₃ are J, respectively.
K flip-flops, A _{0 to} A ₃ are AND gates, DF ₀ and DF ₁ are D flip-flops (Delay or Data flip-flops), CLK is an input pulse signal (clock pulse) to be counted, and b _{0 to} b ₃ are The output of each bit is shown. The circuit of FIG. 5 has AND gates A ₀ to
In a 4-bit synchronous counter composed of A ₃ and JK flip-flops FF _{0 to} FF ₃ , if the portions that are grouped every 2 bits are named stages, each stage on the serial carry line of the AND gate is In this configuration, a D flip-flop is inserted into the output that moves to the stage, and the output of the D flip-flop is used as the carry input of the next stage. In this case, if m = 2 and the number of stages is n, then n = 2 and the total number of bits is m × n = 4.

Next, the operation will be described. FIG. 6 is a timing chart of the circuit of FIG. In FIG. 6, the delay of each JK flip-flop in the circuit of FIG.
c, the delay of each AND gate is 1 nsec, the delay of each D flip-flop is 2 nsec, the cycle of the clock pulse CLK is 6 nsec, and the characteristics when counting is started from the state of resetting each JK flip-flop, The value is plotted on the vertical axis and the time on the horizontal axis. Further, each element in FIG. 5 is activated at the falling edge of the clock pulse, and the values of the respective JK flip-flops FF _{0 to} FF ₃ at this time are count values. In this embodiment, since the D flip-flops are inserted every 2 bits, the carry length of the AND gates existing between the D flip-flops is at most 2 gates. That is, a D flip-flop is inserted for each stage, and each AND
Since the delay in the gate is set to 0 at that point, even if the total number of AND gates on the series carry line is large, the delay that affects the operation is suppressed only to the delay in each stage. Therefore, when the number of bits m in the stage is 2, as in the example of FIG. 5, the delay that affects the operation is a delay of two AND gates, no matter how large the total number of bits is. The pulse cycle can be as high as 6 nsec as shown in the figure.

However, in the configuration of FIG. 5, the D flip-flop is inserted on the serial carry line, which causes the following problems in the count value. FIG. 7 is a table showing the correspondence between each bit output and the decimal number in the circuit of FIG. In FIG. 7, at the portion surrounded by the broken line, that is, at decimal points 4, 8, and 12, the value D of the D flip-flop
F is "1", and the count value is incorrect in this part. That is, the value that should originally be 4 = “0100” is “0000”, and 8 = “1000” is “0100”.
Therefore, 12 = “1100” becomes “1000”. As mentioned above, in this 4-bit counter,
0, 1, 2, 3, 5, 6, 7, 9, 10, 11, 13,
14 and 15 can be counted accurately, but 4, 8 and
12 cannot be counted. When the above-mentioned number that can be normally counted, that is, a set that can be counted is named an OK set, the OK set is generally represented by the following (Equation 1).

[0021]

[Equation 1]

However, in the above equation (1), V is a value represented by the following equation (2).

[0023]

[Equation 2]

The condition of V in the above OK corresponds to that all the values of the D flip-flops on the serial carry line are zero. As described above, in the counter as shown in FIG. 5, although the high speed operation is possible, the numbers other than the numbers belonging to the OK set cannot be normally counted. Therefore, when using such a counter as a counter for counting addresses in an input / output device, if the address corresponding to a value different from the normal value is to be omitted, use the same address designation method as usual. Can be done. For example,
In the case of the above 4-bit counter, 0, 1, 2, 3,
13 of 5, 6, 7, 9, 10, 11, 13, 14, 15
If only one address is used and three addresses 4, 8, and 12 are omitted and the memory is not used, 0 is used as usual.
The first data D ₀ may be designated as the address and the second data D ₁ may be designated as the address. In the circuit of FIG. 5, when the count value belongs to the OK set, the outputs of all the D flip-flops are “0”. Therefore, the output of each D flip-flop is passed through the NOT circuit (negative circuit). If it is connected to an AND gate, the output value of the AND gate being "1" indicates that the count value at that time belongs to the OK set. Therefore, in the case of the input / output method including the missing number as described above, the address may be designated by the count value only when the output of the AND gate is "1".

However, the above-mentioned input / output method is uneconomical because some addresses cannot be used in the memory. Therefore, it is the input / output method of the present invention that the special high-speed counter as described above is used and all the addresses of the memory can be effectively utilized. The details will be described below. FIG. 1 is a block diagram of an embodiment of a data input / output device of the present invention, showing an example in which the special high-speed counter as described above is used as a program counter of a microprogram which uses a count value as an address. In FIG.
1 is a special counter as described above, for example, a counter with m = 2 and n = 3 as shown in FIG. Further, 2 is a memory, 3 is a central processing unit (CPU), 4 is an address bus, and 5 is a data bus. Further, S ₁ and S ₂ are set signals for setting each flip-flop in the counter 1,
R ₁ and R ₂ are also reset signals (details will be described later). CLK is a clock signal and WR is a memory write signal. When the write signal WR is “1”,
The value on the data bus 5 is written at the address indicated by the value on the address bus 4. Further, each JK flip-flop of the counter 1 is directly connected to the address bus 4 of the memory 2, and the count value of each JK flip-flop specifies the address.

Next, FIG. 2 is a block diagram showing the details of the counter 1 described above. In FIG. 2, FF _{0 to} FF ₄ are J
K flip-flops, DF ₀ and DF ₁ are D flip-flops, A _{0 to} A ₃ are AND gates, and b _{0 to} b ₄ are outputs of each JK flip-flop. Each JK flip-flop FF
_{0 to} FF ₄ have a set terminal set and a reset terminal reset, and each D flip-flop DF ₀ , DF ₁ has a reset terminal reset. The set signal S ₁ output from the processing device 3
Is a JK flip-flop FF ₀ , FF ₂ , FF ₃ , FF ₄
And the reset signal R ₁ is applied to the reset terminals of the JK flip-flops FF ₀ , FF ₂ , FF ₃ and FF _{4 and} the reset terminals of the D flip-flops DF ₀ and DF ₁ . On the other hand, the set signal S ₂ is given to the set terminal of the JK flip-flop FF ₁ , and the reset signal R ₂ is given to the reset terminal of the JK flip-flop FF ₁ . The set function and the reset function in the above JK flip-flop and D flip-flop operate asynchronously, and the initial state of the counter can be asynchronously set to an arbitrary value. Note that FIG. 4 is a timing chart of signal waveforms in the circuit of FIG.

The operation will be described below. In order to specify the address of the memory 2 by the m × n bit counter 1, the memory numbered from 0 to 2 ↑ (m + n) −1 is used as the memory 2. If the series of data stored in this memory is D ₀ , D ₁ , D ₂ , ..., D _i , ..., D _X , writing of these data to the memory is performed by the following procedure. (1) Select an arbitrary OK value of n-1 or more, and use the counter 1
Each JK flip-flop is set or reset to set the initial value of the counter 1 to the selected OK value. Further, all the D flip-flops of the counter 1 are reset. (2) The first data D ₀ is written in the value of the counter 1, that is, the address indicated by the above initial value. (3) When the counter 1 counts the input pulse signal and transitions from the current state to the next state, the next data is written in the address indicated by the count value of the counter 1. (4) The above (3) is repeated until writing of all data, that is, up to D _X is completed. (5) In the case of data reading, the address of the memory is specified and the data of the address is read by the same procedure as above.

Next, as an example, as shown in FIG. 2, m =
2, with a counter of n = 3, 5 bits, ie D ₀ ,
A case where 32 pieces of data up to D ₁ , ..., D ₃₁ are written in the memory 2 will be described. In this example, 5
Since it is used as a bit, only one JK flip-flop is connected to FF _{4 in} the third stage in FIG. 2, but if two JK flip-flops are connected in the third stage, m × n = 2 × 3 = 6 bits, which can be used for up to 64 data. (1) Since n = 3 and n-1 = 2 and 2 is an OK value, this value is used as an initial value. In order to set this initial value, set signals and reset signals such as S ₁ , R ₁ , S ₂ , and R ₂ in the signal waveform of FIG. 4 are given. That is,
The set terminals of the JK flip-flops FF ₀ , FF ₂ , FF ₃ and FF ₄ are “0” (S ₁ ), the JK flip-flop F
The reset terminals of F ₀ , FF ₂ , FF ₃ , and FF _{4 and} the reset terminals of the D flip-flops DF ₀ and DF ₁ are “1”.
(R _1), JK to the set terminal of the flip-flop _{FF 1 "1" (S 2} ), the reset terminal JK flip-flop FF ₁ gives a "0" (R _2). As a result, the initial value of the counter 1 becomes "00010" (= 2). (2) The first data D ₀ is written to the address indicated by the count value of the counter 1, that is, the address 2. (3) When the counter 1 counts the clock signal CLK and transitions from the current state to the next state, the next data is counted by the counter 1
Write to the address indicated by the value of. (4) The above (3) is repeated until the data is exhausted, that is, until the 32nd data D ₃₁ is written. When the initial value is set to 2 and counting is performed, the series of count values of the JK flip-flop in the counter of FIG.
0, 5, 6, 7, 4, 9, 10, 11, 8, 13, 1
4, 15, 12, 1, 18, 19, 16, 21, 22,
23, 20, 25, 26, 27, 24, 29, 30, 3
It becomes 1, 28 and 17. Therefore, data is stored in the order of D ₀ , D ₁ , D ₂ , ..., D ₃₁ at the addresses shown in this sequence. FIG. 3 is a diagram showing the correspondence between the specified address and the data number to be input. Hereinafter, the reason why all the addresses of 5 bits and 32 bits can be specified by setting the initial value as described above will be described.
In the counter of FIG. 2, the number belonging to the OK set is 0,
1, 2, 3, 5, 6, 7, 9, 10, 11, 13, 1
4, 15, 18, 19, 21, 22, 23, 25, 2
There are 24 of 6, 27, 29, 30, 31 and the numbers that do not belong to the OK set are 4, 8, 12, 16, 17, 20, 2.
There are 8 of 4, 28. Of the 24 pieces of the above-mentioned OK set, the values of the remaining 22 pieces except 0 and 1 are uniquely determined, so that these values are used as the addresses as they are without causing any trouble. Also, of the eight that do not belong to the OK set,
For six of 8, 12, 16, 20, 24, 28,
The count value of 8 corresponds to 4 (that is, when the counter of FIG. 2 is 8, the count value of 4 becomes “00100”), and 1
2 to 8; 16 to 12; 20 to 16; 24 to 20
Therefore, 28 corresponds to 24, which is different from the true value, but is uniquely determined. Therefore, by changing the contents of the address according to the count value, it can be used without trouble. Can be done. For example, the value 8 has a count value of 4, so that the series of addresses is the third address, followed by the eighth address, and then the ninth, tenth, and eleventh addresses.
Just change the contents so that the address will come. However, 0 and 1 of the OK set and 4 and 1 that do not belong to the OK set
For 7, 0 and 4 are the same count value 0 (“0000
0 ") and 1 and 17 are the same count value 1 (" 0000
Therefore, in this embodiment, the initial value of the counter is set to 2 instead of 0, 4 corresponds to 0 address, and 17 corresponds to 1 address. By doing so, the sequence of count values of the JK flip-flop in the counter of FIG.
3, 0, 5, 6, 7, 4, 9, 10, 11, 8, 13,
14, 15, 12, 1, 18, 19, 16, 21, 2
2, 23, 20, 25, 26, 27, 24, 29, 3
It will orbit in the order of 0, 31, 28, 17. Therefore, if the addresses are specified in the above order, it becomes possible to uniquely specify all the addresses of the memory by using the special high-speed counter as shown in FIG. As described above, in the present embodiment, the first data D ₀ to address 2, so that the second data D ₁ to address 3, the third data D ₂ are written into address 0, address Although the order of is different from the order of the data number written therein, if the same address is designated at the time of writing and reading, no problem will occur. By using the procedures of (1) to (4), not only the counter of FIG. 2 but also other values of m and n and counters of other bit numbers, similar to the above,
It becomes possible to uniquely specify all addresses in the memory.

[0029]

As described above, according to the present invention, a special counter in which a D flip-flop is inserted every m bits is used in the serial carry line of the AND gate,
Further, by using the procedures such as the above (1) to (4), the excellent effect that the read / write speed of the data input / output device can be greatly improved can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a data input / output device of the present invention.

2 is a block diagram of an example of a synchronous counter used in the apparatus of FIG.

FIG. 3 is a chart showing a comparison between designated addresses and data numbers in the apparatus.

FIG. 4 is a timing chart showing operation waveforms in the circuit of FIG.

FIG. 5 is a block diagram of an example of a synchronous counter.

6 is a timing chart showing operation waveforms in the circuit of FIG.

FIG. 7 is a chart showing count values in the circuit of FIG.

FIG. 8 is a block diagram of an example of a conventional asynchronous counter.

9 is a timing chart showing signal waveforms in the circuit of FIG.

FIG. 10 is a block diagram of an example of a conventional synchronous counter.

11 is a timing chart showing signal waveforms in the circuit of FIG.

[Explanation of symbols]

1 ... synchronous counter 2 ... memory 3 ... central processing unit 4 ... address bus 5 ... data bus FF ₀ to ff ₄ ... JK flip-flop A ₀ to A ₃ ... the AND gate DF _0, DF ₁ ... D flip-flop CLK ... Input pulse signal (clock pulse) to be counted b _{0 to} b ₄ ... Output of each bit WR ... Write signal S ₁ ... FF ₀ , FF ₂ , FF ₃ , FF ₄ , DF ₀ and DF ₁
Set signal S ₂ ... FF ₁ set signal R ₁ ... FF ₀ , FF ₂ , FF ₃ , FF ₄ , DF ₀ and DF ₁
Reset signal R ₂ ... FF ₁ reset signal

Claims (2)

[Claims] 1. A data input / output method in which an input pulse signal is counted by a counter and data is input / output by designating an address corresponding to the counted value in a memory, wherein the counter corresponds to the number of bits. The number of flip-flops and the same number of AND gates, the output of each flip-flop is connected to the input of the flip-flop of the next bit via one AND gate, and the output of each AND gate is The serial carry line of the AND gate in the synchronous counter, which is connected to one input of the AND gate of the bit to form the serial carry line of the AND gate, has a D flip-flop every m (m is a positive integer) bits. Have a configuration in which
A synchronous counter that outputs a normal count value at a plurality of predetermined values determined in advance is used, and the predetermined value which becomes the normal count value is set as an OK value, and the D
When n is the number of stages divided by flip-flops, 0 to a maximum of 2 ↑ (m + n) -1 (hereinafter, this value is X
Is displayed), and a series of data written to or read from the memory is D ₀ ,
_{D 1, D 2, ...,} D i, ..., and D _X, the data output wherein the writing or reading of the memory of these data in the following order. (1) Select an arbitrary OK value of n-1 or more, set or reset each flip-flop of the synchronous counter, and set the initial value of the synchronous counter to the selected OK value. , And all the D flip-flops of the synchronous counter are reset. (2) The first data D ₀ is written in the value of the synchronous counter, that is, the address indicated by the initial value. (3) When the synchronous counter counts the input pulse signal and transitions from the current state to the next state, the next data is written in the address indicated by the count value of the synchronous counter. (4) The above (3) is repeated until writing of all data, that is, up to D _X is completed. (5) In the case of data reading, the address of the memory is specified and the data of the address is read by the same procedure as above. 2. A memory for storing data, a number of flip-flops corresponding to the number of bits, and the same number of AND gates, and the output of each flip-flop outputs the next bit through one AND gate. A serial carry of the AND gate in a synchronous counter which is connected to the input of a flip-flop and the output of each AND gate is connected to one input of the AND gate of the next bit to form a serial carry line of the AND gate. A synchronous counter having a configuration in which a D flip-flop is inserted in series for each m (m is a positive integer) bit, and which outputs a normal count value at a plurality of predetermined values; A predetermined value that is a normal count value is an OK value, and the above D
When the number of stages divided by the flip-flops is n, each flip-flop of the synchronous counter is set or reset so that the initial value of the synchronous counter is n-1 or more, which is a preselected one. Initial value setting means for setting one OK value and resetting all the D flip-flops of the synchronous counter, and the first data D ₀ is the value of the synchronous counter, that is, the address indicated by the initial value. When the synchronous counter counts the input pulse signal and transitions from the current state to the next state, the next data is written to the address indicated by the count value of the synchronous counter, and the above operation is performed. Repeated until the data is exhausted, and also in the case of data reading, the control means for specifying the memory address and reading the data at the address is provided. A data input / output device characterized by.