JP2018148338A - Clock synchronous serial data receiving circuit and bus system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock synchronous serial data receiving circuit which easily detects the transmission error and ignores the data when a clock signal is erroneously recognized due to the influence of noise.SOLUTION: A clock synchronous serial data receiving circuit 1 sets a value of serial data SD to output terminals QA to QH of a shift register 11 at a rising timing of a clock pulse of a serial clock signal SCK while the select signal SEL input with negative logic is at an L level, and when a counter 13 counts 8 pulses from the serial clock signal SCK, an output signal TP1 of a Q3 terminal becomes at an H level, and an output signal TP2 of an AND circuit 14 becomes at the H level only when a select signal SEL becomes at the H level while the TP1 is holding the H level, and 8-bit data input to a latch 12 from the shift register 11 is determined to be the output value of the output terminals Q0 to Q7.SELECTED DRAWING: Figure 2

Description

  The present invention has at least three signal inputs of a serial data signal, a serial clock signal, and a select signal, and captures the serial data signal at the change timing of the serial clock signal while the select signal is active, The present invention relates to a clock synchronous serial data receiving circuit that shifts each time 1-bit data is received and converts it into parallel data of a reference bit number, and a bus system that actively connects a plurality of clock synchronous serial data receiving circuits.

  A clock-synchronized serial data transfer system is widely used for data transfer between components in various computer systems and machine devices such as gaming machines or between boards. In this clock synchronous serial data transfer system, data is received bit by bit from serial data transmitted through a data signal line in accordance with a clock signal clock (for example, rise timing).

  In the clock synchronous serial data transfer system, the handling of data transmission errors that occur accidentally due to noise or the like is determined by the design policy of the entire system. In general, when a transmission error occurs, a process of notifying the other party that the transmission error has occurred and requesting retransmission is performed. However, in the case of a machine device that operates in a poor noise environment such as a gaming machine, a communication error often occurs. Therefore, if a retransmission request is made each time, it causes a decrease in throughput, and promptly. There is a possibility of hindering the progress of the game, which is not preferable.

  If data is transferred periodically at short intervals, even if there is an error in some received data, it does not request retransmission and simply ignores the erroneous data and does not receive it. The same effect as retransmission may be obtained simply by waiting for data. For example, in the gaming machine described in Patent Document 1, in order to repeatedly drive N × M lamps at a high speed, drawing data is transmitted from the effect control board to the lamp connection board in a short cycle of about 2 mS. If the drawing data is garbled, the drawing data is discarded and the lamp is not driven. As described above, even if the lamp driving based on the abnormal drawing data is discarded, there is no problem as a whole due to the relationship between human vision and the lamp lighting cycle.

JP 2009-279252 A

  However, in the invention described in Patent Document 1, it is normal that the basis for detecting the abnormality of the received data by the abnormality detection circuit is the content of the received data (only one bit of the common data COM1 to COM4 is 1, It is difficult to apply to a general-purpose clock synchronous serial data transfer circuit. That is, unless abnormality detection based on such a simple determination condition is possible, it is difficult to appropriately discard drawing data periodically transmitted in a short period of time.

  In general, the occurrence of bit corruption due to the influence of noise means that noise is added to the serial data signal at the rising edge or falling edge (hereinafter referred to as “edge”) of the clock signal, and is originally recognized as H level. Although it should be misrecognized as L level (or vice versa), noise is generally a voltage change in a very short time, so noise is present in the serial data signal at the timing of the edge of the clock signal. Riding is rare.

  On the other hand, when noise is added to the clock signal, even if the voltage changes for a short time, the electronic circuit recognizes it as an edge, so that a data abnormality occurs in which the bit position of the serial data is shifted. . In addition, any part of the clock signal is noisy and a data abnormality occurs, so the frequency of occurrence is higher.

  When such a bit position shift due to noise occurs, it cannot be detected by the abnormality detection circuit in the invention described in Patent Document 1, and the lamp effect is executed with the bit position shifted from the original position. There is a risk of executing a natural lamp effect.

  The present invention has been made in view of the above circumstances, and when a clock signal is erroneously recognized due to the influence of noise, a clock synchronous serial data receiving circuit that easily detects the transmission error and ignores the data, and An object of the present invention is to provide a bus system for actively connecting a plurality of clock synchronous serial data receiving circuits.

  In order to solve the above problem, the invention according to claim 1 has at least three signal inputs of a serial data signal, a serial clock signal, and a select signal, and while the select signal is active, In the clock synchronous serial data receiving circuit that takes in the serial data signal at the change timing of the serial clock signal and shifts it every time 1-bit data is received and converts it into parallel data of the reference bit number, the select signal becomes active A capture timing determination means for outputting a capture timing determination signal, and counting the number of serial clock signals detected while the count value is a natural number multiple of the reference bit number; The select signal is within a period during which the capture timing determination signal is output by the means. Only if it becomes inactive, characterized in that it comprises a reception data determination means for determining said parallel data as reception data.

  Further, in the invention according to claim 2, in the clock synchronous serial data receiving circuit according to claim 1, it is possible to output a serial data signal for the next stage obtained by shifting the serial data signal by a reference bit number. It is characterized by.

  According to a third aspect of the present invention, at least the serial data signal, the serial clock signal, and the select signal are supplied from a master side device, and the clock synchronous serial data receiving circuit according to the second aspect is provided with M A bus system (M is a natural number greater than or equal to 2) provided in a cascade-connected slave side device, and actively connects each clock synchronous serial data receiving circuit, wherein the serial data signal is a predetermined first stage A serial data signal line for supplying only the serial data signal input terminal in the clock synchronous serial data receiving circuit, and a serial clock signal line for supplying the serial clock signal to the serial clock signal input terminals in all clock synchronous serial data receiving circuits And the select signal to all A select signal line to be supplied to a select signal input terminal in the lock synchronous serial data receiving circuit, a serial data signal output terminal for the next stage in the nth stage (1 ≦ n <M) clock synchronous serial data receiving circuit, and n + 1 And a serial data signal line for the next stage for connecting to a serial data signal input terminal in the clock synchronous serial data receiving circuit of the stage.

  According to the clock synchronous serial data receiving circuit of the present invention, when a clock signal is erroneously recognized due to the influence of noise, the transmission error can be easily detected and the data can be ignored. Further, according to the bus system of the present invention, a clock synchronous serial data receiving function corresponding to the number of bits M times the reference number of bits can be realized by cascading M clock synchronous serial data receiving circuits. .

It is a schematic block diagram of a gaming machine provided with a clock synchronous serial data receiving circuit according to the present invention. 1 is a circuit configuration diagram showing an embodiment of a clock synchronous serial data receiving circuit according to the present invention. FIG. It is a timing chart when normal communication data is received by the clock synchronous serial data receiving circuit of this embodiment. It is a timing chart when abnormal communication data is received by the clock synchronous serial data receiving circuit of this embodiment. It is a schematic block diagram of the slave side device provided with the bus structure which can cascade-connect four clock synchronous serial data receiver circuits.

  Embodiments of a clock synchronous serial data receiving circuit according to the present invention will be described below in detail with reference to the accompanying drawings.

  A gaming machine 100 illustrated in FIG. 1 is a pachinko gaming machine capable of playing a ball game using a game ball. The main control board 200 responsible for controlling the main game progress in the gaming machine 100 controls various game function devices. For example, the sub-control board 300 mainly performing effect control by a liquid crystal display device or a decoration lamp provided at an appropriate position of the gaming machine 100 transmits a command signal for driving the lamp to the lamp connection board 400 and receives the lamp. A drive signal is output from the connection board 400 to the various lamps 110, and a lamp effect is executed.

  Here, the sub control board 300 is a master side device that transmits clock synchronous serial data, and the lamp connection board 400 is a slave side device that receives clock synchronous serial data. The lamp connection board 400 includes a clock synchronous serial data receiving circuit 1 that converts the received clock synchronous serial data into parallel data and outputs the parallel data. This clock synchronous serial data receiving circuit 1 is not limited to a pachinko game machine, and even in the case of a revolving game machine, when transmitting clock synchronous serial data from a master side device to a slave side device, Can be used for side devices.

  FIG. 2 is a circuit configuration diagram showing an embodiment of the clock synchronous serial data receiving circuit 1 described above. The clock synchronous serial data receiving circuit 1 mainly includes a shift register 11, a latch 12, and a counter 13, and uses an AND circuit 14, a negative logic OR circuit 15a, and a knot circuit 15b. Input signals to the clock synchronous serial data receiving circuit 1 are a serial data signal SD, a serial clock signal SCK, a select signal SEL, and a clear signal CLR.

  The clear signal CLR is a negative logic signal at the H level in a normal state, and is input to the CLR terminal of the latch 12 and the CLR terminal of the shift register 11 and the counter 13 via the OR circuit 15a. Therefore, when the clear signal CLR becomes L level, the shift register 11, the latch 12, and the counter 13 are initialized.

    The select signal SEL is an H level negative logic signal in a normal state, and is input to the CLR terminals of the shift register 11 and the counter 13 via the NOT circuit 15b and the OR circuit 15a, respectively. When the select signal SEL is normally at the H level, the shift register 11 and the counter 13 are stopped in the initial state. On the other hand, when the select signal SEL becomes L level, the CLR terminals of the shift register 11 and the counter 13 become H level, and the device becomes operable.

  The output of the AND circuit 14 to which the select signal SEL is applied to one input terminal remains at the L level until the Q3 output of the counter 13 described later is inverted to the H level and the select signal SEL becomes the H level. Does not fluctuate. Therefore, until the output of the AND circuit 14 changes to the H level and is input to the CK terminal of the latch 12, the output (for example, 8 bits) of the latch 12 is in a state of holding the previously latched output.

  The shift register 11 outputs the signal level of the serial data signal SD input to the D terminal to the QA terminal at the rising timing of the serial clock signal SCK input to the CK terminal. At the same timing, the signal level output to the QA terminal is output to the QB terminal. Similarly, the signal at the adjacent terminal is shifted to the QH terminal.

  The reception timing of the serial clock signal by the shift register 11 will be described with reference to FIGS. First, the case where the serial data signal is normally received will be described with reference to FIG.

  Since the shift register 11 becomes operable while the select signal SEL is at the L level, the serial data signal is detected at the rising edge timing of each clock pulse in the serial clock signal SCK (including eight clock pulse signals T1 to T8). SD data is taken in and shifted from QA to QH. Specifically, the first bit data “1” is registered in the QA from the serial data signal SD at the rising edge of the first clock pulse T1. Subsequently, the second bit data “1” from the serial data SD is registered in the QA at the rising edge of the second clock pulse T2, and the first bit data “1” already registered in the QA is shifted to QB. . Similarly, the third to eighth bit data “0”, “0”, “1”, “0”, “1” and “0” are received from the third clock pulse T3 to the eighth clock pulse T8, and from QA to QH. Stores 8-bit data.

  The bit data respectively stored in QA to QH of the shift register 11 is applied to the data input terminals D0 to D7 of the latch 12, but the output signal of the AND circuit 14 (detailed later) is applied to the CK terminal of the latch 12. Until it is input, it is not latched by the output terminals Q0 to Q7 of the latch 12. The QH of the shift register 11 can be taken out of the clock synchronous serial data receiving circuit 1. The signal obtained from the QH is a serial data signal obtained by shifting the serial data signal SD by 8 bits, and can be used as a serial data signal for the next stage (detailed later).

  On the other hand, when the select signal SEL becomes L level and the counter 13 starts operating, it is in an initial state, so the outputs of the Q0 to Q3 terminals remain at L level. Thereafter, the count value is incremented at the rising timing of the serial clock signal SCK input thereafter, and the result is output in binary from Q0 to Q3. In the counter 13, the output signal TP1 of the Q3 terminal corresponding to bit 3 becomes H level at the rising timing of the eighth pulse (eighth clock pulse T8) of the serial clock signal SCK.

  Further, the output signal TP1 of the Q3 terminal in the counter 13 is input to its own LD terminal. Input signals D0 to D3 are output from Q0 to Q3 at the rising timing of the CK terminal input when the LD terminal is at the H level. In the counter 13 of this configuration example, since D0 is connected to the H level and D1 to D3 are all connected to the L level, the count values of the Q0 to Q3 outputs are returned to “1” again. In other words, the output signal TP1 of the Q3 terminal changes from the L level to the H level at the rising edge of the CK terminal after the CLR terminal becomes the H level (n is an arbitrary natural number), and from the L level to the 8n + 1. It becomes L level again.

  Therefore, the counter 13 counts the number of serial clock signals detected while the select signal is active, and takes in when the counted value is a natural number multiple of the reference bit number (for example, 8). It functions as “take-in timing determination means for outputting a timing determination signal”. In the clock synchronous serial data receiving circuit 1 of the present embodiment, since the reference bit number to be output as parallel data is set to 8, the timing at which the bit number of data to be transferred is considered to be 8 (serial clock signal SCK The output signal TP1 of the Q3 terminal, which is the output of the counter 13, is set to the H level at the timing of counting up to eight clock pulses). Even when the reference bit number is 16 or 32, the serial clock signal SCK What is necessary is just to comprise so that the output signal TP1 of Q3 terminal may be set to H level at the timing which counted the clock pulse to 16 or 32.

  The above-described Q3 output TP1 of the counter 13 is ANDed with the select signal SEL by the AND circuit 14 and input to the CK terminal of the latch 12. Therefore, only when the select signal SEL becomes H level after the number of clock pulses of the serial clock signal SCK inputted to the clock synchronous serial data receiving circuit 1 becomes 8n and before it becomes 8n + 1. The output signal TP2 of the circuit 14 becomes H level and is input to the CK terminal of the latch 12. When the rising signal (the rising edge of the output signal TP2 of the AND circuit 14) is input to the CK terminal, the latch 12 latches the input signal from D0 to D7 and outputs the input signal from the Q0 to the Q7 terminal. That is, the first bit (least significant bit LSB) transmitted first is the Q7 terminal, the second bit is the Q6 terminal, the third bit is the Q5 terminal, the fourth bit is the Q4 terminal, and the fifth bit is the Q3 terminal. The 6th bit is latched at the Q2 terminal, the 7th bit is latched at the Q1 terminal, and the 8th bit (most significant bit MSB) transmitted last is latched at the Q0 terminal to obtain an 8-bit parallel signal. Can do.

  Therefore, the AND circuit 14 indicates that “when the select signal SEL becomes inactive within the period in which the capture timing determination signal (output signal TP1 of the Q3 terminal) is output by the capture timing determination means (counter 13). In this case, it functions as a “received data determining means for determining parallel data as received data”. When the select signal SEL becomes H level, the input to the CLR terminal of the counter 13 becomes L level and the operation is stopped, so that the output signal TP1 of the Q3 terminal becomes L level. Therefore, the period during which the output signal TP2 of the AND circuit 14 is at the H level is short (see FIG. 3), but the latch operation from the Q0 terminal to the Q7 terminal by the latch 12 is performed at the rising edge detection timing to the CK terminal. So there is no problem.

  Next, a case where the serial data signal cannot be normally received will be described with reference to FIG.

  Because the noise was added to the serial clock signal SCK and this noise was mistakenly recognized as the clock pulse T5, the fifth pulse was originally the clock pulse T6, the sixth pulse was the clock pulse T7, and the seventh pulse was the clock pulse. T8, the eighth clock pulse is counted as T9. Note that noise is often a signal with a very narrow width as shown in FIG. 4, but even a narrow signal is normal when the circuit operates based on a rising edge like a clock signal. It is mistaken for a signal.

  As described above, when a false detection of a clock pulse due to noise occurs, the output terminal QA to QH of the shift register 11 has an error of “010101001” at the timing when the select signal SEL becomes inactive H level. If data is output and the latch 12 fetches the data into the output terminals Q0 to Q7, a communication error occurs, and device operation with an incorrect parallel signal is executed, which may impair the reliability of the device itself.

  Therefore, the clock synchronous serial data receiving circuit 1 according to the present embodiment includes the counter 13 as the acquisition timing determination unit and the AND circuit 14 as the reception data determination unit. Can be prevented from being taken into the output terminals Q0 to Q7. That is, since the seventh pulse is normally counted as the clock pulse T8, the output signal TP1 of the Q3 terminal of the counter 13 becomes H level by detecting the rising edge of the clock pulse T8, and then the clock pulse T9. When the rising edge is detected, the output signal TP2 of the AND circuit 14 does not become H level and the CK terminal of the latch 12 remains L level even if the select signal SEL subsequently rises to H level. Therefore, erroneous data is not latched at the output terminals Q0 to Q7 of the latch 12.

  As described above, although there is a risk of erroneously detecting noise as a clock pulse regardless of the timing at which the serial clock signal SCK has noise while the select signal SEL is at the L level, this embodiment In the clock synchronous serial data receiving circuit 1, it is possible to prevent erroneous data from being latched at the output terminals Q <b> 0 to Q <b> 7 of the latch 12 regardless of the timing of erroneous detection of the clock pulse. Note that while the select signal SEL is at the L level, noise may be added to the serial data signal SD, and an error may occur in the data content itself. However, since it is very unlikely that noise with an extremely short time width will occur at the same timing as the rising edge of the clock pulse of the serial clock signal SCK, it is considered that there is no problem in practical use.

  As described above, according to the clock synchronous serial data receiving circuit 1 according to the present embodiment, when a clock signal is erroneously recognized due to the influence of noise, the transmission error is easily detected and the data is ignored. Therefore, it is possible to prevent the device operation based on the error data from being executed, and to avoid the risk of impairing the reliability of the device itself.

  Note that the clock synchronous serial data receiving circuit 1 alone according to the present embodiment can only deal with a parallel signal output of a predetermined number of reference bits. However, when a plurality of clock synchronous serial data receiving circuits 1 are functionally connected, it is possible to cope with a bit number that is a natural number multiple of the reference bit number. A bus system 2 for functionally connecting a plurality of clock synchronous serial data receiving circuits 1 will be described with reference to FIG.

  The master side device 301 is a transmission source of clock synchronous serial data, and a serial data signal SD, a serial clock signal SCK, a select signal SEL, and a clear signal CLR are supplied to the slave side device 401 via a wire harness or the like. . The bus system 2 is provided on the input side of the slave device 401 that receives these signals. Further, the bus system 2 shown in the present embodiment has a structure in which up to four clock synchronous serial data receiving circuits 1 can be functionally connected, and the first clock synchronous serial data receiving circuit 1 that is modularized can be mounted. A socket 21, a second socket 22, a third socket 23, and a fourth socket 24 are provided.

  When a plurality of clock synchronous serial data receiving circuits 1 are attached, it is necessary to attach them sequentially from the first socket 21. Further, the number of sockets to which the clock synchronous serial data receiving circuit 1 is attached is not particularly limited, and M sockets can be provided for cascade connection of M stages (M is a natural number of 2 or more). It ’s fine. In the bus system 2 shown in FIG. 5, only the first socket 21 and the second socket 22 are provided with the modular clock synchronous serial data receiving circuit 1 and the third socket 23 and the fourth socket 24 are left empty. It was supposed to be used. In this case, it is not necessary to mount dummy modules or the like in the empty third and fourth sockets 23 and 24, and only with the two clock synchronous serial data receiving circuits 1 mounted in the first and second sockets 21 and 22, It can function as a serial data receiving port.

  The serial data signal line L1 that receives the serial data signal from the master device 301 is connected only to the serial data signal input terminal in the first clock synchronous serial data receiving circuit 1A attached to the first socket 21 that is the first stage.

  On the other hand, the serial clock signal line L2 that receives the serial clock signal SCK from the master device 301 is connected to the first to fourth clock synchronous serial data receiving circuits 1A to 1D attached to the first to fourth sockets 12 to 24. Connect to each serial clock signal input terminal. The select signal line L3 that receives the select signal SEL from the master side device 301 is input to each select signal of the first to fourth clock synchronous serial data receiving circuits 1A to 1D mounted in the first to fourth sockets 12 to 24. Connect to the terminal. The clear signal line L4 that receives the clear signal CLR from the master device 301 is input to each of the clear signals of the first to fourth clock synchronous serial data receiving circuits 1A to 1D mounted in the first to fourth sockets 12 to 24. Connect to the terminal. That is, the serial clock signal SCK, the select signal SEL, and the clear signal CLR are supplied to the first to fourth clock synchronous serial data receiving circuits 1A to 1D at the same timing.

  The next-stage serial data signal output terminal QH in the first-stage first clock synchronous serial data receiving circuit 1A is connected to the second-stage second clock synchronous serial data receiving circuit 1B by the second-stage serial data signal line L51. Connected to the serial data signal input terminal, the serial data signal for the next stage is supplied from the first clock synchronous serial data receiving circuit 1A to the second clock synchronous serial data receiving circuit 1B. Since the serial data signal for the next stage is a serial data signal obtained by shifting the serial data signal SD from the master device 301 by 8 bits, the first bit of the serial data signal SD is changed to the first bit when the rising edge of the eighth clock pulse is detected. It is supplied to the serial data signal input terminal of the 2-clock synchronous serial data receiving circuit 1B, and when the rising edge of the ninth clock pulse is detected, the output of the shift register 11 in the second clock synchronous serial data receiving circuit 1B The first bit of the serial data signal SD is registered at the terminal QA.

  That is, when the select signal SEL is at the L level, 16-bit serial data is transmitted by the serial data signal SD, and when the 16-bit data is captured by the 16 clock pulses of the serial clock signal SCK, the first data Bits to 8th bit are output from the output signal line L6B of the second clock synchronous serial data receiving circuit 1B, and 9th to 16th bits are output from the output signal line L6A of the first clock synchronous serial data receiving circuit 1A. Therefore, when the first clock synchronous serial data receiving circuit 1A and the second clock synchronous serial data receiving circuit 1B are cascade-connected, serial data having a bit number (16) that is twice the reference bit number (8) is supported. Can be made.

  Similarly, if the third clock synchronous serial data receiving circuit 1C is set in the third socket 23, the next-stage serial data in the second clock synchronous serial data receiving circuit 1B is transmitted by the third-stage serial data signal line L52. The signal output terminal QH and the serial data signal input terminal in the third clock synchronous serial data receiving circuit 1C are connected, and the first to eighth bits are from the output signal line L6C of the third clock synchronous serial data receiving circuit 1C. The 9th to 16th bits are output from the output signal line L6B of the second clock synchronous serial data receiving circuit 1B, and the 17th to 24th bits are the output of the first clock synchronous serial data receiving circuit 1A. Since it is output from the signal line L6A, the first to third clock synchronous serial data reception When the road 1A~1C cascading, 3 times the number of bits of the reference number of bits (8) can be made to correspond to the serial data (24).

  Further, when the fourth clock synchronous serial data receiving circuit 1C is set in the fourth socket 24, the next-stage serial data signal in the third clock synchronous serial data receiving circuit 1C is obtained by the fourth-stage serial data signal line L53. The output terminal QH and the serial data signal input terminal in the fourth clock synchronous serial data receiving circuit 1D are connected, and the first to eighth bits are output from the output signal line L6D of the second clock synchronous serial data receiving circuit 1D. The 9th to 16th bits are output from the output signal line L6C of the third clock synchronous serial data receiving circuit 1C, and the 17th to 24th bits are the output signal of the second clock synchronous serial data receiving circuit 1B. Is output from the line L6B, and the 25th to 32nd bits are the first clock synchronous serial Since the first to fourth clock synchronous serial data receiving circuits 1A to 1D are cascade-connected, the number of bits (32) is four times the reference number of bits (8). It is possible to correspond to serial data transfer.

  That is, when M clock-synchronous serial data receiving circuits 1 are cascade-connected, the next-stage serial data signal output terminal QH in the n-th (1 ≦ n <M) clock-synchronous serial data receiving circuit 1; If the serial data signal input terminal in the n + 1 stage clock synchronous serial data receiving circuit 1 is connected, serial data transfer of the number of reference bits × M can be supported. According to such a bus system 2, even if the number of driven devices (for example, decorative lamps) connected to the slave-side device 401 increases, it can be easily handled by increasing the number of bits of serial data. Therefore, there is no need to change the design to increase the signal from the master device 301, the design effort is reduced, and no process change is required in the assembly work.

  As mentioned above, although the embodiment of the clock synchronous serial data receiving circuit and the bus system according to the present invention has been described based on the accompanying drawings, the present invention is not limited to this embodiment and is described in the claims. As long as the configuration is not changed, the known equivalent technical means may be diverted.

DESCRIPTION OF SYMBOLS 1 Clock synchronous type serial data receiving circuit 11 Shift register 12 Latch 13 Counter 14 AND circuit 15a OR circuit 15b Not circuit

Claims (3)

It has at least three signal inputs: serial data signal, serial clock signal, and select signal. While the select signal is active, the serial data signal is captured at the change timing of the serial clock signal, and 1-bit data In a clock synchronous serial data receiving circuit that shifts every time a signal is received and converts it into parallel data of a reference number of bits,
Capture timing determination means for counting the number of serial clock signals detected while the select signal is active and outputting a capture timing determination signal when the counted value is a natural number multiple of the reference bit number When,
Reception data confirmation means for confirming the parallel data as reception data only when the select signal becomes inactive within a period in which the capture timing determination signal is output by the capture timing determination means;
A clock-synchronous serial data receiving circuit comprising:   2. The clock synchronous serial data receiving circuit according to claim 1, wherein a serial data signal for the next stage obtained by shifting the serial data signal by a reference bit number can be output. 3. At least the serial data signal, the serial clock signal, and the select signal are supplied from a master side device, and the clock synchronous serial data receiving circuit according to claim 2 is cascaded in M stages (M is a natural number of 2 or more). A bus system that is provided in a connected slave device and actively connects each clock synchronous serial data receiving circuit,
A serial data signal line for supplying the serial data signal only to a serial data signal input terminal in a predetermined first stage clock synchronous serial data receiving circuit;
A serial clock signal line for supplying the serial clock signal to serial clock signal input terminals in all clock synchronous serial data receiving circuits;
A select signal line for supplying the select signal to select signal input terminals in all clock synchronous serial data receiving circuits;
A serial data signal output terminal for the next stage in the n-th stage (1 ≦ n <M) clock-synchronous serial data receiving circuit is connected to a serial data signal input terminal in the n + 1-stage clock-synchronous serial data receiving circuit. Serial data signal line for the next stage,
A bus system comprising:

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