KR20030052020A - Parity error detection circuit - Google Patents

Abstract

PURPOSE: A parity error detection circuit is provided to stably detect by synchronizing with the clock with implementing the parity check in a further rapid time in comparison with a conventional method. CONSTITUTION: A parity error detection circuit includes a first NAND gate(21) for outputting by logically calculating the external receive signal and the feedback signal, a first XOR gate(22) for outputting by logically calculating the inputted data signal and the output signal of the first NAND gate(21), a shift register(23), a second XOR gate(24), a second NAND gate(25) and an inverter(26) for outputting the final output signal by inverting the output signal of the second NAND gate(25). The second XOR gate receives the output signal of the second XOR gate(24) and the first input signal to determine the parity inputted from the outside and outputs the received signal by being logically calculated. The second NAND gate(25) receives the output signal of the second XOR gate(24) the second input signal to determine the parity inputted from the outside and outputs the received signal by being logically calculated.

Description

Parity error detection circuit

The present invention relates to a parity error detection circuit, and more particularly, to a parity error detection circuit suitable for checking transmission error of received data in serial data reception.

In general, in serial data communication, parity bits are used to confirm correct transmission of data.

When transmitting, parity bits are generated and transmitted through the data bits, so no special technique is required. However, when receiving, there is a fear of data distortion due to noise during transmission.

Hereinafter, a conventional parity error detection circuit will be described with reference to the accompanying drawings.

1 illustrates a typical 8-bit serial communication data format.

As shown in FIG. 1, a parity check is performed according to an 8-bit serial communication data format.

2 is a circuit diagram showing a conventional shift register.

As shown in FIG. 2, a plurality of registers 100 are connected in series, and after the register 100 is initialized by the shift clock signal RX_SH_CLK, the serial data RX_DATA is synchronized with the RX_SH_CLK signal and shifted one by one to the right. To make it work.

At this time, if shifted 11 times, the start bit value is located in the final output signal LSB0, and the output value of the second register becomes the parity bit when transmitting even and odd parity. If no parity, stop1.

3 is a circuit diagram showing a conventional parity error detection circuit.

As shown in FIG. 3, first, second, third, and fourth equivalence gates that receive logically arithmetic operation of two adjacent data among the eight input data D0 to D7 as inputs and output the logical operation (1,2,3,4), output signals of the first and second equalization gates (1,2) and output signals of the third and fourth equalization gates (3,4) as inputs The fifth and sixth equivalent gates 5 and 6 to receive and logically output and the output signals of the fifth and sixth equivalent gates 5 and 6 as inputs A seventh equalization gate 7, a first inverter 8 which inverts and outputs an output signal of the seventh equalization gate 7, an output signal of the first inverter 8 and an external input A first NAND gate 10 for receiving a logic operation and outputting the first and second input signals ps1 and ps0 for determining parity to be input, and the second input signal p A second inverter 9 which inverts and outputs s0, an output signal of the second inverter 9, an output signal of the seventh equalization gate 7, and a first input signal ps1 are input as inputs, respectively. A second NAND gate 11 for receiving and performing a logic operation and outputting, a third NAND gate 12 for receiving and outputting an output signal of the first and second NND gates 10 and 11 as an input, and An XOR gate 13 which receives an output signal of the third NAND gate 12 and an external parity signal as an input, but outputs a logic operation, an output signal of the XOR gate 13 and a first input signal ps1. ) And a fourth NAND gate 14 for receiving and receiving an external parity enable signal parityEn as an input and performing a logic operation, and inverting the output signal of the fourth NAND gate 14 to obtain a final output signal ( The third inverter 15 outputs PE_SET).

Fig. 4 is a simulation showing the input of a serial signal as an example for an even parity operation in which [PS1, PS0] is [11] in a conventional parity error detection circuit.

As shown in FIG. 4, in the conventional parity error detection circuit, the PE_SET value is determined by the output value of FIG. 2 and ps1, ps0, parity, and parityEn.

Here, ps1 and ps0 are signals for determining the parity type. If [ps1, ps0] is [11], it is even, if [10] is odd, and if [01] is zero, [00] Defined as no parity.

If the output value net6 of the seventh equality gate 7 is "1", even data is input. If "0", odd data is input.

The output value net0167 of the third NAND gate 12 is determined according to ps1 and ps0 determining a parity type, and is an expected parity value for the eight input data D0 to D7.

Accordingly, when the error value is calculated by calculating the output value net0167 of the third NAND gate 12 and the received parity signal with the XOR gate 13, “1” is an output value net0221 of the XOR gate 13 when an error occurs. do.

On the other hand, in the operation of the fourth NAND gate 14, the final PE_TEST is determined by the even, odd condition, and parity enable signal parityEn by the input of ps1.

Here, since eight data DO to D7 and a parity signal are output at the same time, there is a problem of generating a fine glitch due to signal delay at the output of the XOR gate 13.

However, the above-mentioned conventional parity error detection circuit has the following problems.

That is, since eight data (DO to D7) and a parity signal (parity) inputted in series are output at the same time, there is a problem of minute glitches due to signal delay at the output of the XOR gate.

The present invention has been made to solve the above-mentioned conventional problems. By synchronizing the serial data to a clock and directly feedbacking the data value output from the shift register, a real-time parity signal is obtained for the data input, and an input time difference between two nodes is obtained. It is an object of the present invention to provide a parity error detection circuit for solving the glitch problem caused by the present invention.

1 illustrates a typical 8-bit serial communication data format.

2 is a circuit diagram showing a conventional shift register

3 is a circuit diagram illustrating a conventional parity error detection circuit.

Fig. 4 is a simulation showing the input of a serial signal as an example for an even parity operation in which [PS1, PS0] is [11] in a conventional parity error detection circuit.

5 is a circuit diagram showing a parity error detection circuit according to the present invention;

Fig. 6 is a simulation showing the input of a serial signal as an example for an even parity operation in which [PS1, PS0] is [11] in the parity error detection circuit of the present invention.

Explanation of symbols for the main parts of the drawings

21: first NAND gate 22: first XOR gate

23: shift register 24: second XOR gate

25: second NAND gate 26: inverter

The parity error detection circuit according to the present invention for achieving the above object includes a first NAND gate that receives an external receive signal and a feedback signal and performs a logic operation on the feedback signal, an input data signal, and an output signal of the first NAND gate. A first XOR gate that receives and outputs a logic operation, a shift register that stores an output signal of the first XOR gate after being initialized by an external shift reset signal and outputs a value stored in synchronization with the shift clock signal; A second XOR gate that receives a logic operation and outputs an output signal of the shift register and a first input signal that determines an externally input parity, and determines an output signal of the second XOR gate and an externally input parity A second NA that receives a second input signal and a parity enable signal as inputs, and outputs a logical operation And an inverter for inverting an output signal of the second NAND gate and outputting a final output signal.

Hereinafter, a parity error detection circuit according to the present invention will be described in detail with reference to the accompanying drawings.

In the present invention, in the serial data communication, a parity value is sent to the sender so that the sender can check whether the data is correctly received without being distorted during transmission. On the receiving end, the receiver receives the data and the expected parity value. The parity values received are compared.

As a result, if the expected value and the received value are the same, it is interpreted that the data is correctly transmitted. If different from each other, it is determined that the value is distorted during transmission.

If an error occurs during transmission, the transmitter may be able to retransmit by notifying the transmitter of information on the error, but the present invention does not take this into consideration and the circuit checks whether the received data is correctly transmitted.

5 is a circuit diagram showing a parity error detection circuit according to the present invention.

As shown in FIG. 5, the first NAND gate 22 which receives and receives an external receive signal and a feedback signal bbb and performs a logical operation and outputs the data signal RX− DATA and the first XOR gate 22 for receiving and outputting the output signal aa of the first NAND gate 21 and performing a logical operation, and after being initialized by an external shift reset signal RX_SH_RST, the first XOR gate ( A shift register 23 which stores the output signal in of 22 and outputs values (inverted signal bbb and non-inverted signal b_parity) stored in synchronization with the shift clock signal RX_SH_CLK, and the shift A second XOR gate 24 that receives and outputs an output signal b_parity of the register 23 and a first input signal PS0 for determining parity input from the outside, and outputs a logical operation; A second input for determining an output signal p_result of 24) and a parity input from the outside; A second NAND gate 25 that receives the output signal PS1 and the parity enable signal parityEn as inputs, and outputs a logic operation, and inverts an output signal of the second NAND gate 25 to generate a final output signal ( And an inverter 26 for outputting PE_SET).

Instead of the first XOR gate 22, an equalization gate and an inverter may be used.

Fig. 6 is a simulation showing the input of a serial signal as an example for an even parity operation in which [PS1, PS0] is [11] in the parity error detection circuit of the present invention.

As shown in Fig. 6, in the parity error detection circuit according to the present invention, the RX-DATA remains high (IDLE state) and then changes to low (start signal), after which the transmission board ratio According to the baud rate, 8-bit data, 1-bit parity, and stop bits are transmitted at regular time intervals.

Data is sequentially received in synchronization with the shift clock signal RX_SH_CLK.

Meanwhile, the output signal of the first NAND gate 21 remains high due to the RECEIVE signal Low, and the inverted signal bbb of the shift register 23, i.e., the first NAND gate 21, by the initial RX_SH_RST signal. The input feedback signal is low.

When RX-DATA changes to Low and becomes an input, the shift register 23 executes an instruction of the first NAND gate 21 which outputs the stored Low value.

Since the RECEIVE signal does not change until the reception is completed, the values are changed sequentially according to RX-DATA.

Finally, when the eighth data value " L " is inputted, the output signal aaaa of the first NAND gate 21 becomes High and the non-inverted signal of the shift register 23 becomes High. This indicates an even data state because the number of high states of the input data HLHH_HLLL is four.

If PS1 and PS0 are high, the parity bit should be low when defined as even parity.

However, since the value of the received data is in the "High" state, it should be determined that the distorted data has been received.

At the 10th RX_SH_CLK when the parity bit is received, the output signal aaaa of the first NAND gate 21 changes to a low state, and the non-inverting signal b_parity of the shift register 23 also changes to a low state.

As a result, since the number of high states including the parity value is five, the parity error signal is output with the par_en value being PE_SET high.

As described above, the parity error detection circuit according to the present invention has the following effects.

That is, parity check is performed within a faster time (shift cycle signal of one cycle) than the prior art, and can be stably detected by synchronizing to the clock.

Claims (2)

A first NAND gate receiving and receiving an external receive signal and a feedback signal and performing a logic operation; A first XOR gate which receives an input data signal and an output signal of a first NAND gate and performs a logic operation on the first XOR gate; A shift register which stores an output signal of the first XOR gate after being initialized by an external shift reset signal and outputs a value stored in synchronization with the shift clock signal; A second XOR gate configured to receive an output signal of the shift register and a first input signal for determining parity input from an external source and perform a logic operation on the output signal; A second NAND gate which receives and outputs an output signal of the second XOR gate and a second input signal and a parity enable signal for determining parity input from the outside, and outputs a logic operation; And an inverter for inverting an output signal of the second NAND gate and outputting a final output signal. The parity error detection circuit of claim 1, wherein the input data signal is input in series.