CN112073152B

CN112073152B - FPGA anti-interference processing method for improving reliability of CHSI received data

Info

Publication number: CN112073152B
Application number: CN202010966570.1A
Authority: CN
Inventors: 李建秋; 王爱国; 李正勇; 张江
Original assignee: Sichuan Jiuzhou ATC Technology Co Ltd
Current assignee: Sichuan Jiuzhou ATC Technology Co Ltd
Priority date: 2020-09-15
Filing date: 2020-09-15
Publication date: 2022-06-24
Anticipated expiration: 2040-09-15
Also published as: CN112073152A

Abstract

The invention discloses an FPGA anti-interference processing method for improving CHSI received data reliability, which at least comprises the following steps: s1: inputting a TTL serial clock CLK and DATA DATA of an original CHSI bus into the FPGA; s2: synchronous processing of input asynchronous signals by the FPGA; s3: finishing the waveform burr removal processing of the input data; s4: completing the detection of the burst dislocation position of the waveform; s5: completing adaptive waveform adjustment; s6: CHSI input data acquisition; s7: CRC checking the received data message; s8: and judging the header and the length of the data message. The method improves the reliable transmission capability of the CHSI for receiving data communication, and solves the problem of bit error rate caused by poor receiving anti-interference capability and incapability of processing the sudden waveform dislocation and burr interference in real time in the prior art.

Description

FPGA anti-interference processing method for improving reliability of CHSI received data

Technical Field

The invention belongs to the field of digital signal processing, relates to an FPGA data processing method, and particularly relates to an FPGA anti-interference processing method for improving CHSI received data reliability.

Background

A chsi (crypto Host Serial interface) Serial bus communication method is proposed in the foreign related communication technology standard, and is used for data transmission between a communication sender and a communication receiver. The CHSI bus comprises a CHSI sending bus and a CHSI receiving bus, and each group of buses has a clock CLK signal and a DATA DATA signal with TTL levels.

The real-time transmission rate of the CHSI serial interface is 16Mbit/S, the sending and receiving of DATA messages between the master communication equipment and the slave communication equipment are independently transmitted through two groups of independent signal lines, two signal lines are arranged in each group, one signal line is a clock line ClK, and the other signal line is a DATA line DATA; the electrical characteristic is a TTL level. The CHSI serial data frame structure is characterized in that according to the sequence of the whole data frame from left to right, the first byte represents the route of a data packet and is divided into two groups, the high-order 4 bits represent an information sink, and the low-order 4 bits represent an information source; the second byte represents the data packet identification and is divided into two groups, the high-order 4 bits represent the message category, and the low-order 4 bits represent the message number; the third byte represents the message content length, i.e. from 0 to 256 bytes, the message length being an integer number of bytes; the fourth part is a message content field, from 0 to 256 bytes, and the inside of each Byte is arranged from left to right as Byte1(bit0 … bit7) … Byte256(bit0 … bit 7); the last two bytes are CRC fields, the selected CRC check polynomial is X16+ X12+ X5+1, and 16 bits are occupied.

In practical engineering application, the CHSI serial bus waveform is easily interfered by an internal radio frequency signal or an external electromagnetic signal of a communication device, so that phenomena such as transmission clock CLK and DATA signal are easily generated, such as glitches and waveform "dislocation", and sudden transmission errors such as signal amplitude and phase jump are easily generated, so that transmission is unreliable. Especially, when the device is applied in a complex electromagnetic environment and a man-made interference environment, the unreliable transmission phenomenon of signals is more obvious, even communication failure is directly caused, and the communication performance is seriously influenced.

In the prior CHSI receiving processing technology, except for enhancing the hardware method processing such as reliable connector plugging of clock CLK and DATA DATA signals, ground supply performance, PCB wiring and the like, the FPGA can only eliminate '0 to 1' or '1 to 0' type burrs, and the width of the burrs is not enough, and only can eliminate the 'burrs' within the range of 0 to 15.625 ns.

In the existing CHSI receiving and processing technology, DATA sampling mainly depends on the timing relation between a clock CLK and DATA DATA, a fault-tolerant mechanism is not established, and the communication failure caused by the sudden 'dislocation' of waveforms of the clock CLK and the DATA DATA cannot be processed.

In the existing CHSI receiving and processing technology, the receiving judgment after data sampling mainly adopts CRC (cyclic redundancy check) check, no data message word header and length judgment are adopted, and even if an error occurs, an explicit error type is not indicated.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provide an FPGA anti-interference processing method for improving the reliability of CHSI received data, the method improves the reliable transmission capability of CHSI received data communication, and solves the problem of bit error rate caused by poor receiving anti-interference capability and incapability of processing burst waveform dislocation and burr interference in real time in the prior art.

The purpose of the invention is realized by the following technical scheme:

an FPGA anti-interference processing method for improving CHSI receiving data reliability at least comprises the following steps: s1: inputting a TTL serial clock CLK and DATA DATA of an original CHSI bus into the FPGA; s2: synchronous processing of input asynchronous signals by the FPGA; s3: finishing the waveform burr removal processing of the input data; s4: completing the detection of the burst dislocation position of the waveform; s5: completing adaptive waveform adjustment; s6: CHSI input data acquisition; s7: CRC checking the received data message; s8: and judging the header and the length of the data message.

According to a preferred embodiment, the step S1 specifically includes: s11: detecting whether the states of signal waveforms of a clock CLK and a DATA DATA are changed in real time; s12: according to the waveform timing of the CHSI input clock CLK and the DATA defined in the standard, in the idle state, the logic levels of the waveforms of the clock CLK and the DATA are both "1" high level, and the detection of the initial state of the signal is completed.

According to a preferred embodiment, the step S2 specifically includes: s21: calling 3D triggers in the FPGA; s22: the incoming clock CLK and DATA signals are delayed by 3 beats using a 128Mhz clock, respectively.

According to a preferred embodiment, the step S3 specifically includes: s31: the FPGA adopts a 128Mhz clock to synchronously sample clock CLK and DATA DATA signals input by a serial 16Mhz/s, and delay processing is carried out; s32: waveform inverse narrow processing, namely delaying the CLK clock and DATA DATA signal waveforms after synchronous processing by 3 128Mhz clock cycles respectively; s33: a waveform stretching process of delaying the CLK clock and DATA signals after the "inverse narrow" by 3 128Mhz clock cycles, respectively; s34: a waveform re-stretching process of delaying the waveforms of the CLK clock and the DATA signal stretched in step S33 by 3 cycles of 128Mhz clock, respectively; s35: and (4) performing waveform re-narrowing processing, namely delaying the CLK clock and the DATA DATA signal re-widened in the step S34 by 3 128Mhz clock cycles respectively, so as to realize the second restoration of the waveforms of the CLK clock and the DATA DATA signal.

According to a preferred embodiment, the step S4 specifically includes: s41: performing dislocation mark counting on input waveforms of a CHSI clock CLK and DATA DATA after deburring processing, delaying 14 128Mhz clock cycles respectively, shifting register waveforms, and setting a Count value Count from the first falling edge of the CLK to the first falling edge of the DATA to be 6 128Mhz clocks in a standard; s42: determining a misalignment decision rule, wherein when the flag Count result in step S41 is in a range of 1 to 5 128MHZ, it indicates that the DATA waveform is shifted to the left by a corresponding period of 1 to 5 128MHZ relative to the clock CLK waveform; when the flag Count result in step S41 is in the range of 7 to 11 128MHZ, it indicates that the DATA waveform is shifted to the right by 7 to 11 cycles of 128MHZ relative to the clock CLK waveform; the shift register is performed for 13 cycles of 128Mhz for the input clock CLK and the DATA, respectively.

According to a preferred embodiment, the step S5 specifically includes: s51: establishing a waveform correction lookup table according to the corresponding relation between the Count value of the dislocation mark Count and the time sequence of the standard waveform; s52: and adaptively adjusting the waveforms of the time CLK and the DATA DATA according to the waveform correction lookup table, and outputting the waveforms to the next stage for DATA sampling processing.

According to a preferred embodiment, the step S6 specifically includes: s61: for standard clock and data waveforms formed after self-adaptive adjustment, delaying CLK for 3 beats according to the time sequence relation of the clock and the data, and acquiring data at the rising edge of the delayed clock of 2 nd beat to ensure the data at the most middle position of the data bit waveform; s62: and defining a register variable Buff and finishing the storage of the acquired data.

According to a preferred embodiment, the step S7 specifically includes: s71: according to the CRC check polynomial specified in the standard: x16+ X12+ X5+1, and CRC check calculation is completed; s72: when the CRC check calculation result is different from the received CRC value and indicates that an error exists, discarding the frame data and sending an identification signal indicating that the CRC check fails.

According to a preferred embodiment, the step S8 specifically includes: s81: according to a data communication protocol agreed with a sender, performing header judgment on a data message subjected to CRC, and when the data message is judged to have errors, discarding corresponding frame data and sending a header undefined identification signal; s82: and according to a data communication protocol agreed with the sender, judging the length of the data message subjected to the header check, and sending the qualified data message to the next-stage data processing.

The main scheme and the further selection schemes can be freely combined to form a plurality of schemes which are all adopted and claimed by the invention; in the invention, the selection (each non-conflict selection) and other selections can be freely combined. The skilled person in the art can understand that there are many combinations, which are all the technical solutions to be protected by the present invention, according to the prior art and the common general knowledge after understanding the scheme of the present invention, and the technical solutions are not exhaustive herein.

The invention has the beneficial effects that: according to the CHSI receiving time sequence characteristics and the phenomenon that the waveform is easily interfered, a fault-tolerant mechanism is established in FPGA data processing, a deburring anti-interference method is adopted, high-magnification sampling, synchronous processing of asynchronous communication and real-time detection of waveform dislocation burst positions are adopted, self-adaptive waveform adjustment to a standard waveform is achieved, correct sampling of data is guaranteed, and meanwhile CRC (cyclic redundancy check) checking, message header information and data length judgment are carried out. The correctness of the CHSI for receiving the data message is ensured, and the reliability of data transmission is improved. The invention provides a solution, establishes a fault-tolerant mechanism and effectively solves the problem of unreliable CHSI data transmission.

Drawings

Fig. 1 is a schematic diagram of a data processing flow of the FPGA anti-interference processing method of the present invention.

Fig. 2 is a timing diagram of waveforms of a standard CHSI bus in the FPGA interference rejection processing method of the present invention.

Fig. 3 is a schematic diagram illustrating the occurrence of "glitches" in the FPGA anti-interference processing method of the present invention.

FIG. 4 is a flow chart of FPGA processing for eliminating "glitches" in the waveform in the FPGA anti-interference processing method of the present invention.

FIG. 5 is a pattern of sudden change of "skew" between waveforms of the CHSI clock CLK and the DATA DATA in the FPGA interference rejection processing method of the present invention.

Fig. 6 is a processing flow chart of step S5 in the FPGA interference rejection processing method of the present invention.

Fig. 7 is a schematic diagram of state division and corresponding time sequence in the data acquisition process of step S6 in the FPGA anti-interference processing method of the present invention.

Fig. 8 is a data acquisition processing flow chart of step S6 in the FPGA anti-interference processing method of the present invention.

FIG. 9 is a flowchart of the processing of steps S7 and S8 in the FPGA anti-interference processing method of the present invention.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.

It should be noted that, in order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention are clearly and completely described below, and it is obvious that the described embodiments are some embodiments of the present invention, but not all embodiments.

Thus, the following detailed description of the embodiments of the present invention is not intended to limit the scope of the invention as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate orientations and positional relationships that are conventionally used in the products of the present invention, and are used merely for convenience in describing the present invention and for simplicity in description, but do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and therefore, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.

Furthermore, the terms "horizontal", "vertical", "overhang" and the like do not imply that the components are required to be absolutely horizontal or overhang, but may be slightly inclined. For example, "horizontal" merely means that the direction is more horizontal than "vertical" and does not mean that the structure must be perfectly horizontal, but may be slightly inclined.

In the description of the present invention, it should also be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

In addition, in the present invention, if the specific structures, connections, positions, power source relationships, etc., are not specifically written, the structures, connections, positions, power source relationships, etc., related to the present invention, can be known to those skilled in the art without creative work on the basis of the prior art.

Example 1

Referring to fig. 1, the present invention discloses an FPGA anti-interference processing method for improving reliability of CHSI received data, where the FPGA anti-interference processing method at least includes the following steps.

Step S1: and inputting a TTL serial clock CLK and DATA DATA of the original CHSI bus into the FPGA. The externally input, i.e., the waveform data and the time waveform input in step S1 are received and detected in real time inside the FPGA.

Preferably, the step S1 specifically includes: s11: the state of the clock CLK and DATA signal waveforms is detected in real time for a change. S12: according to the waveform timing of the CHSI input clock CLK and the DATA defined in the standard, in the idle state, the logic levels of the waveforms of the clock CLK and the DATA are both "1" high level, and the detection of the initial state of the signal is completed.

Step S2: and synchronously processing the input asynchronous signals by the FPGA. And (5) according to the step S2, carrying out synchronous logic processing by using 3D triggers in the FPGA to eliminate the metastable state of the signal.

Preferably, the step S2 specifically includes: s21: and calling 3D triggers in the FPGA. S22: the incoming clock CLK and DATA signals are delayed by 3 beats using a 128Mhz clock, respectively. I.e. 3 cycles of 128Mhz delay. Therefore, the synchronous logic design is realized when the clock and data signals lag to the rising edge of the 3 rd 128Mhz clock, and the metastable state can be effectively avoided.

Step S3: and finishing the waveform deburring processing of the input data. The input clock CLK and DATA waveforms are delayed and subjected to "inverse narrowing", "stretching (reducing)", "re-stretching", and "re-reducing" processing, respectively, to eliminate "1 to 0" and "0 to 1" glitches.

Preferably, referring to fig. 4, the step S3 specifically includes:

step S31: the FPGA adopts a 128Mhz clock to synchronously sample clock CLK and DATA DATA signals input by a serial 16Mhz/s, and carries out delay processing.

Step S32: and performing waveform narrowing processing, namely delaying the CLK clock and DATA DATA signal waveforms after synchronous processing by 3 128Mhz clock cycles respectively. Namely, generating CLK _ r1, CLK _ r2, CLK _ r 3; DATA _ d1, DATA _ d2, DATA _ d3, ANDed, respectively, are: the "0 to 1" glitches in the CLK and DATA signal waveforms are removed from "CLK _ zhai ═ CLK _ r1& CLK _ r2& CLK _ r 2" and "DATA _ zhai ═ DATA _ d1& DATA _ d2& DATA _ d 3", respectively.

Step S33: the waveform stretching process delays the "inverse narrow" CLK clock and DATA signals by 3 128Mhz clock cycles, respectively. Namely CLK _ zhai _ r1, CLK _ zhai _ r2, CLK _ zhai _ r 3; DATA _ zhai _ d1, DATA _ zhai _ d2, DATA _ zhai _ d 3. Respectively "phase or", i.e.: "CLK _ kuan1 ═ CLK _ zhai _ r1| CLK _ zhai _ r2| CLK _ zhai _ r 3", "DATA _ kuan1 ═ DATA _ zhai _ d1| DATA _ zhai _ d2| DATA _ zhai _ d 3", realizes the first restoration of the CLK clock and DATA signal waveforms.

Step S34: the waveform re-stretching process delays the waveforms of the CLK clock and the DATA signal stretched in step S33 by 3 cycles of 128Mhz clock, respectively. Namely: generating CLK _ kuan1_ r1, CLK _ kuan1_ r2, CLK _ kuan1_ r 3;

DATA _ kuan1_ d1, DATA _ kuan1_ d2, DATA _ kuan1_ d3, respectively "or" are:

“CLK_kuan2＝CLK_kuan1_r1&CLK_kuan1_r2&CLK_kuan1_r3”，

"DATA _ kuan2 ═ DATA _ kuan1_ d1& DATA _ kuan1_ d2& DATA _ kuan1_ d 3", the "1 to 0" glitch in the CLK clock and DATA signal waveforms, respectively, is removed.

Step S35: and (4) performing waveform re-narrowing processing, namely delaying the CLK clock and the DATA DATA signal re-widened in the step S34 by 3 128Mhz clock cycles respectively, so as to realize the second restoration of the waveforms of the CLK clock and the DATA DATA signal. Namely: CLK _ kuan2_ r1, CLK _ kuan2_ r2, CLK _ kuan2_ r 3; DATA _ kuan2_ d1, DATA _ kuan2_ d2, DATA _ kuan2_ d3, respectively, and, i.e.: "CLK _ kuan2_ r1& CLK _ kuan2_ r2& CLK _ kuan2_ r 3", and "DATA _ kuan2_ d1& DATA _ kuan2_ d2& DATA _ kuan2_ d 3" realize the second restoration of the CLK clock and DATA signal waveforms.

Step S4: and completing the detection of the burst staggered position of the waveform. And marking dislocation counting in the FPGA according to the standard corresponding relation of the clock and the data waveform, and establishing a waveform correction corresponding table.

The step S4 specifically includes:

step S41: the input waveforms of the CHSI clock CLK and the DATA DATA after the deburring processing are counted by a dislocation mark, 14 cycles of 128Mhz clock are delayed respectively, and the registered waveforms are shifted. That is to say that the first and second electrodes,

“CLK_delay[13:0]＝{CLK_delay[11:0],CLK},DATA_delay[13:0]＝{DATA_delay[11:0],DATA}。”

the first falling edge Count value Count counted from the first falling edge of CLK to Data is specified in the standard to be 6 128Mhz clocks.

Step S42: and determining a malposition decision rule.

When the flag Count result in step S41 is in the range of 1 to 5 128MHZ, it indicates that the DATA waveform is shifted to the left of the clock CLK waveform by 1 to 5 cycles of 128 MHZ.

When the flag Count result in step S41 is in the range of 7 to 11 128MHZ, it indicates that the DATA waveform is shifted to the right by 7 to 11 cycles of 128MHZ relative to the clock CLK waveform; the shift register is performed for 13 cycles of 128Mhz for the input clock CLK and the DATA, respectively, at the same time.

Step S5: and completing the adaptive waveform adjustment. And realizing the adaptive adjustment of the waveforms of the clock CLK and the DATA DATA according to the 'dislocation' counting value and the waveform correction corresponding table.

Fig. 6 illustrates the FPGA processing flow data processing of inventive method step S5. The waveform 'dislocation' pattern in 10 shown in fig. 5 is subjected to adaptive adjustment to a standard timing waveform according to the waveform adaptive correction lookup table. By taking a sample graph without ' dislocation ' of the standard with count being 6 as a center, the waveform of the FPGA is adaptively adjusted, and the waveform ' dislocation ' in the range of +/-39.0625 ns ' can be corrected. The anti-interference performance and the adaptability of the multi-platform environment are greatly enhanced.

The step S5 specifically includes: s51: and establishing a waveform correction lookup table according to the corresponding relation between the Count value of the dislocation mark Count and the time sequence of the standard waveform. See table 1.

Table 1 waveform correction look-up table

S52: and adaptively adjusting the waveforms of the time CLK and the DATA DATA according to the waveform correction lookup table, and outputting the waveforms to the next stage for DATA sampling processing.

Step S6: CHSI input data acquisition. And sampling and storing data of the data waveform after the self-adaptive adjustment according to the time sequence relation of the clock and the data waveform in the technical standard.

Preferably, fig. 8 shows the FPGA processing flow of the data acquisition of step S6 of the present invention. The step S6 specifically includes: s61: and for standard clock and data waveforms formed after self-adaptive adjustment, delaying the CLK by 3 beats and then acquiring data at the rising edge of the delayed clock of 2 beats according to the time sequence relation of the clock and the data, so as to ensure that the data is at the most middle position of the data bit waveform. S62: and defining a register variable Buff and finishing the storage of the acquired data.

Step S7: and performing CRC check on the received data message. And performing CRC calculation on the data message which finishes CHSI data acquisition and storage, if the data message is correct, sending the data message to the next stage for processing, otherwise, discarding the data packet of the frame and giving an error type indication.

Preferably, the step S7 specifically includes: s71: according to the CRC check polynomial specified in the standard: and X16+ X12+ X5+1, completing CRC check calculation. S72: when the CRC check calculation result is different from the received CRC value and indicates that an error exists, discarding the frame data and sending an identification signal indicating that the CRC check fails.

Step S8: and judging the header and the length of the data message. And judging the header and the length of the data message subjected to the correct CRC check again, and if the header and the length of the data message are correct, sending the data message to the next stage for processing. Otherwise, the frame data packet is discarded, a header or length error type indication is given, and the transmitting end is required to retransmit.

Preferably, the step S8 specifically includes: s81: and according to a data communication protocol agreed with a sender, performing header judgment on the data message subjected to CRC, and discarding corresponding frame data and sending a header undefined identification signal when the data message is judged to have an error. S82: and judging the length of the data message subjected to the header check according to a data communication protocol agreed with the sender, and sending the qualified data message to the next-stage data processing.

Fig. 9 shows the processing flow of steps S7 and S8 in the method of the present invention. For the stored data completed in step S6, step S7 completes CRC check, and step S8 completes judgment of the header and length of the data packet, thereby enhancing the integrity judgment of the data packet, sending the correct packet to the next stage of processing, giving a corresponding error flag for the check error, and requiring retransmission.

The FPGA anti-interference processing method disclosed by the invention improves the reliable transmission capability of CHSI receiving data communication, and solves the problem of bit error rate caused by poor receiving anti-interference capability and incapability of processing burst waveform dislocation and burr interference in real time in the prior art.

According to the CHSI receiving time sequence characteristics and the phenomenon that the waveform is easily interfered, the invention establishes a fault-tolerant mechanism in FPGA data processing, adopts a 'deburring' anti-interference method, adopts high-magnification sampling, synchronous processing of asynchronous communication and real-time detection of waveform dislocation burst positions, realizes self-adaptive waveform adjustment to a standard waveform, ensures correct sampling of data, and simultaneously judges through CRC check, message header information and data length. The correctness of the CHSI for receiving the data message is ensured, and the reliability of data transmission is improved. The invention provides a solution, establishes a fault-tolerant mechanism and effectively solves the problem of unreliable CHSI data transmission.

Example 2

Based on embodiment 1, fig. 2 is a schematic diagram of the timing relationship between the clock CLK and the DATA input by the CHSI in step S1 according to the present invention. The schematic illustrates the corresponding timing relationship between the clock CLK and DATA waveforms without any disturbance, and it can be seen from the figure that the timing width is 6 cycles of 128Mhz from the first falling edge of the clock CLK to the first falling edge of the DATA, indicating that there is DATA input from the outside.

Example 3

On the basis of

embodiments

1 and 2, fig. 3 is a schematic illustration of "glitches" appearing in waveforms of clock CLK and DATA in DATA processing of step S3 of the method of the present invention, the "glitches" appearing in practical engineering applications and the appearing positions are relatively random, fig. 3 is only schematic, but the types of "glitches" generated in the waveforms are only two types, namely "0 to 1" and "1 to 0".

Example 4

Fig. 5 is a sample diagram of the waveform "misalignment" detected in step S4 of the method of the present invention, based on

embodiments

1, 2 and 3. The standard timing correspondence between the clock CLK and DATA waveforms is used as a basis, that is, the first falling edge of the clock to the first falling edge of the DATA waveform is 6 128Mhz clock cycles count equal to 6. The "skew" phenomenon occurring in the actual engineering is exemplified by the case where the data waveform is "left-shifted" by 5 128Mhz clock cycles and "right-shifted" by 5 128Mhz clock cycles with respect to the clock waveform, i.e., the case where the count is 5,4,3,2,1 and the count is 7,8,9,10, 11.

Example 5

On the basis of

embodiments

1, 2, 3 and 4, fig. 7 shows a state division and a corresponding time sequence diagram in the data acquisition process of step S6 according to the present invention. According to the time sequence characteristics, the complete process of data reception can be divided into "idle state", "initial state", "data acquisition state", "stop state" and "idle state". At the time of data acquisition, the CLK waveform was delayed 3 times by 128Mhz, i.e., by 3 beats. And data acquisition is carried out at the rising edge of the delayed 2 nd-beat CLK, and the time is the most middle position of the data waveform, so that the accuracy of data acquisition is ensured.

The foregoing basic embodiments of the invention and their various further alternatives can be freely combined to form multiple embodiments, all of which are contemplated and claimed herein. In the scheme of the invention, each selection example can be combined with any other basic example and selection example at will. Numerous combinations will be known to those skilled in the art.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims

1. An FPGA anti-interference processing method for improving CHSI receiving data reliability is characterized by at least comprising the following steps:

s1: inputting a TTL serial clock CLK and DATA DATA of an original CHSI bus into the FPGA;

s2: synchronous processing of input asynchronous signals by the FPGA;

s3: finishing the waveform burr removal processing of the input data;

the step S3 specifically includes:

s31: the FPGA adopts a 128Mhz clock to synchronously sample clock CLK and DATA DATA signals input by a serial 16Mhz/s and carries out delay processing;

s32: waveform inverse narrow processing, namely delaying the CLK clock and DATA DATA signal waveforms after synchronous processing by 3 128Mhz clock cycles respectively; the generated CLK _ r1, CLK _ r2, CLK _ r 3; AND-OR of DATA _ d1, DATA _ d2, DATA _ d3, respectively;

s33: a waveform stretching process of delaying the CLK clock and DATA signal after the inverse narrowing by 3 cycles of 128Mhz clock, respectively; the generated CLK _ zhai _ r1, CLK _ zhai _ r2, CLK _ zhai _ r3, DATA _ zhai _ d1, DATA _ zhai _ d2 and DATA _ zhai _ d3 are respectively OR-ed;

s34: a waveform re-stretching process of delaying the waveforms of the CLK clock and the DATA signal stretched in step S33 by 3 cycles of 128Mhz clock, respectively; respectively OR the generated CLK _ kuan1_ r1, CLK _ kuan1_ r2, CLK _ kuan1_ r3, DATA _ kuan1_ d1, DATA _ kuan1_ d2 and DATA _ kuan1_ d 3;

s35: performing waveform re-narrowing processing, namely delaying the CLK clock and the DATA signal re-widened in the step S34 by 3 128Mhz clock cycles respectively to realize second restoration of the waveforms of the CLK clock and the DATA signal, and performing phase inversion on CLK _ kuan2_ r1, CLK _ kuan2_ r2, CLK _ kuan2_ r3, DATA _ kuan2_ d1, DATA _ kuan2_ d2 and DATA _ kuan2_ d3 respectively;

s4: completing the detection of the burst dislocation position of the waveform;

s41: performing dislocation mark counting on CHSI clock CLK and DATA DATA input waveforms after deburring, delaying 14 128Mhz clock cycles respectively, and shifting register waveforms, wherein a Count value Count from a first falling edge of CLK to a first falling edge of DATA is specified as 6 128Mhz clocks in a standard;

s42: a rule for a misposition decision is determined,

when the result of the flag Count in step S41 is in the range of 1 to 5 128MHZ, it indicates that the waveform of the DATA deviates from the waveform of the clock CLK by 1 to 5 corresponding cycles of 128 MHZ;

when the flag Count result in step S41 is in the range of 7 to 11 128MHZ, it indicates that the DATA waveform is shifted to the right by 7 to 11 cycles of 128MHZ relative to the clock CLK waveform;

shift register is carried out on the input clock CLK and the DATA DATA respectively for 13 cycles of 128 Mhz;

s5: completing adaptive waveform adjustment;

the step S5 specifically includes:

s51: establishing a waveform correction lookup table according to the corresponding relation between the Count value of the dislocation mark Count and the time sequence of the standard waveform;

s52: according to the waveform correction lookup table, the waveforms of the time CLK and the DATA DATA are adaptively adjusted and output to the next stage for DATA sampling processing;

s6: CHSI input data acquisition;

the step S6 specifically includes:

s61: for standard clock and data waveforms formed after self-adaptive adjustment, delaying CLK for 3 beats according to the time sequence relation of the clock and the data, and acquiring data at the rising edge of the delayed clock of 2 nd beat to ensure the data at the most middle position of the data bit waveform;

s62: defining a register variable Buff and finishing the storage of the acquired data;

s7: CRC checking the received data message;

s8: and judging the header and the length of the data message.

2. The FPGA anti-interference processing method for improving reliability of CHSI received data according to claim 1, wherein the step S1 specifically includes:

s11: detecting whether the states of signal waveforms of a clock CLK and a DATA DATA are changed in real time;

s12: according to the waveform timing of the CHSI input clock CLK and the DATA DATA defined in the standard, in an idle state, the logic levels of the waveforms of the clock CLK and the DATA DATA are both 1 high level, and the detection of the initial state of the signal is completed.

3. The FPGA anti-interference processing method for improving reliability of CHSI received data according to claim 2, wherein the step S2 specifically includes:

s21: calling 3D triggers in the FPGA;

s22: the incoming clock CLK and DATA signals are delayed by 3 beats using a 128Mhz clock, respectively.

4. The FPGA anti-interference processing method for improving reliability of CHSI received data according to claim 1, wherein the step S7 specifically includes:

s71: according to the CRC check polynomial specified in the standard: x16+ X12+ X5+1, and CRC check calculation is completed;

s72: when the CRC check calculation result is different from the received CRC value and indicates that an error exists, discarding the frame data and sending an identification signal indicating that the CRC check fails.

5. The FPGA anti-interference processing method for improving CHSI received data reliability as claimed in claim 4, wherein said step S8 specifically comprises:

s81: according to a data communication protocol agreed with a sender, performing header judgment on a data message subjected to CRC, and when the data message is judged to have errors, discarding corresponding frame data and sending a header undefined identification signal;

s82: and judging the length of the data message subjected to the header check according to a data communication protocol agreed with the sender, and sending the qualified data message to the next-stage data processing.