CN107943739A - A kind of multigroup SPI code signals detection verification method based on FPGA - Google Patents
A kind of multigroup SPI code signals detection verification method based on FPGA Download PDFInfo
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- CN107943739A CN107943739A CN201711262681.9A CN201711262681A CN107943739A CN 107943739 A CN107943739 A CN 107943739A CN 201711262681 A CN201711262681 A CN 201711262681A CN 107943739 A CN107943739 A CN 107943739A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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Abstract
A kind of multigroup SPI code signals detection verification method based on FPGA, using high speed sampling clock by the SPI clocks in every group of SPI signal, SPI data and the step-by-step of SPI latch signals are stored in First Input First Output FIFO respectively, carry out deburring processing, export carrot-free SPI clocks, SPI data and SPI latch signals, in each from low level at the time of high level saltus step of SPI clocks, corresponding SPI data are stored in random access memory ram, in each from low level at the time of high level saltus step of SPI latch signals, the SPI data of lock cache, play back the SPI data of locking, SPI clocks it is each from high level to low transition at the time of, export corresponding back read data, back read data is saved as file, contrasted with initial data.Cause the loss of data the invention avoids the delay that deburring processing procedure produces, solve the problems, such as that multigroup SPI signal interference causes data communication abnormal, can determine the position of corrupt data, design is simple, and versatility is good, is easy to Project Realization.
Description
Technical field
The present invention relates to a kind of multigroup SPI code signals based on FPGA to detect verification method.
Background technology
In data communication system, there are multiple standards in the interface of peripheral electron device, it is known that some interface protocols
There are the problems such as speed is slow, agreement is complicated.Spi bus is a kind of universal serial bus that can overcome disadvantages mentioned above, is preferably met
Data communication is quick, simple, reliable to be required.
According to the operation principle of SPI, SPI interface is designed to that (i.e. SPI expands a kind of universal peripheral ECP Extended Capabilities Port in FPGA
Open up port）, the ECP Extended Capabilities Port is allowed to complete the read functions of data.Or combine flexibility and the spi bus of FPGA programmings
Ease for use, realizes the connection of the SPI interface based on FPGA, to FLASH into line access.
The SPI port design for being mostly based on FPGA is all to be applied to one group of data link to establish and data transfer control
System etc., in the case that multigroup SPI clocks, SPI data and SPI latch signals are carried out at the same time data communication, clock, data
With, there are interference signal, cause data communication to be abnormal on latch signal.
The content of the invention
The present invention provides a kind of multigroup SPI code signals detection verification method based on FPGA, avoids deburring and treats
Journey produce delay and cause the loss of data, solve when multigroup SPI clocks, SPI data and SPI latch signals are carried out at the same time
In the case of data communication, there are interference signal on clock, data and latch signal, the problem of causing data communication abnormal, energy
Enough determine the position of corrupt data, and carry out data re-transmission, design is simple, and versatility is good, is easy to Project Realization.
In order to achieve the above object, the present invention provides a kind of multigroup SPI code signals detection verification method based on FPGA, bag
Containing following steps：
Step S1, using high speed sampling clock by the SPI clocks in every group of SPI signal, SPI data and SPI latch signal step-by-steps
The First Input First Output FIFO being stored in respectively in FPGA；
Step S2, SPI clocks, SPI data and SPI latch signals are sequential read out from First Input First Output FIFO, carries out unhairing
Thorn processing, exports carrot-free SPI clocks, SPI data and SPI latch signals；
Step S3, in the signal of First Input First Output FIFO outputs, in each from low level to high level saltus step of SPI clocks
At the time of, corresponding SPI data are stored in the random access memory ram in FPGA；
Step S4, in each from low level at the time of high level saltus step of SPI latch signals, the SPI data of lock cache；
Step S5, the SPI data locked in replay procedure S4, SPI clocks it is each from high level to low transition when
Carve, export corresponding SPI data, form back read data；
Step S6, back read data is saved as file, is contrasted with initial data, if back read data differs with initial data
Cause, then record the position of corrupt data, and the number of mistake of statistics numeric data code, re-start this data transfer.
The frequency of the high speed sampling clock is 4 times of input SPI clock frequencies.
The deburring processing method comprises the steps of：Binary system judgement is carried out to each signal collected；
When the signal collected is ' 0 ', then the judgement equal to ' 0 ' is continuously carried out to the signal collected, when continuous 4 times
When obtained collection signal is ' 0 ', then it is ' 0 ' by the signal output, otherwise keeps the state of the signal constant；
When the signal collected is ' 1 ', then the judgement equal to ' 1 ' is continuously carried out to the signal collected, when continuous 4 times
When obtained collection signal is ' 1 ', then it is ' 1 ' by the signal output, otherwise keeps the state of the signal constant.
The present invention has the following advantages：
1st, the SPI clocks in every group of SPI signal, SPI data and the step-by-step of SPI latch signals are deposited respectively using high speed sampling clock
Enter First Input First Output FIFO to be cached, caching SPI clocks, SPI data and SPI latch signals can be completed at deburring
Reason, avoids the delay of deburring processing procedure generation and causes the loss of data；
2nd, carrot-free SPI clock signals and SPI data are directly used, each in SPI clocks is jumped from low level to high level
At the time of change, corresponding SPI data are stored in random access memory ram；
3rd, after SPI latch signals are effective, SPI clocks it is each from high level to low transition at the time of, output correspond to
SPI data, back read data is finally saved as file, and initial data is contrasted, complete collection to this group of SPI data and
Verification, can show the position of current data error, the number of programming count wrong data code, and startup re-starts this data
Transmitting procedure.
Brief description of the drawings
Fig. 1 is a kind of flow chart of multigroup SPI code signals detection verification method based on FPGA provided by the invention.
Fig. 2 is multigroup SPI signal collection schematic diagram.
Fig. 3 is each group of SPI signal timing diagram.
Fig. 4 is the simulation result for not taking deburring to handle.
Fig. 5 is the simulation result for taking deburring to handle.
Embodiment
Below according to Fig. 1~Fig. 5, presently preferred embodiments of the present invention is illustrated.
As shown in Figure 1, the present invention provides a kind of multigroup SPI code signals detection verification method based on FPGA, comprising following
Step：
Step S1, using high speed sampling clock by the SPI clocks in every group of SPI signal, SPI data and SPI latch signal step-by-steps
The First Input First Output FIFO being stored in respectively in FPGA；
Step S2, SPI clocks, SPI data and SPI latch signals are sequential read out from First Input First Output FIFO, carries out unhairing
Thorn processing, exports carrot-free SPI clocks, SPI data and SPI latch signals；
Step S3, in the signal of First Input First Output FIFO outputs, in each from low level to high level saltus step of SPI clocks
At the time of, corresponding SPI data are stored in the random access memory ram in FPGA；
Step S4, in each from low level at the time of high level saltus step of SPI latch signals, the SPI data of lock cache；
Step S5, the SPI data locked in replay procedure S4, SPI clocks it is each from high level to low transition when
Carve, export corresponding SPI data, form back read data；
Step S6, back read data is saved as file, is contrasted with initial data, if back read data differs with initial data
Cause, then record the position of corrupt data, and the number of mistake of statistics numeric data code, re-start this data transfer.
It is one embodiment of the present of invention as shown in Fig. 2~Fig. 5, which comprises the steps of：
Step S1, using high speed sampling clock by the SPI clocks in every group of SPI signal, SPI data and SPI latch signal step-by-steps
First Input First Output FIFO is stored in respectively.
The frequency of high speed sampling clock is 4 times of input SPI clock frequencies, 4 times of inputs of frequency of high speed sampling clock
SPI clock frequencies just can meet system processing requirement, and certain sampling rate be able to can simply be obtained more with higher
Redundant data, has an impact the disposal ability of detecting system.Caching SPI clocks, SPI data and SPI latch signals can be to avoid
Loss of data caused by the delay that follow-up deburring processing procedure produces.
As shown in Fig. 2, it is necessary to the SPI signal for carrying out code signal collection and verification has 20 groups in the present embodiment, every group of SPI
Signal includes a bit clock signal, a data signal and a latch signal, and one obtained after treatment returns
Read data back read data.The sequential relationship that 4 tunnel code signals of every group of SPI signal meet is as shown in Figure 3.Wherein, each group of SPI code
Comprising 100 Bits Serial data, therefore clock signal, data-signal, the storage depth of FIFO of latch signal and back read data are
100, storage bit wide is 1bit.Latch signal is always low during numeric data code is sent, under after numeric data code is sent completely
One SPI rising edge clock is changed into high level before reaching, and meets that data establish retention time requirement to SPI clocks, continues
One SPI clock cycle.
Step S2, SPI clocks, SPI data and SPI latch signals are sequential read out from First Input First Output FIFO, is carried out
Deburring is handled, and exports carrot-free SPI clocks, SPI data and SPI latch signals.
The deburring processing is combined with the detection process that a kind of binary system judges and sets burr effective time：Hair
Thorn refers to the spurious signal on signal wire, since multigroup SPI signal is carried out at the same time signal ' 0 ' and ' 1 ' quick upset, mutually
There is interference each other, the result that the signal that input is ' 0 ' originally may obtain after acquisition is ' 1 ', and inputs originally and be
The result that ' 1 ' signal may obtain after acquisition is ' 0 '.Hair is always considerably larger than using the duration of effective data-signal
The characteristics of piercing signal, binary system judgement is carried out to each signal collected, when the signal collected is ' 0 ', is then connected
Continue the judgement carried out to the signal collected equal to ' 0 ', when the collection signal that continuous 4 times obtain is ' 0 ', then believe this
Number output be ' 0 ', otherwise keep the state of the signal constant.Similarly, when the signal collected is ' 1 ', then continuously to adopting
Collect the judgement that obtained signal be equal to ' 1 ', when the collection signal that continuous 4 times obtain is ' 1 ', then by the signal output
For ' 1 ', otherwise keep the state of the signal constant.
SPI clock signals, SPI data-signals and SPI latch signals are all the signals of 1bit, carrot-free SPI clocks letter
Number, SPI data-signals and SPI latch signals can directly carry out sampling processing.
Fig. 4 is the simulation result for not taking deburring to handle.It can be seen from the figure that before not using the present invention, first group
SPI code signals are overturn at random be subject to second group of SPI code signal to be influenced, in first group of SPI clock signal SPI_CLK_1, SPI number
It is believed that there is ghost pulse on number SPI_DATA_1 and SPI latch signals SPI_LATCH_1, fail correctly first group of parsing identification
SPI code information.The SPI latch signals of mistake trigger a numeric data code retaking of a year or grade, while numeric data code retaking of a year or grade SPI_BACK_1 occurs
The data of mistake.
Fig. 5 is the simulation result taken after deburring processing.It can be seen from the figure that after applying the present invention, first group of SPI
Although code signal is overturn at random be subject to second group of SPI code signal is influenced, first group of SPI clock signal, SPI data-signals and
Occur ghost pulse in the input of SPI latch signals, but exported after deburring processing SPI clock signals, SPI data-signals
Do not have ghost pulse with SPI latch signals, correctly parsing identifies first group of SPI code information.Correct SPI latch signals
A numeric data code retaking of a year or grade is triggered, and the numeric data code of retaking of a year or grade is consistent with initial data.
Step S3, in the signal of First Input First Output FIFO outputs, in each from ' 0 ' to ' 1 ' saltus step of SPI clocks
At the moment, corresponding SPI data are stored in RAM.
Step S4, in each from ' 0 ' at the time of ' 1 ' saltus step of SPI latch signals, the SPI data of lock cache；
Step S5, the SPI data of playback locking, in each from ' 1 ' at the time of ' 0 ' saltus step of SPI clocks, output is corresponding
SPI data, form back read data；
Step S6, back read data is saved as file, and initial data is contrasted；
Illustrate, it is assumed that the data of transmission are ten bits " 01011010 ", and the data of step S5 outputs are also ten
Binary number " 01011010 ", then it represents that result is consistent；If data bits and data content have difference, then it represents that it is inconsistent,
If inconsistent, the position of record current data error, the number of mistake of statistics numeric data code, re-starts this data transfer.
So far the collection and verification of one group of SPI data are just completed.Circulation performs step S1~step S6, in each group SPI
After latch signal is effective, playback corresponds to the SPI data of group locking, and back read data is saved as file, and this group of initial data
Contrasted.
The present invention can be acquired and verify to multigroup SPI data at the same time, utilize First Input First Output FIFO to SPI
Deburring processing is carried out to signal while clock signal, SPI data-signals and SPI latch signals are cached, is avoided
Burr processing procedure produce delay and cause the loss of data, the present invention is solved as multigroup SPI clocks, SPI data and SPI
In the case that latch signal is carried out at the same time data communication, there are interference signal on clock, data and latch signal, data are caused to be led to
The problem of letter is abnormal, can determine the position of corrupt data, and carry out data re-transmission, and present invention design is simple, and versatility is good, easily
It is the general of a kind of detection, reception and the verification of the original code signal for being suitable for multigroup SPI data communication systems in Project Realization
Signal processing technology.
Although present disclosure is discussed in detail by above preferred embodiment, but it should be appreciated that above-mentioned
Description is not considered as limitation of the present invention.After those skilled in the art have read the above, for the present invention's
A variety of modifications and substitutions all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (3)
1. a kind of multigroup SPI code signals detection verification method based on FPGA, it is characterised in that comprise the steps of：
Step S1, using high speed sampling clock by the SPI clocks in every group of SPI signal, SPI data and SPI latch signal step-by-steps
The First Input First Output FIFO being stored in respectively in FPGA；
Step S2, SPI clocks, SPI data and SPI latch signals are sequential read out from First Input First Output FIFO, carries out unhairing
Thorn processing, exports carrot-free SPI clocks, SPI data and SPI latch signals；
Step S3, in the signal of First Input First Output FIFO outputs, in each from low level to high level saltus step of SPI clocks
At the time of, corresponding SPI data are stored in the random access memory ram in FPGA；
Step S4, in each from low level at the time of high level saltus step of SPI latch signals, the SPI data of lock cache；
Step S5, the SPI data locked in replay procedure S4, SPI clocks it is each from high level to low transition when
Carve, export corresponding SPI data, form back read data；
Step S6, back read data is saved as file, is contrasted with initial data, if back read data differs with initial data
Cause, then record the position of corrupt data, and the number of mistake of statistics numeric data code, re-start this data transfer.
2. multigroup SPI code signals detection verification method based on FPGA as claimed in claim 1, it is characterised in that described
The frequency of high speed sampling clock is 4 times of input SPI clock frequencies.
3. multigroup SPI code signals detection verification method based on FPGA as claimed in claim 1, it is characterised in that described
Deburring processing method comprises the steps of：Binary system judgement is carried out to each signal collected；
When the signal collected is ' 0 ', then the judgement equal to ' 0 ' is continuously carried out to the signal collected, when continuous 4 times
When obtained collection signal is ' 0 ', then it is ' 0 ' by the signal output, otherwise keeps the state of the signal constant；
When the signal collected is ' 1 ', then the judgement equal to ' 1 ' is continuously carried out to the signal collected, when continuous 4 times
When obtained collection signal is ' 1 ', then it is ' 1 ' by the signal output, otherwise keeps the state of the signal constant.
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| CN201711262681.9A CN107943739B (en) | 2017-12-04 | 2017-12-04 | FPGA-based multi-group SPI code signal detection and verification method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020150954A1 (en) * | 2019-01-24 | 2020-07-30 | 深圳市汇顶科技股份有限公司 | Method and apparatus for spi-based asynchronous handling of events, and storage medium |
| CN112073152A (en) * | 2020-09-15 | 2020-12-11 | 四川九洲空管科技有限责任公司 | FPGA anti-interference processing method for improving reliability of CHSI received data |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040039866A1 (en) * | 2001-03-16 | 2004-02-26 | Hugo Cheung | Serial peripheral interface with high performance buffering scheme |
| CN105528325A (en) * | 2014-09-29 | 2016-04-27 | 安凯(广州)微电子技术有限公司 | Protection method and system for high-speed transmission through standard SPI protocol |
| CN205263808U (en) * | 2015-12-28 | 2016-05-25 | 杭州士兰控股有限公司 | SPI slave unit and SPI communication system |
-
2017
- 2017-12-04 CN CN201711262681.9A patent/CN107943739B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040039866A1 (en) * | 2001-03-16 | 2004-02-26 | Hugo Cheung | Serial peripheral interface with high performance buffering scheme |
| CN105528325A (en) * | 2014-09-29 | 2016-04-27 | 安凯(广州)微电子技术有限公司 | Protection method and system for high-speed transmission through standard SPI protocol |
| CN205263808U (en) * | 2015-12-28 | 2016-05-25 | 杭州士兰控股有限公司 | SPI slave unit and SPI communication system |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020150954A1 (en) * | 2019-01-24 | 2020-07-30 | 深圳市汇顶科技股份有限公司 | Method and apparatus for spi-based asynchronous handling of events, and storage medium |
| CN112073152A (en) * | 2020-09-15 | 2020-12-11 | 四川九洲空管科技有限责任公司 | FPGA anti-interference processing method for improving reliability of CHSI received data |
| CN112073152B (en) * | 2020-09-15 | 2022-06-24 | 四川九洲空管科技有限责任公司 | FPGA anti-interference processing method for improving reliability of CHSI received data |
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