WO2020150954A1

WO2020150954A1 - Method and apparatus for spi-based asynchronous handling of events, and storage medium

Info

Publication number: WO2020150954A1
Application number: PCT/CN2019/072927
Authority: WO
Inventors: 李昆
Original assignee: 深圳市汇顶科技股份有限公司
Priority date: 2019-01-24
Filing date: 2019-01-24
Publication date: 2020-07-30
Also published as: CN109891400A

Abstract

Provided by the present application are a method and apparatus for the SPI-based asynchronous handling of events, and a storage medium. The method comprises: acquiring a level transition state of a chip select signal from a master device by means of a serial peripheral interface (SPI); according to the level transition state of the chip select signal, determining whether there is an SPI data transmission event; and if there is an SPI data transmission event and it is determined that SPI data transmission is completed, then initiating a hardware interrupt to notify a processor in a slave device of handling the SPI data transmission event. The described method not only implements the monitoring of SPI data transmission events, but also conserves running resources of the processor.

Description

Method, device and storage medium for asynchronously processing events based on SPI

Technical field

This application relates to the field of communication technology, and in particular to a method, device and storage medium for asynchronously processing events based on SPI.

Background technique

The serial peripheral interface (Serial Peripheral Interface, SPI) protocol is a high-speed, full-duplex, and synchronous communication bus protocol. Since the SPI protocol is full-duplex and has no defined speed limit, its transmission speed can usually reach or exceed 10 megabits per second (Million bits per second, Mbps), which is very suitable for high-speed data transmission. The master device (master) sends SPI data transmission events to the slave device (slave) to control the slave device. The master device is connected to the slave device (slave) through the master input data line (master input slave output, MISO) and the slave device output data line (master output slave input, MOSI), and is connected to the slave device (slave) through MISO and MOSI Perform SPI data transfer. After the slave device receives the SPI data transmission event sent by the master device, the processor connected to the slave device or the processor in the slave device needs to process the SPI data transmission event sent by the master device.

In the prior art, for the problem of how to determine whether the master device sends SPI data transmission events to the slave device, a processor is usually used, such as a central processing unit (CPU), a microcontroller unit (MCU), etc. , Detect whether the slave device has received the SPI data transmission event sent by the master device by means of circular query.

However, in the prior art, the processor in the slave device is used to detect whether the slave device has received the SPI data transmission event sent by the master device in a circular query, and then the SPI data transmission event is processed, which will cause problems in the slave device. Waste of processor operating resources.

Summary of the invention

This application provides a method, device and storage medium for asynchronously processing events based on SPI, which not only realizes the detection of SPI data transmission events sent by the master device, but also saves processor operating resources.

In the first aspect, this application provides a method for asynchronously processing events based on SPI, including:

Obtain the level transition status of the chip select signal from the master device through the serial peripheral interface SPI; determine whether there is an SPI data transmission event according to the level transition status of the chip select signal; if there is an SPI data transmission event, determine the SPI When the data transmission is completed, a hardware interrupt is initiated to notify the processor in the slave device to process the SPI data transmission event.

In this solution, the level transition status of the chip select signal is obtained, and the level transition status of the chip select signal is used to determine whether there is an SPI data transmission event, and after the completion of the SPI data transmission, a hardware interrupt is initiated to notify the slave The processor in the device processes the SPI data transmission event, which not only realizes the monitoring of the SPI data transmission event, but also saves the operating resources of the processor in the slave device.

Optionally, determine whether there is an SPI data transmission event according to the level transition state of the chip select signal, including:

If the chip select signal has a falling edge transition and a rising edge transition after the falling edge transition, it is determined that there is an SPI data transmission event.

In this solution, through the falling edge transition and the rising edge transition of the chip select signal, the judgment of the SPI data transmission event is realized.

If the chip select signal has a rising edge transition and a falling edge transition after the rising edge transition, it is determined that there is an SPI data transmission event.

In this solution, the chip select signal's rising edge and falling edge jumps are used to determine the SPI data transmission event.

Optionally, the SPI asynchronous event processing method provided in this application also includes:

If the chip select signal has a falling edge transition, the slave device allocates storage space for the SPI data.

In this solution, when the chip select signal has a falling edge transition, storage space is allocated to prepare to receive SPI data to avoid the situation that SPI data cannot be received normally. Optionally, the SPI asynchronous event processing method provided in this application also includes:

If the chip select signal has a rising edge transition, the slave device allocates storage space for the SPI data.

In this solution, when the chip select signal has a rising edge transition, storage space is allocated to prepare to receive SPI data to avoid the situation that SPI data cannot be received normally.

The following will introduce devices, chips, equipment, storage media, and computer program products for asynchronously processing events based on SPI. The effects can be referred to the effects of the method section, which will not be repeated below.

In the second aspect, this application provides a device for asynchronously processing events based on SPI, including:

The acquisition module is used to acquire the level transition status of the chip select signal from the master device through the serial peripheral interface SPI. The judgment module is used to judge whether there is an SPI data transmission event according to the level transition state of the chip select signal.

The processing module is used to initiate a hardware interrupt to notify the processor in the slave device to process the SPI data transmission event if there is an SPI data transmission event and it is determined that the SPI data transmission is completed.

Optionally, the judgment module includes:

The first judging sub-module is used for judging that there is an SPI data transmission event if there is a falling edge transition in the chip select signal, and there is a rising edge transition after the falling edge transition.

Optionally, the judgment module includes:

The second judgment sub-module is used for judging that there is an SPI data transmission event if the chip select signal has a rising edge transition and there is a falling edge transition after the rising edge transition.

Optionally, the SPI-based asynchronous event processing device provided in this application also includes:

The first allocation module is used to allocate storage space to the SPI data in the slave device if the chip select signal has a falling edge transition.

The second allocation module is used to allocate storage space to the SPI data in the slave device if the chip select signal has a rising edge transition.

In the third aspect, the present application provides a chip for executing the SPI-based asynchronous event processing method as in the first aspect and the optional methods of the first aspect.

In a fourth aspect, this application provides a device including a processor and a chip,

The chip is used for:

The processor is used for:

Respond to hardware interrupts and handle SPI data transmission events.

Optionally, the chip of the device provided in this application is also used for

If the chip select signal has a falling edge transition, the storage space is allocated to the SPI data in the slave device.

Optionally, the chip of the device provided in this application is also used for:

If the chip select signal has a rising edge transition, the storage space is allocated to the SPI data in the slave device. In a fifth aspect, this application provides a computer storage medium. The storage medium includes computer instructions. When the instructions are executed by a computer, the computer realizes the SPI-based asynchronous event processing method as in the first aspect or an optional manner in the first aspect.

In a sixth aspect, the present application provides a computer program product, including computer instructions, which when executed by a computer, enable the computer to implement the first aspect or the SPI-based asynchronous event processing method in an optional manner in the first aspect.

This application provides a method, device, and storage medium for asynchronously processing events based on SPI. The method includes: obtaining the level transition state of a chip select signal from a master device through an SPI interface; and according to the level transition state of the chip select signal, Determine whether there is an SPI data transmission event, if there is an SPI data transmission event, and determine that the SPI data transmission is complete, initiate a hardware interrupt to notify the processor in the slave device to process the SPI data transmission event. Since the level jump state of the chip select signal is obtained, and the level jump state of the chip select signal is used to determine whether there is an SPI data transmission event, and after the completion of the SPI data transmission, a hardware interrupt is initiated to notify the processing in the slave device The processor processes SPI data transmission events, which not only realizes the monitoring of SPI data transmission events, but also saves processor operating resources in the slave device.

Description of the drawings

In order to more clearly describe the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description These are some embodiments of the present application. For those of ordinary skill in the art, other drawings may be obtained based on these drawings without creative labor.

Figure 1 is a schematic application scenario diagram of the technical solution of this application;

FIG. 2 is a flowchart of a method for asynchronously processing events based on SPI according to an embodiment of the present application;

3 is a schematic diagram of processing SPI data processing events provided by an embodiment of the present application;

4 is a schematic structural diagram of an SPI-based asynchronous event processing apparatus provided by an embodiment of the present application;

5 is a schematic structural diagram of an SPI-based asynchronous event processing apparatus provided by another embodiment of the present application;

6 is a schematic structural diagram of an SPI-based asynchronous event processing apparatus provided by another embodiment of the present application;

Fig. 7 is a schematic diagram of a terminal device provided by an embodiment of the present application.

detailed description

In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments It is a part of the embodiments of this application, but not all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of this application.

The terms "first", "second", "third", "fourth", etc. (if any) in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and do not have to be used To describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein, for example, can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations of them are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to the clearly listed Those steps or units may include other steps or units that are not clearly listed or are inherent to these processes, methods, products, or equipment.

The SPI protocol is a high-speed, full-duplex, and synchronous communication bus protocol. Since the SPI protocol is full-duplex and has no defined speed limit, its transmission speed can usually reach or exceed 10Mbps, which is very suitable for high-speed data transmission. The master device sends SPI data transmission events to the slave device to control the slave device. The master device is connected to the slave device through MISO and MOSI, and performs SPI data transfer through MISO and MOSI. After the slave device receives the SPI data transmission event sent by the master device, the processor in the slave device needs to process the SPI data transmission event sent by the master device. However, in the prior art, detecting whether the slave device has received the SPI data transmission event sent by the master device through the processor in the slave device in a circular query manner will cause a waste of processor operating resources. In order to solve the above problems, this application provides a method, device and storage medium for asynchronously processing events based on SPI.

Hereinafter, an exemplary application scenario of the embodiment of the present application will be introduced.

Fig. 1 is an exemplary application scenario diagram of the technical solution of the present application. As shown in Fig. 1, the SPI protocol works in a master-slave mode. This working mode involves one or more master devices 11 and one or more slave devices 12. Figure 1 takes a master device 11 and a slave device 12 as an example for introduction. The master device can be a chip, CPU, MCU, Field-Programmable Gate Array (FPGA), or terminal device, etc. The device can be a chip, MCU, CPU, FPGA or terminal device, etc. The terminal device can be a personal computer (PC) or a mobile terminal, etc. The mobile terminal can also be referred to as User Equipment (UE), Access terminal, user unit, user station, mobile station, mobile station, user terminal, terminal, wireless communication device, user agent or user device. The mobile terminal can be a smart phone, a cellular phone, a cordless phone, a tablet computer, a personal digital assistant (PDA) device, a handheld device with wireless communication function or other processing devices connected to a wireless modem, a vehicle-mounted device, Wearable devices, etc. In the embodiment of the present invention, the terminal device has an SPI communication interface.

For data transmission between the master device 11 and the slave device 12, 4 data lines are usually required. They are serial clock (Serial Clock, SCLK) signal lines for synchronous data transmission. The SCLK signal line is only controlled by the master device. The slave device cannot control the SCLK signal line. The master device controls the communication through the control of the SCLK signal line; the Chip Select (CS) line is used by the master device to output chip select signals to the slave device, only the chip select signal When it is a predetermined enable signal, the operation of the slave device by the master device is effective; MOSI data line and MISO data line, because the MOSI data line and MISO data line are independent of each other, the input and output of SPI data are independent, so it is allowed Complete data input and output at the same time. When the master device 11 transmits data to the slave device 12, the master device 11 will send a CS signal to the slave device 12, and when the master device 11 sends SPI data to the slave device 12, there will be a level jump of the CS signal.

Based on the above application scenarios, the technical solution of this application is described in detail below:

Fig. 2 is a flowchart of a method for asynchronously processing events based on SPI according to an embodiment of the present application, where the method can be executed by an SPI asynchronous event processing device, which can be implemented by software and/or hardware, for example: The device may be part or all of the above-mentioned slave device. The following describes the method of asynchronously processing events based on SPI with the chip in the above-mentioned slave device as the execution body. As shown in FIG. 2, the method includes the following steps:

Step S101: The chip obtains the level transition state of the chip selection signal from the master device through the SPI.

When the master device transmits SPI data to the slave device, the master device sends a chip select signal to the slave device through the chip select line. The chip select signal is a high-level signal or a low-level signal, and the chip select signal can be selected by setting Active high or active low, where active high means that when the chip select signal is a high signal, the master device can transmit SPI data to the slave device through MOSI, and active low means chip select signal When it is a low level signal, the master device can transmit SPI data to the slave device through MOSI.

In a possible implementation, if the chip select signal is set to be active low, the master device can successfully send SPI data to the slave device only when the chip select signal is a low-level signal. When the slave device sends SPI data, if the chip select signal is a high level signal, the master device cannot successfully send SPI data to the slave device. Therefore, when the master device is ready to send SPI data to the slave device, the chip select signal sent by the master device through the chip select line jumps from high to low level. When the master device sends SPI data to the slave device, the master device The chip select signal sent through the chip select line changes from low level to high level.

In another possible implementation, if the chip select signal is set to be active at high level, the master device can successfully send SPI data to the slave device only when the chip select signal is at high level. When the device sends SPI data, if the chip select signal is a low-level signal, the master device cannot successfully send SPI data to the slave device. Therefore, when the master device is preparing to send SPI data to the slave device, the chip select signal sent by the master device through the chip select line jumps from low to high level. When the master device sends SPI data to the slave device, the master device The chip select signal sent through the chip select line changes from high level to low level.

The embodiment of the present invention does not limit the manner of obtaining the level transition state of the chip select signal, as long as the level transition state of the chip select signal can be accurately obtained.

Step S102: The chip judges whether there is an SPI data transmission event according to the level jump state of the chip selection signal.

For ease of description, the following is an example of how the chip select signal is active low or the chip select signal is active high to describe how to determine whether there is an SPI data transmission event according to the level transition state of the chip select signal.

First, take the chip select signal as low-level active as an example. When the chip select signal is a low-level signal, and the master device sends SPI data to the slave device, there may be an SPI data transmission event. When the chip select signal is high-level When signal, the master device cannot send SPI data to the slave device, so there is no SPI data transmission event.

When the master device is ready to send SPI data to the slave device, the chip select signal sent by the master device through the chip select line jumps from high to low. When the master device sends SPI data to the slave device, the master device passes the chip select The chip selection signal sent by the line selection jumps from low level to high level. In order to determine whether there is an SPI data transmission event based on the level transition state of the chip select signal, in a possible implementation manner, determine whether there is an SPI data transmission event based on the level transition state of the chip select signal, including:

Falling edge transition is the chip select signal changes from high to low level, and the rising edge jumps to chip select signal from low to high. When the SPI data transmission starts between the master device and the slave device, the master device changes the chip select signal from a high-level signal to a low-level signal. At this time, the chip select signal has a falling edge transition. When the device communication ends, the master device changes the chip select signal from a low-level signal to a high-level signal. At this time, the chip select signal has a rising edge jump. Therefore, if the chip select signal has a falling edge jump, and it is falling If there is a rising edge transition after the edge transition, it is determined that there is an SPI data transmission event.

In this solution, by obtaining the level transition state of the chip select signal, and judging whether there is an SPI data transmission event based on the level transition state of the chip select signal, not only the monitoring of the SPI data transmission event is realized, but also the saving The operating resources of the processor.

In order to ensure that the slave device can successfully receive the SPI data transmission event when the master device sends the SPI data transmission event to the slave device, optionally, there is a falling edge transition through the chip select signal, and there is a rising edge after the falling edge transition Jump, in the process of judging that there is an SPI data transmission event, it can also include:

When the chip select signal has a falling edge transition, it means that the master device is ready to send SPI data to the slave device. In a possible implementation, when the chip select signal has a falling edge transition within a preset time, the master device sends For SPI data to the slave device, the embodiment of the present invention does not limit the preset time. In order to ensure the smooth reception of SPI data, the slave device can allocate storage space to prepare to receive SPI data.

In this solution, when the chip select signal has a falling edge transition, storage space is allocated to prepare to receive SPI data to avoid the situation that SPI data cannot be received normally.

In addition, taking the chip select signal as high level active as an example, when the chip select signal is a high level signal, the master device sends SPI data to the slave device, there may be an SPI data transmission event, when the chip select signal is low level When signal, the master device cannot send SPI data to the slave device, so there is no SPI data transmission event.

When the master device is preparing to send SPI data to the slave device, the chip select signal sent by the master device through the chip select line changes from low level to high level. When the master device sends SPI data to the slave device, the master device passes the chip select The chip selection signal sent by the line selection jumps from high level to low level. In order to determine whether there is an SPI data transmission event based on the level transition state of the chip select signal, in a possible implementation manner, determine whether there is an SPI data transmission event based on the level transition state of the chip select signal, including:

When the SPI data transmission starts between the master device and the slave device, the master device changes the chip select signal from a low-level signal to a high-level signal. At this time, the chip select signal has a rising edge transition. When the device communication ends, the master device changes the chip select signal from a high-level signal to a low-level signal. At this time, the chip select signal has a falling edge transition. Therefore, if the chip select signal has a rising edge transition and is rising If there is a falling edge transition after the edge transition, it is determined that there is an SPI data transmission event.

In order to ensure that the slave device can successfully receive the SPI data transmission event when the master device sends the SPI data transmission event to the slave device, optionally, there is a rising edge transition through the chip select signal, and there is a falling edge after the rising edge transition Jump, in the process of judging that there is an SPI data transmission event, it can also include:

If the chip select signal has a rising edge transition, the storage space is allocated to the SPI data in the slave device.

When the chip select signal has a rising edge transition, it means that the master device is ready to send SPI data to the slave device. In a possible implementation, when the chip select signal has a rising edge transition within a preset time, the master device sends For SPI data to the slave device, the embodiment of the present invention does not limit the preset time. In order to ensure the smooth reception of SPI data, the slave device can allocate storage space to prepare to receive SPI data.

Step S103: If there is an SPI data transmission event, and it is determined that the SPI data transmission is completed, a hardware interrupt is initiated to notify the processor in the slave device to process the SPI data transmission event.

In the embodiment where the chip select signal is active at low level, by judging that the chip select signal has a falling edge transition, and there is a rising edge transition after the falling edge transition, it is determined that there is an SPI data transmission event, and the SPI data transmission Complete; In the embodiment where the chip select signal is active at high level, by judging that the chip select signal has a rising edge transition, and there is a falling edge transition after the rising edge transition, it is determined that there is an SPI data transmission event, and SPI The data transfer is complete. If it is judged that there is an SPI data transmission event and it is determined that the SPI data transmission is complete, the terminal device can initiate a hardware interrupt to notify the processor to process the SPI data transmission event, where the hardware interrupt is an asynchronous signal used to interrupt the processor being processed. Tasks, and notify the processor to process SPI data transmission events; hardware interrupts are asynchronous interrupts, which are interrupts generated by electrical signals generated by the processor’s external devices. The timing of the hardware interrupts is unpredictable, as long as there are SPI data transmission events and determine After SPI data transmission is complete, a hardware interrupt can be initiated. By initiating a hardware interrupt to notify the processor to process the SPI data transmission event when the SPI data transmission is determined to be completed, the processor's time can be effectively saved.

Figure 3 is a schematic diagram of processing SPI data processing events provided by an embodiment of the present application. Taking the slave device as a terminal device, and the terminal device includes a chip and a processor as an example, the process of processing SPI data processing events is introduced, as shown in Figure 3 As shown, the processor is sequentially processing subtask 1 and subtask 2 in the slave device. The subtasks represent other tasks in the terminal device except for the SPI data transmission event. When the terminal device passes the level jump state according to the chip select signal , It is judged that there is an SPI data transmission event, and when the SPI data transmission is determined to be completed, a hardware interrupt is initiated to notify the processor to process the SPI data transmission event. The processor responds to the hardware terminal and processes the SPI data transmission event. After the processing is completed, it then processes the terminal For subtask 3, subtask 4, etc. in the device, when the processor is processing the subtask, as long as the terminal device determines that there is an SPI data transmission event according to the level transition state of the chip select signal, and determines the SPI data When the transmission is completed, a hardware interrupt can be initiated to notify the processor to process the SPI data transmission event. The processor responds to the hardware terminal and processes the SPI data transmission event. After the processing is completed, it then processes other subtasks.

In this solution, after determining the completion of the SPI data transmission, a hardware interrupt is initiated to notify the processor to process the SPI data transmission event, which realizes the timely processing of the SPI data transmission event and saves the processor's operating resources.

The following will introduce devices, chips, equipment, storage media, and computer program products based on SPI asynchronous processing events. The effects can be referred to the effects of the method part, which will not be repeated below.

Figure 4 is a schematic structural diagram of a device for asynchronous processing of events based on SPI according to an embodiment of the present application. The device can be implemented by software and/or hardware. For example, the device can be part or all of a slave device. The device is a chip in a slave device as an example for description. As shown in FIG. 4, the SPI-based asynchronous event processing device provided in the embodiment of the present application may include:

The obtaining module 51 is used to obtain the level transition state of the chip select signal from the master device through the SPI.

The judging module 52 is used for judging whether there is an SPI data transmission event according to the level transition state of the chip select signal.

The processing module 53 is configured to initiate a hardware interrupt to notify the processor in the slave device to process the SPI data transmission event if there is an SPI data transmission event and it is determined that the SPI data transmission is completed.

Optionally, FIG. 5 is a schematic structural diagram of a device for asynchronously processing events based on SPI according to another embodiment of the present application. The device can be implemented by software and/or hardware. For example, the device can be part of the slave device described above. Or all, the following description takes the device as a chip in a slave device as an example. As shown in FIG. 5, the device judgment module 52 based on SPI asynchronous processing events provided by the embodiment of the present application may include:

The first judging sub-module 521 is configured to: if the chip select signal has a falling edge transition and there is a rising edge transition after the falling edge transition, then there is an SPI data transmission event.

Optionally, as shown in FIG. 5, the SPI-based asynchronous event processing apparatus provided in the embodiment of the present application may further include:

The first allocation module 54 is configured to allocate storage space to the SPI data in the slave device if the chip select signal has a falling edge transition.

Optionally, FIG. 6 is a schematic structural diagram of a device for asynchronously processing events based on SPI according to another embodiment of the present application. The device can be implemented by software and/or hardware. For example, the device can be part of the slave device described above. Or all, the following description takes the device as a chip in a slave device as an example. As shown in FIG. 6, the device judgment module 52 based on SPI asynchronous processing events provided in the embodiment of the present application may include:

The second judging sub-module 522 is used for judging that there is an SPI data transmission event if there is a rising edge transition in the chip select signal, and there is a falling edge transition after the rising edge transition.

Optionally, as shown in Figure 6, the SPI-based asynchronous event processing device provided in this application may also include:

The second allocation module 55 is configured to allocate storage space to the SPI data in the slave device if the chip select signal has a rising edge transition.

This application provides a chip for executing the above-mentioned SPI-based asynchronous event processing method. For the content and effect, please refer to the method embodiment.

This application provides a terminal device. FIG. 7 is a schematic diagram of a terminal device provided by an embodiment of this application. As shown in FIG. 7, the terminal device provided by this application includes a processor 71 and a chip 72.

The chip 72 is used to: obtain the level transition status of the chip select signal from the master device through SPI; determine whether there is an SPI data transmission event according to the level transition status of the chip select signal; if there is an SPI data transmission event, determine the SPI When the data transmission is completed, a hardware interrupt is initiated to notify the processor 71 in the slave device to process the SPI data transmission event.

The processor 71 is used to respond to hardware interrupts and process SPI data transmission events.

Optionally, the chip 72 of the device provided in this application is also used for

Optionally, the chip 72 of the device provided in this application is also used for:

If the chip select signal has a rising edge transition, the storage space is allocated to the SPI data in the slave device. The present application provides a computer storage medium. The storage medium includes computer instructions. When the instructions are executed by a computer, the computer realizes the above-mentioned SPI-based asynchronous event processing method. Please refer to the method embodiments for its content and effects.

This application provides a computer program product, including computer instructions. When the instructions are executed by a computer, the computer realizes the above-mentioned SPI-based asynchronous processing event method. For the content and effects, please refer to the method embodiments.

A person of ordinary skill in the art can understand that all or part of the steps in the foregoing method embodiments can be implemented by a program instructing relevant hardware. The aforementioned program can be stored in a computer readable storage medium. When the program is executed, it executes the steps including the foregoing method embodiments; and the foregoing storage medium includes: ROM, RAM, magnetic disk, or optical disk and other media that can store program codes.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand: The technical solutions recorded in the foregoing embodiments can still be modified, or some or all of the technical features can be equivalently replaced; these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the embodiments of the present invention range.

Claims

A method for processing events asynchronously based on SPI, which is characterized in that it includes:

Obtain the level transition status of the chip select signal from the master device through the serial peripheral interface SPI;

Determine whether there is an SPI data transmission event according to the level transition state of the chip select signal;

If there is the SPI data transmission event, and it is determined that the SPI data transmission is completed, a hardware interrupt is initiated to notify the processor in the slave device to process the SPI data transmission event.
The method according to claim 1, wherein the judging whether there is an SPI data transmission event according to the level transition state of the chip select signal comprises:

If the chip select signal has a falling edge transition, and there is a rising edge transition after the falling edge transition, it is determined that the SPI data transmission event exists.
The method according to claim 1, wherein the judging whether there is an SPI data transmission event according to the level transition state of the chip select signal comprises:

If the chip select signal has a rising edge transition, and there is a falling edge transition after the rising edge transition, it is determined that the SPI data transmission event exists.
The method according to claim 2, characterized by comprising:

If the chip select signal has the falling edge transition, the slave device allocates storage space for the SPI data.
The method according to claim 3, characterized by comprising:

If the chip select signal has the rising edge transition, the storage space is allocated to the SPI data in the slave device.
A device for processing events asynchronously based on SPI is characterized in that it comprises:

The acquisition module is used to acquire the level transition status of the chip select signal from the master device through the serial peripheral interface SPI;

The judging module is used to judge whether there is an SPI data transmission event according to the level transition state of the chip select signal;

The processing module is configured to, if there is the SPI data transmission event and it is determined that the SPI data transmission is completed, initiate a hardware interrupt to notify the processor in the slave device to process the SPI data transmission event.
The device according to claim 6, wherein the judgment module comprises:

The first judging sub-module is used for judging that the SPI data transmission event exists if the chip select signal has a falling edge transition and there is a rising edge transition after the falling edge transition.
The device according to claim 6, wherein the judgment module comprises:

The second judging sub-module is used for judging that the SPI data transmission event exists if the chip select signal has a rising edge transition and there is a falling edge transition after the rising edge transition.
The device according to claim 7, further comprising:

The first allocation module is configured to allocate storage space to the SPI data in the slave device if the falling edge transition of the chip select signal occurs.
The device according to claim 8, further comprising:

The second allocation module is configured to allocate storage space to the SPI data in the slave device if the rising edge transition of the chip select signal occurs.
A chip, characterized by being used to execute the method according to any one of claims 1-5.
A slave device, which is characterized by comprising: a processor and a chip,

The chip is used for:

Obtain the level transition status of the chip select signal from the master device through the serial peripheral interface SPI;

Determine whether there is an SPI data transmission event according to the level transition state of the chip select signal;

If there is the SPI data transmission event, and it is determined that the SPI data transmission is complete, initiate a hardware interrupt to notify the processor in the slave device to process the SPI data transmission event;

The processor is used for:

Respond to the hardware interrupt and process the SPI data transmission event.
The device according to claim 12, wherein the judging whether there is an SPI data transmission event according to the level transition state of the chip select signal comprises:

If the chip select signal has a falling edge transition, and there is a rising edge transition after the falling edge transition, it is determined that the SPI data transmission event exists.
The device according to claim 12, wherein the judging whether there is an SPI data transmission event according to the level transition state of the chip select signal comprises:

If the chip select signal has a rising edge transition, and there is a falling edge transition after the rising edge transition, it is determined that the SPI data transmission event exists.
The device according to claim 13, wherein the chip is further used for:

If the chip select signal has the falling edge transition, the SPI data is allocated storage space in the slave device.
The device according to claim 14, wherein the chip is further used for:

If the chip select signal has the rising edge transition, the storage space is allocated to the SPI data in the slave device.
A computer storage medium, characterized in that the storage medium includes computer instructions, and when the instructions are executed by a computer, the computer realizes the SPI-based asynchronous method according to any one of claims 1-5. The method of handling the event.