CN102117261A - Communication method between inner processors of chip - Google Patents
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- CN102117261A CN102117261A CN2009102508328A CN200910250832A CN102117261A CN 102117261 A CN102117261 A CN 102117261A CN 2009102508328 A CN2009102508328 A CN 2009102508328A CN 200910250832 A CN200910250832 A CN 200910250832A CN 102117261 A CN102117261 A CN 102117261A
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Abstract
The invention discloses a communication method between inner processors of a chip. As the communication between the processors is realized by a shared data region formed by a plurality of data storage blocks, each shared data region is provided with a read pointer, a write pointer and an interrupt resource, wherein a transmitting data processor can write data in an idle data storage block of the shared data region, modifies the write pointer to direct at the next idle data storage block, and transmits interrupts to inform a receiving data processor; and the receiving data processor responds to the interrupts, processes data in unprocessed data storage blocks in the shared data region according to instructions of the read pointer and the write pointer, modifies the read pointer and finishes the data receiving. The technical scheme of the invention can realize the data communication between two processors by utilizing a pair of interrupts, reduces the occupancy of interrupt resources in a system, and avoids delay data processing or data loss caused by coverage or loss of the interrupts.
Description
Technical field
The present invention relates to a kind of communication means between the chip internal processor.
Background technology
Development along with chip technology; at single chip internal a plurality of processors being set has obtained using widely in present chip technology to move different application software respectively; for example; in the baseband chip of portable terminal; usually can comprise an arm processor and a plurality of dsp processor; wherein, arm processor is used for operation system, application layer software, protocol stack sofeware etc., and dsp processor is used to move physical layer software.
Usually need interaction data between the different application software, if a plurality of application software operate in respectively on the different processors, realize that the data interaction between them just needs the communication between the different processor of realization, baseband chip with portable terminal is an example, need to carry out frequent data interaction between protocol stack and the Physical layer, and because protocol stack generally operates on the arm processor, and physical layer software generally operates on the dsp processor, therefore, in fact protocol stack and data interaction between the Physical layer depend on communicating by letter between ARM and the DSP.
Communication between the existing techniques in realizing chip internal different processor adopts the mode of sharing data area to realize usually:
1, needing that the sharing data area that a plurality of DSB data store block are formed is set between the processor of interaction data;
2, distribute an interrupt resources for each DSB data store block;
3, the processor of transmission data writes data the DSB data store block of a free time;
4, the processor of transmission data sends the pairing interruption of this DSB data store block to the processor that receives data;
5, the processor response of reception data sends the interruption of the processor transmission of data;
6, the processor processing of reception data is interrupted the data in the corresponding DSB data store block;
There are following 2 problems in the implementation method of prior art:
1, interactive data quantity is very big between processor, in the time of very intensive, the also corresponding meeting of DSB data store block that needs is a lot, and above-mentioned implementation method is to distribute an interrupt resources at each DSB data store block, like this, can take a lot of system break resources, cause the waste of system break resource.
2, when the data throughout of inter-processor communication is very big, system break can be very frequent, like this, the situation that may exist interruption to lose, cover, above-mentioned implementation method may cause the data in some or a plurality of DSB data store block in time not to be received in this case even can't received problem.
For example, with the HSPA business in the TDSCDMA system, data throughout was at 15kbits in the arm processor of the baseband chip in the data service process and the data interaction extreme case data transmission between the dsp processor required 5 milliseconds, the primitives interoperation number of times limit is 6 times between per 5 milliseconds, two-way each 3 times.This intensive primitives interoperation causes the situation of interrupting covering, losing possibly, thereby causes primitive can not in time be received even lose primitive.
Summary of the invention
In view of this, the present invention proposes the communication means between a kind of chip internal processor, take too much system break resource and data can not be by the problem that in time receives even lose to solve to exist in the prior art.
Technical scheme of the present invention comprises,
A kind of chip internal processor sends the method for data to other processors:
Steps A, need receive in processor and each between the processor of data of its transmission and be respectively provided to few 1 sharing data area, each sharing data area is made up of n data storage block;
Wherein, n is the integer greater than 1;
Step B, a read pointer, a write pointer and an interrupt resources are set for each sharing data area;
Wherein read pointer is indicated next pending DSB data store block, and write pointer is indicated next idle data storage block;
Step C, processor judge according to read pointer and write pointer whether corresponding sharing data area also has the idle data storage block;
If step D sharing data area has idle DSB data store block, processor writes data the idle data storage block and revises write pointer according to the indication of write pointer;
Step e, processor send and interrupt, and the processor that notice needs to receive data receives data.
Further, described step C comprises:
Processor judges whether the DSB data store block that read pointer points to is the next DSB data store block of write pointer DSB data store block pointed, if judge no idle data storage block in the sharing data area; If not, judge that sharing data area has idle DSB data store block.
Wherein, if write pointer DSB data store block pointed is last DSB data store block of sharing data area, first DSB data store block that its next DSB data store block is a sharing data area.
Further, described step D comprises:
Processor writes write pointer DSB data store block pointed with data;
Revising write pointer makes it point to next DSB data store block;
Wherein, if write pointer DSB data store block pointed is last DSB data store block of sharing data area, first DSB data store block that its next DSB data store block is a sharing data area.
A kind of chip internal processor receives the method for data from other processors:
Processor sends the sharing data area reading of data of data from sending data processor to it;
Steps A, processor response send the interruption that data processor sends over;
Step B, processor judge according to the read pointer and the write pointer that interrupt corresponding sharing data area whether untreated data are arranged in this sharing data area;
If step C has untreated data, processor is handled the data in the DSB data store block of corresponding sharing data area according to read pointer and write pointer, revise read pointer;
If step D does not have untreated data, processor is not handled.
Further, described step B comprises:
Processor is the read pointer and the write pointer of this sharing data area relatively;
If read pointer is less than write pointer, untreated DSB data store block comprises the last data storage block of read pointer DSB data store block pointed to write pointer DSB data store block pointed; If read pointer is greater than write pointer, untreated DSB data store block comprises data block that read pointer the points to last data storage block to first data block in last data block in shared data zone and shared data zone to write pointer DSB data store block pointed; If read pointer equals write pointer, there is not untreated data block.
Further, described step C comprises: processor is the read pointer and the write pointer of this sharing data area relatively;
Processor reads the data in all untreated DSB data store block; The modification read pointer is the DSB data store block number of read pointer+this processing.
Further, described step C comprises:
Data in untreated DSB data store block of processor processing;
Judge whether read pointer points to this DSB data store block;
If read pointer points to this DSB data store block, judge whether to also have untreated DSB data store block; If untreated DSB data store block is arranged, revise read pointer, make it point to next untreated DSB data store block; If there is not untreated DSB data store block, revise read pointer, make it point to write pointer DSB data store block pointed;
If read pointer does not point to this DSB data store block, this data block is designated handles;
Wherein, whether described also have the determination range of untreated DSB data store block to be, if read pointer less than write pointer, determination range is the last data storage block of this DSB data store block to write pointer DSB data store block pointed; If read pointer is greater than write pointer, the last data storage block that determination range is this DSB data store block to first data block in last data block in shared data zone and shared data zone to write pointer DSB data store block pointed.
Technical scheme of the present invention is provided with a read pointer and a write pointer respectively to indicate the operating position of each DSB data store block in this sharing data area for each sharing data area, only distribute an interrupt resources for each sharing data area, the processor that sends data is after each DSB data store block that data is write in the sharing data area, send the processor that same interrupt notification receives data, when the processor of reception data responds this interruption, all untreatment data storage blocks in can the deal with data sharing data area, like this, even it is bigger in the data interaction handling capacity, the covering of interruption appears, when losing, also can effectively avoid the untimely of Data Receiving maybe can't receive data conditions.
Description of drawings
Fig. 1 is a communication means process flow diagram between the prior art chip internal different processor
Fig. 2 is the specific embodiment of the invention 1 process flow diagram
Fig. 3 is the specific embodiment of the invention 2 process flow diagrams
Fig. 4 is the specific embodiment of the invention 3 process flow diagrams
Embodiment
For clearly demonstrating technical scheme of the present invention, provide preferred embodiment below and be described with reference to the accompanying drawings.
The application scenarios of the preferred embodiments of the present invention 1,2,3 is the communication process between inner arm processor of mobile communication terminal baseband chip and the dsp processor, in each preferred embodiment, be used for arm processor and send intercommunication primitive for ARM is provided with a sharing data area BUFFER_A2D who comprises n data storage block in advance to dsp processor; Be used for dsp processor and send intercommunication primitive to arm processor for DSP is provided with a sharing data area BUFFER_D2A who comprises n data storage block, n is the integer greater than 1.
The present embodiment application scenarios is that arm processor sends intercommunication primitive to dsp processor in the mobile communication terminal baseband chip, idiographic flow as shown in Figure 2:
In the present embodiment, arm processor sends intercommunication primitive by BUFFER_A2D to dsp processor;
For BUFFER_A2D is provided with a read pointer CPD_R, a write pointer CPA_W and an interrupt resources MB_A2D;
In the present embodiment, read pointer and write pointer initial value all point to first DSB data store block of sharing data area, i.e. CPD_R=CPD_R=1;
1, after data send beginning, when arm processor sends intercommunication primitive at every turn, at first detects sharing data area and whether also have the idle data storage block;
Arm processor judges whether (CPA_W%n)+1 equals CPD_R, if execution in step 6, otherwise execution in step 4;
2, arm processor writes data the idle data storage block and revises write pointer according to the indication of write pointer;
The intercommunication primitive that arm processor will send writes the DSB data store block of write pointers point;
Revise write pointer,
CPA_W＝(CPA_W％n)+1。
3, arm processor sends and interrupts MB_A2D to dsp processor;
4, arm processor judges whether that its intercommunication primitive need send in addition, returns step 3 in this way, otherwise execution in step 5.
5, ARM finishes this data transmission procedure.
Specific embodiment 2
The present embodiment application scenarios is that the dsp processor in the baseband chip of mobile terminal receives the intercommunication primitive that arm processor sends, idiographic flow as shown in Figure 3:
In the present embodiment, dsp processor is from sharing data area BUFFER_A2D received communication primitive;
Be provided with a read pointer CPD_R, a write pointer CPA_W and an interrupt resources MB_A2D for this sharing data area in advance;
1, dsp processor response MB_A2D interrupts;
2, dsp processor judges that MB_A2D interrupts in the corresponding sharing data area whether untreated data being arranged;
Dsp processor is CPD_R and CPA_W relatively, if CPD_R less than CPA_W, execution in step 3, if CPD_R greater than CPA_W, execution in step 4, if CPD_R equals CPA_W, execution in step 6;
3, dsp processor reads the data storage BOB(beginning of block) that points to from the CPD_R data to the CPA_W-1 DSB data store block pointed; Execution in step 5;
4, dsp processor read the data storage BOB(beginning of block) that points to from CPD_R to last DSB data store block of sharing data area and from first data storage BOB(beginning of block) of sharing data area to CPA_W-1 the data the DSB data store block pointed;
5, dsp processor is revised CPD_R, the DSB data store block number of this processing of CPD_R=CPD_R+;
6, dsp processor finishes the process from arm processor received communication primitive.
Specific embodiment 3
The present embodiment application scenarios is that the arm processor in the baseband chip of mobile terminal receives the intercommunication primitive that dsp processor sends, idiographic flow as shown in Figure 4:
In the present embodiment, arm processor sends the sharing data area BUFFER_D2A received communication primitive of data to arm processor from the dsp processor that sets in advance;
Be provided with a read pointer CPA_R, a write pointer CPD_W and an interrupt resources MB_D2A for this sharing data area in advance;
1, arm processor response MB_D2A interrupts;
2, the arm processor operating system scheduling needs the task of received communication primitive;
3, arm processor judges that MB_D2A interrupts in the corresponding sharing data area whether untreated data being arranged;
Arm processor is CPA_R and CPD_W relatively, if CPA_R=CPD_W, judging in the sharing data area does not have untreated DSB data store block, execution in step 6, otherwise execution in step 4;
4, arm processor is handled the data in each DSB data store block of corresponding sharing data area, revises read pointer;
401, arm processor is handled the data in the untreated DSB data store block;
402, arm processor judges whether CPA_R points to this DSB data store block, if, execution in step 403, otherwise execution in step 406;
403, judge whether to also have untreated DSB data store block, if execution in step 404 is arranged, otherwise execution in step 405;
In this step, judge to also have the foundation of untreated DSB data store block to be:
Except that the DSB data store block of this processing, also has unmarked DSB data store block in the determination range for having handled.
404, revise CPA_R, make it point to next untreated DSB data store block, execution in step 5;
405, revise CPA_R, make it point to CPD_W DSB data store block pointed, execution in step 6;
406, this data block is designated handles;
Wherein, whether described also have the determination range of untreated DSB data store block to be, if CPA_R less than CPD_W, determination range is the last data storage block of this DSB data store block to CPD_W DSB data store block pointed; If CPA_R is greater than CPD_W, the last data storage block that determination range is this DSB data store block to first data block in last data block in shared data zone and shared data zone to CPD_W DSB data store block pointed.
5, ARM judges whether moving of task also needs deal with data, if execution in step 4, otherwise execution in step 6;
6, ARM finishes this data handling procedure.
In the present embodiment, arm processor is as receiving data processor, because ARM can operate external memory unit, therefore, in the ARM system data are carried out in the processing procedure, directly in sharing data area, data are handled and do not needed the primitive data read is handled in the ram space of himself again.Improved the storage space utilization factor, reduce the data-moving time and to the bus holding time, simultaneously, because the ARM system is the mode of operating system scheduling task run, different primitive have the different priorities task to be handled, therefore might not handle immediately after ARM receives data, but, when inter-related task is carried out, just data be handled by task scheduling.Because the task scheduling of ARM system and the influence of task priority, intercommunication primitive in the different pieces of information storage block may be handled by the task of different priorities, this will produce low priority task and handle position DSB data store block the preceding, and high-priority task handle the position after the situation of DSB data store block.High-priority task can be finished data processing earlier, if the direct CPA_R of modification can cause the discontinuous situation of idle data storage block after each task was handled its corresponding DSB data store block, in present embodiment step 3, ARM does not directly discharge this DSB data store block (revising CPA_R) after handling a data storage block, but judge before this DSB data store block, whether to also have untreated DSB data store block, if also have, then do not revise CPA_R, only this DSB data store block is designated " handling ", wait for after DSB data store block before it is handled in follow-up work and revise CPA_R again, effectively avoided the discontinuous situation of idle data storage block.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and obviously, those skilled in the art can carry out various changes and modification and not break away from the spirit and scope of the present invention the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (7)
1. a chip internal processor sends the method for data to other processors, it is characterized in that, comprising:
Steps A, need receive in processor and each between the processor of data of its transmission and be respectively provided to few 1 sharing data area, each sharing data area is made up of n data storage block;
Wherein, n is the integer greater than 1;
Step B, a read pointer, a write pointer and an interrupt resources are set for each sharing data area;
Wherein, the DSB data store block that the read pointer indication is pending, write pointer indication idle data storage block;
Step C, processor judge according to read pointer and write pointer whether corresponding sharing data area also has the idle data storage block;
If step D sharing data area has idle DSB data store block, processor writes data the idle data storage block and revises write pointer according to the indication of write pointer;
Step e, processor send and interrupt, and the processor that notice needs to receive data receives data.
2. a kind of chip internal processor according to claim 1 is characterized in that to the method for other processors transmission data described step C comprises:
Processor judges whether the DSB data store block that read pointer points to is the next DSB data store block of write pointer DSB data store block pointed, if judge no idle data storage block in the sharing data area; If not, judge that sharing data area has idle DSB data store block;
Wherein, if write pointer DSB data store block pointed is last DSB data store block of sharing data area, first DSB data store block that its next DSB data store block is a sharing data area.
3. a kind of chip internal processor according to claim 1 and 2 is characterized in that to the method for other processors transmission data described step D comprises:
Processor writes write pointer DSB data store block pointed with data;
Revising write pointer makes it point to next DSB data store block;
Wherein, if write pointer DSB data store block pointed is last DSB data store block of sharing data area, first DSB data store block that its next DSB data store block is a sharing data area.
4. a chip internal processor receives the method for data from other processors, it is characterized in that, comprising:
Processor sends the sharing data area reading of data of data from sending data processor to it;
Steps A, processor response send the interruption that data processor sends over;
Step B, processor judge according to the read pointer and the write pointer that interrupt corresponding sharing data area whether untreated data are arranged in this sharing data area;
If step C has untreated data, processor is handled the data in the DSB data store block of corresponding sharing data area according to read pointer and write pointer, revise read pointer;
If step D does not have untreated data, processor is not handled.
5. a kind of chip internal processor according to claim 4 is characterized in that from the method for other processors reception data described step B comprises:
Processor is the read pointer and the write pointer of this sharing data area relatively;
If read pointer is less than write pointer, untreated DSB data store block comprises the last data storage block of read pointer DSB data store block pointed to write pointer DSB data store block pointed; If read pointer is greater than write pointer, untreated DSB data store block comprises data block that read pointer the points to last data storage block to first data block in last data block in shared data zone and shared data zone to write pointer DSB data store block pointed; If read pointer equals write pointer, there is not untreated data block.
6. receive the method for data according to claim 4 or 5 described a kind of chip internal processors from other processors, it is characterized in that described step C comprises:
Processor is the read pointer and the write pointer of this sharing data area relatively;
Processor reads the data in all untreated DSB data store block; The modification read pointer is the DSB data store block number of read pointer+this processing.
7. receive the method for data according to claim 4 or 5 described a kind of chip internal processors from other processors, it is characterized in that described step C comprises:
Data in untreated DSB data store block of processor processing;
Judge whether read pointer points to this DSB data store block;
If read pointer points to this DSB data store block, judge whether to also have untreated DSB data store block; If untreated DSB data store block is arranged, revise read pointer, make it point to next untreated DSB data store block; If there is not untreated DSB data store block, revise read pointer, make it point to write pointer DSB data store block pointed;
If read pointer does not point to this DSB data store block, this data block is designated handles;
Wherein, whether described also have the determination range of untreated DSB data store block to be, if read pointer less than write pointer, determination range is the last data storage block of this DSB data store block to write pointer DSB data store block pointed; If read pointer is greater than write pointer, the last data storage block that determination range is this DSB data store block to first data block in last data block in shared data zone and shared data zone to write pointer DSB data store block pointed.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104657327A (en) * | 2013-11-18 | 2015-05-27 | 恩智浦有限公司 | Shared interrupt multi-core architecture for low power applications |
| WO2015089839A1 (en) * | 2013-12-20 | 2015-06-25 | 华为技术有限公司 | Method and device for processing messages in shared queue and receiving core |
| CN105550142A (en) * | 2015-12-07 | 2016-05-04 | 中国航空工业集团公司西安航空计算技术研究所 | Data integrity processing method in high and low-speed conversion interface |
| WO2020118721A1 (en) * | 2018-12-14 | 2020-06-18 | 华为技术有限公司 | Multi-processor system and inter-processor communication method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1472663A (en) * | 2002-07-30 | 2004-02-04 | 深圳市中兴通讯股份有限公司上海第二 | Method for delivering shared critical region data |
| US20070067511A1 (en) * | 2005-09-22 | 2007-03-22 | Charbel Khawand | Method and apparatus for sharing memory in a multiprocessor system |
| CN101105786A (en) * | 2006-07-14 | 2008-01-16 | 中兴通讯股份有限公司 | Double CPU communication method based on shared memory |
-
2009
- 2009-12-30 CN CN200910250832.8A patent/CN102117261B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1472663A (en) * | 2002-07-30 | 2004-02-04 | 深圳市中兴通讯股份有限公司上海第二 | Method for delivering shared critical region data |
| US20070067511A1 (en) * | 2005-09-22 | 2007-03-22 | Charbel Khawand | Method and apparatus for sharing memory in a multiprocessor system |
| CN101105786A (en) * | 2006-07-14 | 2008-01-16 | 中兴通讯股份有限公司 | Double CPU communication method based on shared memory |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104657327A (en) * | 2013-11-18 | 2015-05-27 | 恩智浦有限公司 | Shared interrupt multi-core architecture for low power applications |
| US9996145B2 (en) | 2013-11-18 | 2018-06-12 | Nxp B.V. | Shared interrupt multi-core architecture for low power applications |
| CN104657327B (en) * | 2013-11-18 | 2018-10-09 | 恩智浦有限公司 | The multicore architecture of shared interruption for low-power consumption application |
| WO2015089839A1 (en) * | 2013-12-20 | 2015-06-25 | 华为技术有限公司 | Method and device for processing messages in shared queue and receiving core |
| CN105264499A (en) * | 2013-12-20 | 2016-01-20 | 华为技术有限公司 | Method and device for processing messages in shared queue and receiving core |
| CN105264499B (en) * | 2013-12-20 | 2018-03-13 | 华为技术有限公司 | Message treatment method, device and reception core in a kind of shared queue |
| CN105550142A (en) * | 2015-12-07 | 2016-05-04 | 中国航空工业集团公司西安航空计算技术研究所 | Data integrity processing method in high and low-speed conversion interface |
| WO2020118721A1 (en) * | 2018-12-14 | 2020-06-18 | 华为技术有限公司 | Multi-processor system and inter-processor communication method |
| CN111742306A (en) * | 2018-12-14 | 2020-10-02 | 华为技术有限公司 | Multiprocessor system and communication method between processors |
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Effective date of registration: 20190326 Address after: 361006 Xiamen Free Trade Pilot Area, Xiamen, Fujian Province, Unit X, 8th Floor, Unit 05, Building D, Xiamen International Shipping Center, 97 Xiangyu Road, Xiamen Section Patentee after: Xinxin Finance Leasing (Xiamen) Co.,Ltd. Address before: 201203 Building 1, exhibition hall, 2288 lane, 2288 Chong, road, Zhangjiang hi tech park, Shanghai Patentee before: SPREADTRUM COMMUNICATIONS (SHANGHAI) Co.,Ltd. |
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Application publication date: 20110706 Assignee: SPREADTRUM COMMUNICATIONS (SHANGHAI) Co.,Ltd. Assignor: Xinxin Finance Leasing (Xiamen) Co.,Ltd. Contract record no.: X2021110000009 Denomination of invention: A communication method between processors in chip Granted publication date: 20150415 License type: Exclusive License Record date: 20210317 |
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