CN107943739B

CN107943739B - FPGA-based multi-group SPI code signal detection and verification method

Info

Publication number: CN107943739B
Application number: CN201711262681.9A
Authority: CN
Inventors: 王珺; 张靓; 郭冬梅; 李媛媛
Original assignee: Shanghai Radio Equipment Research Institute
Current assignee: Shanghai Radio Equipment Research Institute
Priority date: 2017-12-04
Filing date: 2017-12-04
Publication date: 2021-01-19
Anticipated expiration: 2037-12-04
Also published as: CN107943739A

Abstract

A detection and verification method for multiple groups of SPI code signals based on FPGA utilizes a high-speed sampling clock to store SPI clocks, SPI data and SPI latching signals in each group of SPI signals into a first-in first-out queue FIFO in a bit-by-bit mode, deburring is carried out, burr-free SPI clocks, SPI data and SPI latching signals are output, corresponding SPI data are stored into a random access memory RAM at the moment that each SPI clock jumps from low level to high level, cached SPI data are locked at the moment that each SPI latching signal jumps from low level to high level, locked SPI data are played back, corresponding readback data are output at the moment that each SPI clock jumps from high level to low level, the readback data are stored into files and are compared with original data. The invention avoids the data loss caused by the time delay generated in the deburring processing process, solves the problem of abnormal data communication caused by the interference of a plurality of groups of SPI signals, can determine the position of data error, and has the advantages of simple design, good universality and easy engineering realization.

Description

FPGA-based multi-group SPI code signal detection and verification method

Technical Field

The invention relates to a multi-group SPI code signal detection and verification method based on an FPGA.

Background

In a data communication system, various standards exist in interfaces of peripheral electronic devices, and known interface protocols have the problems of low speed, complex protocols and the like. The SPI bus is a serial bus that can overcome the above-mentioned disadvantages, and better meets the requirements for fast, simple, and reliable data communication.

According to the working principle of the SPI, an SPI interface is designed into a universal peripheral expansion port (namely an SPI expansion port) in the FPGA, and the expansion port is used for finishing the data reading function. Or the FPGA-based SPI interface connection is realized by combining the flexibility of FPGA programming and the usability of the SPI bus, and FLASH is accessed.

Most SPI port designs based on FPGA are applied to the aspects of establishing a group of data communication links, controlling data transmission and the like, and when a plurality of groups of SPI clocks, SPI data and SPI latching signals are simultaneously in data communication, interference signals exist on the clocks, the data and the latching signals, so that data communication is abnormal.

Disclosure of Invention

The invention provides a multi-group SPI code signal detection and verification method based on an FPGA (field programmable gate array), which avoids data loss caused by time delay generated in a deburring process, solves the problem of abnormal data communication caused by interference signals existing on a clock, data and a latching signal under the condition that data communication is simultaneously carried out on a plurality of groups of SPI clocks, SPI data and SPI latching signals, can determine the position of data error and carry out data retransmission, and is simple in design, good in universality and easy for engineering realization.

In order to achieve the above object, the present invention provides a method for detecting and verifying multiple sets of SPI code signals based on an FPGA, comprising the steps of:

step S1, the SPI clock, the SPI data and the SPI latching signal in each group of SPI signals are respectively stored in a first-in first-out queue FIFO in the FPGA according to the position by utilizing a high-speed sampling clock;

step S2, sequentially reading out the SPI clock, the SPI data and the SPI latching signal from the first-in first-out queue FIFO, removing burrs, and outputting the SPI clock, the SPI data and the SPI latching signal without burrs;

step S3, in the signals output by the first-in first-out queue FIFO, at each time when the SPI clock jumps from low level to high level, the corresponding SPI data is stored in a random access memory RAM in the FPGA;

step S4, locking the buffered SPI data at the time when each SPI latching signal jumps from low level to high level;

step S5, replaying the SPI data locked in step S4, and outputting corresponding SPI data at each time when the SPI clock jumps from high level to low level to form readback data;

and step S6, storing the read-back data into a file, comparing the file with the original data, recording the error position of the data if the read-back data is inconsistent with the original data, counting the number of error data codes, and repeating the data transmission.

The frequency of the high-speed sampling clock is 4 times of the frequency of the input SPI clock.

The deburring method comprises the following steps: carrying out binary judgment on each acquired signal;

when the acquired signal is '0', continuously judging that the acquired signal is equal to '0', and when the acquired signals acquired for 4 times are '0', outputting the signal as '0', otherwise, keeping the state of the signal unchanged;

and when the acquired signal is '1', continuously judging that the acquired signal is equal to '1', and when the acquired signals acquired for 4 times are '1', outputting the signal as '1', otherwise, keeping the state of the signal unchanged.

The invention has the following advantages:

1. the SPI clock, the SPI data and the SPI latching signals in each group of SPI signals are respectively stored in a first-in first-out queue FIFO for caching by using a high-speed sampling clock, and the cached SPI clock, the cached SPI data and the cached SPI latching signals can finish deburring processing, so that data loss caused by time delay generated in the deburring processing process is avoided;

2. directly using a glitch-free SPI clock signal and SPI data, and storing the corresponding SPI data into a Random Access Memory (RAM) at each time when the SPI clock jumps from a low level to a high level;

3. when the SPI latching signal is effective, corresponding SPI data are output at each time of the SPI clock when the SPI clock jumps from a high level to a low level, read-back data are stored into a file and are compared with original data, collection and verification of the group of SPI data are completed, the position of current data errors can be displayed, the number of error data codes is automatically counted, and the data transmission process is started again.

Drawings

Fig. 1 is a flowchart of a method for detecting and verifying multiple sets of SPI code signals based on an FPGA according to the present invention.

FIG. 2 is a schematic diagram of multiple sets of SPI signal acquisition.

FIG. 3 is a timing diagram of each set of SPI signals.

Fig. 4 is a simulation result in which the deburring process is not performed.

Fig. 5 is a simulation result of the deburring process.

Detailed Description

The preferred embodiment of the present invention will be described in detail below with reference to fig. 1 to 5.

As shown in fig. 1, the present invention provides a method for detecting and verifying multiple sets of SPI code signals based on an FPGA, comprising the following steps:

As shown in fig. 2 to 5, an embodiment of the present invention includes the following steps:

and step S1, storing the SPI clock, the SPI data and the SPI latching signal in each group of SPI signals into a first-in first-out queue FIFO in a bit mode by using the high-speed sampling clock.

The frequency of the high-speed sampling clock is 4 times of the frequency of the input SPI clock, the system processing requirement can be met, the sampling rate can be higher, and only more redundant data can be obtained, so that the processing capacity of the detection system is influenced. Buffering the SPI clock, the SPI data and the SPI latching signal can avoid data loss caused by time delay generated in the subsequent deburring processing process.

As shown in fig. 2, in this embodiment, there are 20 sets of SPI signals that need to be subjected to code signal acquisition and verification, and each set of SPI signals includes a one-bit clock signal, a one-bit data signal, a one-bit latch signal, and one-bit readback data obtained after processing. The timing relationship satisfied by the 4-way code signals of each set of SPI signals is shown in fig. 3. Each group of SPI codes contains 100-bit serial data, so the memory depth of the FIFO of the clock signal, the data signal, the latch signal, and the readback data is 100, and the memory bit width is 1 bit. The latch signal is always low during the data code transmission period, and is changed into high level before the rising edge of the next SPI clock after the data code transmission is finished arrives, and the SPI clock meets the requirement of data establishment and retention time and lasts for one SPI clock period.

And step S2, sequentially reading the SPI clock, the SPI data and the SPI latching signal from the first-in first-out queue FIFO, carrying out deburring processing, and outputting the SPI clock, the SPI data and the SPI latching signal without burrs.

The deburring treatment combines binary judgment and burr effective time setting detection treatment: the glitch refers to a false signal on the signal line, and since a plurality of sets of SPI signals are simultaneously subjected to rapid inversion of signals '0' and '1', and there is interference between each other, a result obtained after the signal originally input as '0' may be acquired as '1', and a result obtained after the signal originally input as '1' may be acquired as '0'. The binary judgment is carried out on each acquired signal by utilizing the characteristic that the duration time of an effective data signal is always far longer than that of a burr signal, when the acquired signal is '0', the acquired signal is continuously judged to be equal to '0', when the acquired signals acquired for 4 times are '0', the signal is output to be '0', otherwise, the state of the signal is kept unchanged. Similarly, when the acquired signal is '1', the acquired signal is continuously judged to be equal to '1', and when the acquired signals acquired for 4 times are all '1', the signal is output to be '1', otherwise, the state of the signal is kept unchanged.

SPI clock signal, SPI data signal and SPI latch signal all are 1 bit's signal, and the SPI clock signal, SPI data signal and the SPI latch signal of no burr can directly carry out sampling process.

Fig. 4 shows the simulation result without the deburring process. It can be seen from the figure that before the present invention is adopted, the first group of SPI code signals are affected by the random inversion of the second group of SPI code signals, and false pulses appear on the first group of SPI clock signals SPI _ CLK _1, SPI DATA signals SPI _ DATA _1, and SPI LATCH signals SPI _ LATCH _1, failing to correctly resolve and identify the first group of SPI code information. The erroneous SPI latch signal triggers a data code read BACK while the data code read BACK SPI _ BACK _1 has erroneous data.

Fig. 5 shows the simulation result after the deburring process. It can be seen from the figure that, after the invention is adopted, although the first group of SPI code signals are influenced by the random inversion of the second group of SPI code signals, false pulses appear on the inputs of the first group of SPI clock signals, the SPI data signals and the SPI latch signals, the output SPI clock signals, the SPI data signals and the SPI latch signals after the deburring process do not have the false pulses, and the first group of SPI code information is correctly analyzed and identified. The correct SPI latching signal triggers one-time data code read-back, and the read-back data code is consistent with the original data.

And step S3, in the signals output by the first-in first-out queue FIFO, at the time when each SPI clock jumps from '0' to '1', the corresponding SPI data is stored in the RAM.

Step S4, locking the buffered SPI data at the time when each SPI latching signal jumps from '0' to '1';

step S5, playing back the locked SPI data, and outputting the corresponding SPI data at the time when each SPI clock jumps from '1' to '0', so as to form readback data;

step S6, storing the read-back data into a file, and comparing the file with the original data;

for example, if the transmitted data is a ten-bit binary number "01011010", and the data output in step S5 is also a ten-bit binary number "01011010", the result is consistent; if the data bit number is different from the data content, the data bit number is inconsistent with the data content, if the data bit number is inconsistent with the data content, the error position of the current data is recorded, the number of error data codes is counted, and the data transmission is carried out again.

Thus, the collection and verification of a group of SPI data are completed. And circularly executing the step S1 to the step S6, playing back the SPI data corresponding to the group after each group of SPI latching signals are effective, storing the read-back data into a file, and comparing the file with the original data.

The invention can simultaneously acquire and verify a plurality of groups of SPI data, caches SPI clock signals, SPI data signals and SPI latching signals by utilizing a first-in first-out queue FIFO, and simultaneously deburs the signals, thereby avoiding the data loss caused by the delay generated in the deburring processing process.

While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be determined from the following claims.

Claims

1. A multi-group SPI code signal detection and verification method based on FPGA is characterized by comprising the following steps:

2. The FPGA-based multiple-group SPI code signal detection and verification method of claim 1, characterized in that the frequency of said high-speed sampling clock is 4 times of the frequency of the input SPI clock.

3. The FPGA-based multi-group SPI code signal detection and verification method of claim 1, characterized in that the deburring processing method comprises the following steps: carrying out binary judgment on each acquired signal;