JPS57134733A - Data transfer checking system in data processor - Google Patents

Abstract

PURPOSE:To increase the reliability and maintainability, by making the check of the number of data transfers in high speed at each data transfer and stopping a counter counting the number of data transfers. CONSTITUTION:A delay circuit 1-2 forms a signal (c) after delay of a transmission informing signal (a) and a check timing signal (d) delaying the signal (c). If a noise takes place in a reception response signal (b) from a receiver, an input (g) of a counter 1-6 geberates a count pulse more than that at normal state by one. Since a calculated pulse (f) of the input of a counter 1-5 is normal, a comparison circuit output (j) of outputs (h), (i) of both counters is at ''1''. A data transfer check timing (d) sets the comparison output (j) to an error detection FF 1-8, the control signal (e) of the output is at ''0'' and count pulses (f), (g) are suppressed. Thus, the number of bytes from the start of transfer to the error generation can be detected with the count value at failure generation.