JPS5852712A - Data transfer processor - Google Patents

Abstract

PURPOSE:To improve reliability by executing a check on the number of data transferred at a high speed at every interval of the data transfer, and stopping the counting of a counter in case of the occurrence of a fault. CONSTITUTION:A data transmission information signal (a) is outputted as a timing signal (c) through a delay circuit 1-2. A reception information signal (b), on the other hand, is inputted to an AND gate 1-4 at the same timing with (c). During normal operation, an equal number of outputs (f) and (g) of the signals (c) and (d) are outputted from counters 1-5 and 1-6 at the same timing. If the number of pulses (b) is one less and pulses like (m) are inputted, the counters have different values (h) and (i), so a dissidence signal of timing (j) is outputted. Then, the output l of an error detecting flip-flop 1-8 is turned on to stop the counting of the counters 1-5 and 1-6. Further, even if the answer signal contains a noise with a level lower than a prescribed level like (n), the counting is carried on normally.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer processing device, and more specifically, to a data transfer processing device with improved data transfer checking method.

First, the data processing device including the transmitting device and the receiving device will be referred to as the data transfer processing device.

In a data transfer processing device that transfers data at high speed on an interface between data processing devices, in order to improve the transfer rate, conventionally, the sending side sends a data transmission notification signal during data transfer, and as a result, the receiving side sends a response signal. The number of data transfers is checked by simply counting the number of these two signals and comparing the results, without interlocking the next data transmission notification signal, regardless of whether or not the next data transmission notification signal is returned.

Therefore, since the repetition period of the data transmission notification signal and reception response signal is shorter than the delay of the transmission cable, the transmission notification for the next data is sent before the reception response signal for the data transmission notification signal reaches the data transmission side. As a result, in terms of time, the number of data transfers had to be checked at the end of the data transfer. This means that if an error occurs in data transfer during data transfer, the number of data transferred before the error occurs cannot be determined, and a lot of time is spent investigating the error.

Furthermore, since the pulse width is not checked on the receiving side in parallel with the above, there is a drawback that the counter malfunctions due to noise.

An object of the present invention is to eliminate the above-mentioned drawbacks and to provide highly reliable data transfers by checking the number of data transfers at high speed every time data is transferred, and by stopping the counter that counts the number of data transfers when an abnormality occurs. An object of the present invention is to provide a data transfer processing device with excellent maintainability.

In order to achieve the above object, the Σ data transfer processing device according to the present invention calculates the counted value of the data transmission notification signal counted by the first counting means and the counted value of the data transmission notification signal by the second counting means in the transmitting side device. In a data transfer processing device that checks the number of data transfers by comparing the count value of a reception response signal from a receiving side device, the data transmission notification signal is transmitted from the time when this signal is sent to the receiving side that receives the data transfer processing device. means for delaying the reception response signal from the device by the time required to receive it, and means for controlling the input of the data transmission notification signal and reception response signal to the first and second counting means, A pulse width detection circuit for detecting the pulse width of the data transmission notification signal is configured to drive the first counting means according to the output of the delay means and detect the outputs of the first and second counting means each time counting is performed. are sequentially compared, and if a mismatch is detected, or if an abnormality is detected in the pulse width detection circuit, the control means
The second counting means is configured to stop counting.

According to the above configuration, when a failure occurs, the location of the data byte is immediately known, so it is excellent in maintainability, the number of data transfers is checked every time it is transferred, and it is much more resistant to noise than before. Reliability is improved and the objectives of the invention are fully achieved.

Hereinafter, the present invention will be explained in more detail with reference to the drawings and the like.

FIG. 1 is a block diagram showing an embodiment of a data transfer processing device according to the present invention.

In the figure, 1 is the sending side device of the data transfer processing device, 2 is the sending side device of the data transfer processing device;
is sent to the opposing receiving device.

In the superstition side device 1, 1-1 is a data transfer control circuit, which generates a data transmission notification signal a when transferring data.

1-2 is a delay circuit, in which the data transmission notification signal a
A signal C, which is delayed by the time required from the sending of the signal a to the time required to receive the reception response signal from the opposing data processing device that received it, and a signal d, which is further delayed by a certain period of time from the signal C, are generated. do.

1-3 is an AND game 1-11 that calculates the logical product of the control signal e, which will be described later, the tsuta control signal, and the output C of the 34% circuit 1-2.
-4 is an AND gate that performs the logical product of the control signal e, the control signal, and the response signal S returned from the data transfer control circuit 2-1 on the receiving side of the opposing data processing device.These AND gates 1 -3.1-4 constitutes a control means.

1-5 is a bt counter that counts the output of the AND gate 1-3, and l-6 is a counter that counts the output g of the AND gate 1-4.

1-7 is the comparison circuit, and the output of the digitizer 1-5 is 8t.
After receiving the output i of unit a 1-6, the two are compared. This comparison in the comparison circuit 1-7 is performed every time the counter 1-5.1-6 counts, and each time a match/mismatch information is output.

1-8 is an error detection flip-flop, and delay circuit 1
The output j of the comparison circuit 1-7 is sampled at the timing when the output d of -2 is activated. flip 70
As mentioned above, the output e of the knob 1-8 is connected to the AND gate 1-8.
3 and 1-4, and when an error is detected, counter 1
-5 and 1-6 input signals f and g are suppressed.

On the other hand, in the receiving side device, 2-2 is a pulse width detection circuit for the data transmission notification signal a, which generates a counting clock of the counter and a suppressing signal k to open the gate of Lg when the width is a specified width.

In the above configuration, if an abnormality occurs in the data receiving device during data transfer and the number of transmission notification signals a and reception notification signal s differs, or if noise n occurs in reception response number 46 during operation. works as follows.

This will be explained with reference to the time chart shown in FIG.

As shown in FIG. 2, the data transmission notification signal a is transmitted to the delay circuit 1.
-2 and is output as timing C, while the reception notification signal S is outputted as AND gate l-2 at the same timing as C.
Enter 4.

During normal operation, fs is the output of c and b, respectively.
g is a counter for the same number of pieces at the same timing 1-5.1-6
It is output from

Now, when the V of b is one less and a pulse like m is input, the counter value h1 l is different, so timing j outputs a mismatch signal, that is, turns on, and the output l of error detection flip-flop 1-8 turns off. So counter 1-5
．． Stop counting 1-6.

Furthermore, even if noise below the specified level occurs, such as in the response signal b IICn, the counting continues normally because it does not turn on the output k of the pulse width detection circuit.

With the above configuration, if a failure occurs, the data transfer count stops at 1 as soon as the failure is detected, so the location of the data byte that caused the failure can be immediately identified. Furthermore, since the pulse width is guaranteed, there is no possibility of malfunction due to noise below the specified level.

As explained in detail above, the present invention delays the data transmission notification signal to the same timing as the received signal that is sent back, and provides a circuit for detecting the pulse width of the notification signal on the data receiving side. It is possible to check the number of transfers, which has a great effect on improving reliability and maintainability.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing an embodiment of a data transfer processing device according to the present invention, and FIG. 2 is a waveform diagram for explaining the operation of the device. 1... Data transmitting side device 2... Data receiving side device 1-1.2-1... Data transfer control circuit 1-2...
Delay circuits 1-3, 1-4...AND gates. 1-5.1-6-... Counter 1-7... Comparison circuit 1-8-... Error detection flip-flop 2-2... Pulse width detection circuit Patent applicant NEC Corporation

Claims (1)

[Claims] In the transmitting side device, the number of data transfers is determined by comparing the counted value of the data transmission notification signal counted by the first counting means and the counted value of the reception response signal from the receiving side device counted by the second counting means. In the data transfer processing device, means for delaying the data transmission notification signal by the time required from the time when the signal is sent until receiving a reception response signal from the receiving side device that received the data transmission notification signal; Means for controlling the input of the transmission notification signal and the reception response signal to the first and second counting means is provided, a pulse width detection circuit for detecting the pulse width of the data transmission notification signal is provided in the receiving side device, and the delay The first counting means is driven by the output of the means, and the outputs of the first and second counting means are sequentially compared each time counting is performed, and if a discrepancy is detected or an abnormality is detected in the pulse width detection circuit. In this case, the control means controls the first and second
1. A data transfer processing device, characterized in that the data transfer processing device is configured to stop the counting of the counting means.