JPS62200432A - Computer unit having multiple computers - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a computer computer system having a plurality of computers according to the preamble of claim 1. Computer systems in which data is transmitted serially in the form of data blocks between individual computers can be used, for example, in electrical control systems.

BACKGROUND OF THE INVENTION It is then necessary to be able to ascertain as easily as possible whether data transmission is error-free and trouble-free. In particular, the receiving computer must be able to ascertain whether the sending computer is still transmitting data and determine whether the sending computer is functioning properly. Communicating computers can also be provided in various control devices, in which case also it is desirable to check the transmission and functionality of the transmitting computer.

For checking the received data, additional check bits can each be provided which are calculated from the data.

The required calculations and the transmission of additional check bits are significantly more expensive. According to another checking means, the received data is transmitted once again to the sending computer and a data comparison is performed. This type of one-night test requires a significant portion of the available computing time. Testing methods of this type are therefore never suitable for many applications.

Effect of the Invention The computer device of the present invention having the requirements set forth in the characteristic part of claim 1 is different from the prior art in that the computer device of the present invention can process data by simple means, that is, by dividing the data into data blocks each having a predetermined number. Transmission checks can be performed. In this case, it is not necessary to allocate check bits for each individual data item; rather, it is sufficient for the counters to operate simultaneously during the serial reception of data in the receiving computer. The counting state of the counter must reach a predetermined value at the end of each data block. If the comparison result between the predetermined number of data and the actually counted data number does not match, it indicates that there was a malfunction in the data transmission or in the sending computer.

In addition to checking the number of data, in an advantageous embodiment, a marking bit is transmitted at the beginning of a data block, the data block is transmitted periodically, and the receiving computer detects the occurrence of a marking bit within a predetermined time interval that is greater than or equal to the cycle time. It has an additional function of monitoring and generating an error signal if the marking bit does not arrive. To function and work properly, if you configure the data block to be transmitted periodically at a given time interval, the marking bit must appear at the beginning of the block as periodically as the sending side. It won't happen. If this marking bit does not disappear within a predetermined duration, it also indicates that erroneous operation of the function exists. An error signal generated therefrom can trigger an emergency operation. Thereby, for example, alternative values of the data to be received are further processed. It is also possible to trigger an acoustic or optical alarm signal at the same time.

As soon as a temporary fault appears and the computer system is verified, computer operation transitions to normal functioning operation.

EXAMPLES The present invention will be explained in detail below using examples shown in the drawings.

FIG. 1 is a block circuit diagram of a computer device according to the present invention. The control device SG shown in FIG. 1 has a computer arrangement with two computers CI and C2, which are connected via control lines Sl and 82 to a warning signal indicator W. The two computers CI and 02 exchange data serially with each other via a data bus D. The data are grouped into data blocks having the same number of data. A predetermined number A of data are arranged in each data block. The computer C1 or C2 which performs reception each time counts the received data and at the end of the data block, a predetermined number of A
6. Check whether the number Z matches the actually transmitted number Z.
In case of mismatch, for example, the attached control line Sl or S
An error signal FS is sent out via 2. This error signal F
'S can also be used within the computer to invoke emergency action functions.

Next, the progress of the test performed by the receiving computer will be explained using the flowchart shown in FIG.

The counter of the receiving computer starts from the counting state ZS and is decremented by one for each incoming data until the counting state becomes ZS=O. As long as the counting state does not reach the zero value, it is constantly checked whether the received data is marking bit B or not. If the marking bit is not B, the counting state is further subtracted until it reaches ZS = O. Then, the counting state @ZS is set to the value A indicating the predetermined number of data for each data block, and then the received data is the marking bit B.

If marking bit B, note bit M is 1
is set to The counting state ZS is again subtracted by another incoming data until the counting state becomes ZS=0 again.

In the case of a faulty function, the counting state is likewise initially set to the value A in the counting state ZS=O.

However, in the case of a failure, the next received data does not contain marking bit B. As a result, the note bit M is set to zero and the error signal FS is triggered.

The error signal FS indicates an erroneous transmission condition and initiates a corresponding emergency action or alarm signal.

In the case of a fault, the marking bit B which appears when the counter count ZS is not yet zero likewise triggers the error signal FS. In this case as well, the counting state ZS is first set to the starting value A and the note bit M is cleared.

The number Z of data actually received in this way and the predetermined number A
are compared and an error signal is triggered in case of a mismatch. In the case of a discrepancy, this means that the marking bit B does not appear in the correct position with respect to the respective counting state, so that an erroneous operation is identified.

Corresponding to the flow diagram shown in FIG. 3, the periodic occurrence of note bits M is monitored at the same time. In that case, it is always possible to check whether the note bit M is erased after a fixed time interval, for example every 50 m5. If note bit M is erased, there is an error in the function. Because, due to periodic data transmission,
This is because at least the note bit M for indicating the start of a data block must be set within, for example, 50m5. If, after the expiration of this exemplary time interval, the note bit M is still zero, then the error signal FS is triggered.

On the other hand, if note bit M is non-zero, it means that note bit transmission is functioning normally.

Effects of the Invention By combining the monitoring of the note bits M with the monitoring of the number of received data Z, it is possible in many fields of application to fully check the functionality of a computer device in a very simple manner.

[Brief explanation of drawings]

FIG. 1 is a schematic block circuit diagram of a computer device according to the present invention, FIG. 2 is a flowchart for explaining a data count check, and FIG. 3 is a flowchart for explaining a periodic check of marking bits. S1, S2...Control line, CI, C2...Computer, D...Data bus, W...Alarm signal indicator, SG...Control device.

Claims (1)

[Scope of Claims] 1. In a computer system having a plurality of computers in which the exchange of data organized into data blocks between computers is carried out serially, and each time the data exchange is checked in the receiving computer, each transmitted data A block includes a predetermined number (A) of data, and the data receiving computer (C1; C2) calculates the number of data (Z) received within one data block and the predetermined number (A).
), and in case of discrepancy, generates an error signal (FS). 2. A marking bit (B) is transmitted at the beginning of the data block, the data block is transmitted periodically, and the receiving computer (C1; C2) monitors the occurrence of the marking bit (B) within a predetermined time interval. 2. A computer device having a plurality of computers according to claim 1, wherein said predetermined time interval is greater than or equal to a cycle time and an error signal (FS) is generated if a marking bit (B) does not arrive. 3. A fault signal (FS) initiates an emergency operation and/or triggers an alarm signal, claim 1.
A computer device comprising a plurality of computers according to item 1 or 2. 4. Even after the formation of the error signal (FS), the transmission of the data block is constantly checked, and if the data reception is proper, the operation returns to normal functioning.
A computer device comprising a plurality of computers according to any one of items 3 to 3.